[mirror_ubuntu-hirsute-kernel.git] / arch / arm64 / boot / dts / zte / zx296718.dtsi

/*
 * Copyright 2016 ZTE Corporation.
 * Copyright 2016 Linaro Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/zx296718-clock.h>

/ {
	compatible = "zte,zx296718";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			clocks = <&topcrm A53_GATE>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			clocks = <&topcrm A53_GATE>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "psci";
			clocks = <&topcrm A53_GATE>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "psci";
			clocks = <&topcrm A53_GATE>;
			operating-points-v2 = <&cluster0_opp>;
		};
	};

	cluster0_opp: opp-table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <500000>;
		};

		opp-648000000 {
			opp-hz = /bits/ 64 <648000000>;
			clock-latency-ns = <500000>;
		};

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			clock-latency-ns = <500000>;
		};

		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			clock-latency-ns = <500000>;
		};

		opp-1188000000 {
			opp-hz = /bits/ 64 <1188000000>;
			clock-latency-ns = <500000>;
		};
	};

	clk24k: clk-24k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000>;
		clock-output-names = "rtcclk";
	};

	osc32k: clk-osc32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "osc32k";
	};

	osc12m: clk-osc12m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12000000>;
		clock-output-names = "osc12m";
	};

	osc24m: clk-osc24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc24m";
	};

	osc25m: clk-osc25m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "osc25m";
	};

	osc60m: clk-osc60m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <60000000>;
		clock-output-names = "osc60m";
	};

	osc99m: clk-osc99m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <99000000>;
		clock-output-names = "osc99m";
	};

	osc125m: clk-osc125m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
		clock-output-names = "osc125m";
	};

	osc198m: clk-osc198m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <198000000>;
		clock-output-names = "osc198m";
	};

	pll_audio: clk-pll-884m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <884000000>;
		clock-output-names = "pll_audio";
	};

	pll_ddr: clk-pll-932m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <932000000>;
		clock-output-names = "pll_ddr";
	};

	pll_hsic: clk-pll-960m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <960000000>;
		clock-output-names = "pll_hsic";
	};

	pll_mac: clk-pll-1000m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <1000000000>;
		clock-output-names = "pll_mac";
	};

	pll_mm0: clk-pll-1188m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <1188000000>;
		clock-output-names = "pll_mm0";
	};

	pll_mm1: clk-pll-1296m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <1296000000>;
		clock-output-names = "pll_mm1";
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	gic: interrupt-controller@2a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x02a00000 0x10000>,
		      <0x02b00000 0xc0000>;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		aon_sysctrl: aon-sysctrl@116000 {
			compatible = "zte,zx296718-aon-sysctrl", "syscon";
			reg = <0x116000 0x1000>;
		};

		uart0: uart@11f000 {
			compatible = "arm,pl011", "arm,primecell";
			arm,primecell-periphid = <0x001feffe>;
			reg = <0x11f000 0x1000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24m>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		sd0: mmc@1110000 {
			compatible = "zte,zx296718-dw-mshc";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x01110000 0x1000>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <32>;
			data-addr = <0x200>;
			fifo-watermark-aligned;
			bus-width = <4>;
			clock-frequency = <50000000>;
			clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
			clock-names = "biu", "ciu";
			max-frequency = <50000000>;
			cap-sdio-irq;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
			sd-uhs-sdr104;
			sd-uhs-ddr50;
			status = "disabled";
		};

		sd1: mmc@1111000 {
			compatible = "zte,zx296718-dw-mshc";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x01111000 0x1000>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <32>;
			data-addr = <0x200>;
			fifo-watermark-aligned;
			bus-width = <4>;
			clock-frequency = <167000000>;
			clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
			clock-names = "biu", "ciu";
			max-frequency = <167000000>;
			cap-sdio-irq;
			cap-sd-highspeed;
			status = "disabled";
		};

		dma: dma-controller@1460000 {
			compatible = "zte,zx296702-dma";
			reg = <0x01460000 0x1000>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24m>;
			clock-names = "dmaclk";
			#dma-cells = <1>;
			dma-channels = <32>;
			dma-requests = <32>;
		};

		lsp0crm: clock-controller@1420000 {
			compatible = "zte,zx296718-lsp0crm";
			reg = <0x01420000 0x1000>;
			#clock-cells = <1>;
		};

		lsp1crm: clock-controller@1430000 {
			compatible = "zte,zx296718-lsp1crm";
			reg = <0x01430000 0x1000>;
			#clock-cells = <1>;
		};

		vou: vou@1440000 {
			compatible = "zte,zx296718-vou";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x1440000 0x10000>;

			dpc: dpc@0 {
				compatible = "zte,zx296718-dpc";
				reg = <0x0000 0x1000>, <0x1000 0x1000>,
				      <0x5000 0x1000>, <0x6000 0x1000>,
				      <0xa000 0x1000>;
				reg-names = "osd", "timing_ctrl",
					    "dtrc", "vou_ctrl",
					    "otfppu";
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
					 <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
				clock-names = "aclk", "ppu_wclk",
					      "main_wclk", "aux_wclk";
			};

			vga: vga@8000 {
				compatible = "zte,zx296718-vga";
				reg = <0x8000 0x1000>;
				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&topcrm VGA_I2C_WCLK>;
				clock-names = "i2c_wclk";
				zte,vga-power-control = <&sysctrl 0x170 0xe0>;
				status = "disabled";
			};

			hdmi: hdmi@c000 {
				compatible = "zte,zx296718-hdmi";
				reg = <0xc000 0x4000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
				clocks = <&topcrm HDMI_OSC_CEC>,
					 <&topcrm HDMI_OSC_CLK>,
					 <&topcrm HDMI_XCLK>;
				clock-names = "osc_cec", "osc_clk", "xclk";
				#sound-dai-cells = <0>;
				status = "disabled";
			};

			tvenc: tvenc@2000 {
				compatible = "zte,zx296718-tvenc";
				reg = <0x2000 0x1000>;
				zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
				status = "disabled";
			};
		};

		topcrm: clock-controller@1461000 {
			compatible = "zte,zx296718-topcrm";
			reg = <0x01461000 0x1000>;
			#clock-cells = <1>;
		};

		sysctrl: sysctrl@1463000 {
			compatible = "zte,zx296718-sysctrl", "syscon";
			reg = <0x1463000 0x1000>;
		};

		emmc: mmc@1470000{
			compatible = "zte,zx296718-dw-mshc";
			reg = <0x01470000 0x1000>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			zte,aon-syscon = <&aon_sysctrl>;
			bus-width = <8>;
			fifo-depth = <128>;
			data-addr = <0x200>;
			fifo-watermark-aligned;
			clock-frequency = <167000000>;
			clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>;
			clock-names = "biu", "ciu";
			max-frequency = <167000000>;
			cap-mmc-highspeed;
			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			non-removable;
			disable-wp;
			status = "disabled";
		};

		audiocrm: clock-controller@1480000 {
			compatible = "zte,zx296718-audiocrm";
			reg = <0x01480000 0x1000>;
			#clock-cells = <1>;
		};

		spdif0: spdif@1488000 {
			compatible = "zte,zx296702-spdif";
			reg = <0x1488000 0x1000>;
			clocks = <&audiocrm AUDIO_SPDIF0_WCLK>;
			clock-names = "tx";
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			#sound-dai-cells = <0>;
			dmas = <&dma 30>;
			dma-names = "tx";
			status = "disabled";
		};
	};
};
Commit	Line	Data
2e673c7d JN	1	/*
	2	* Copyright 2016 ZTE Corporation.
	3	* Copyright 2016 Linaro Ltd.
	4	*
	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
	9	*
	10	* a) This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of the
	13	* License, or (at your option) any later version.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* Or, alternatively,
	21	*
	22	* b) Permission is hereby granted, free of charge, to any person
	23	* obtaining a copy of this software and associated documentation
	24	* files (the "Software"), to deal in the Software without
	25	* restriction, including without limitation the rights to use,
	26	* copy, modify, merge, publish, distribute, sublicense, and/or
	27	* sell copies of the Software, and to permit persons to whom the
	28	* Software is furnished to do so, subject to the following
	29	* conditions:
	30	*
	31	* The above copyright notice and this permission notice shall be
	32	* included in all copies or substantial portions of the Software.
	33	*
	34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	35	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	36	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	37	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	38	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	39	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	40	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	41	* OTHER DEALINGS IN THE SOFTWARE.
	42	*/
	43
	44	#include <dt-bindings/input/input.h>
	45	#include <dt-bindings/interrupt-controller/arm-gic.h>
	46	#include <dt-bindings/gpio/gpio.h>
eb2e2a81	47	#include <dt-bindings/clock/zx296718-clock.h>
2e673c7d JN	48
	49	/ {
	50	compatible = "zte,zx296718";
	51	#address-cells = <1>;
	52	#size-cells = <1>;
	53	interrupt-parent = <&gic>;
	54
	55	aliases {
	56	serial0 = &uart0;
	57	};
	58
	59	cpus {
	60	#address-cells = <2>;
	61	#size-cells = <0>;
	62
	63	cpu-map {
	64	cluster0 {
	65	core0 {
	66	cpu = <&cpu0>;
	67	};
	68	core1 {
	69	cpu = <&cpu1>;
	70	};
	71	core2 {
	72	cpu = <&cpu2>;
	73	};
	74	core3 {
	75	cpu = <&cpu3>;
	76	};
	77	};
	78	};
	79
	80	cpu0: cpu@0 {
	81	device_type = "cpu";
	82	compatible = "arm,cortex-a53","arm,armv8";
	83	reg = <0x0 0x0>;
	84	enable-method = "psci";
eb2e2a81 BX	85	clocks = <&topcrm A53_GATE>;
eb2e2a81 BX	86	operating-points-v2 = <&cluster0_opp>;
2e673c7d JN	87	};
	88
	89	cpu1: cpu@1 {
	90	device_type = "cpu";
	91	compatible = "arm,cortex-a53","arm,armv8";
	92	reg = <0x0 0x1>;
	93	enable-method = "psci";
eb2e2a81 BX	94	clocks = <&topcrm A53_GATE>;
eb2e2a81 BX	95	operating-points-v2 = <&cluster0_opp>;
2e673c7d JN	96	};
	97
	98	cpu2: cpu@2 {
	99	device_type = "cpu";
	100	compatible = "arm,cortex-a53","arm,armv8";
	101	reg = <0x0 0x2>;
	102	enable-method = "psci";
eb2e2a81 BX	103	clocks = <&topcrm A53_GATE>;
eb2e2a81 BX	104	operating-points-v2 = <&cluster0_opp>;
2e673c7d JN	105	};
	106
	107	cpu3: cpu@3 {
	108	device_type = "cpu";
	109	compatible = "arm,cortex-a53","arm,armv8";
	110	reg = <0x0 0x3>;
	111	enable-method = "psci";
eb2e2a81 BX	112	clocks = <&topcrm A53_GATE>;
	113	operating-points-v2 = <&cluster0_opp>;
	114	};
	115	};
	116
	117	cluster0_opp: opp-table0 {
	118	compatible = "operating-points-v2";
	119	opp-shared;
	120
61c9e029	121	opp-500000000 {
eb2e2a81 BX	122	opp-hz = /bits/ 64 <500000000>;
	123	clock-latency-ns = <500000>;
	124	};
	125
61c9e029	126	opp-648000000 {
eb2e2a81 BX	127	opp-hz = /bits/ 64 <648000000>;
	128	clock-latency-ns = <500000>;
	129	};
	130
61c9e029	131	opp-800000000 {
eb2e2a81 BX	132	opp-hz = /bits/ 64 <800000000>;
	133	clock-latency-ns = <500000>;
	134	};
	135
61c9e029	136	opp-1000000000 {
eb2e2a81 BX	137	opp-hz = /bits/ 64 <1000000000>;
	138	clock-latency-ns = <500000>;
	139	};
	140
61c9e029	141	opp-1188000000 {
eb2e2a81 BX	142	opp-hz = /bits/ 64 <1188000000>;
eb2e2a81 BX	143	clock-latency-ns = <500000>;
2e673c7d JN	144	};
	145	};
	146
	147	clk24k: clk-24k {
	148	compatible = "fixed-clock";
	149	#clock-cells = <0>;
	150	clock-frequency = <24000>;
	151	clock-output-names = "rtcclk";
	152	};
	153
	154	osc32k: clk-osc32k {
	155	compatible = "fixed-clock";
	156	#clock-cells = <0>;
	157	clock-frequency = <32000>;
	158	clock-output-names = "osc32k";
	159	};
	160
	161	osc12m: clk-osc12m {
	162	compatible = "fixed-clock";
	163	#clock-cells = <0>;
	164	clock-frequency = <12000000>;
	165	clock-output-names = "osc12m";
	166	};
	167
	168	osc24m: clk-osc24m {
	169	compatible = "fixed-clock";
	170	#clock-cells = <0>;
	171	clock-frequency = <24000000>;
	172	clock-output-names = "osc24m";
	173	};
	174
	175	osc25m: clk-osc25m {
	176	compatible = "fixed-clock";
	177	#clock-cells = <0>;
	178	clock-frequency = <25000000>;
	179	clock-output-names = "osc25m";
	180	};
	181
	182	osc60m: clk-osc60m {
	183	compatible = "fixed-clock";
	184	#clock-cells = <0>;
	185	clock-frequency = <60000000>;
	186	clock-output-names = "osc60m";
	187	};
	188
	189	osc99m: clk-osc99m {
	190	compatible = "fixed-clock";
	191	#clock-cells = <0>;
	192	clock-frequency = <99000000>;
	193	clock-output-names = "osc99m";
	194	};
	195
	196	osc125m: clk-osc125m {
	197	compatible = "fixed-clock";
	198	#clock-cells = <0>;
	199	clock-frequency = <125000000>;
	200	clock-output-names = "osc125m";
	201	};
	202
	203	osc198m: clk-osc198m {
	204	compatible = "fixed-clock";
	205	#clock-cells = <0>;
	206	clock-frequency = <198000000>;
	207	clock-output-names = "osc198m";
208	};
209
210	pll_audio: clk-pll-884m {
211	compatible = "fixed-clock";
212	#clock-cells = <0>;
213	clock-frequency = <884000000>;
214	clock-output-names = "pll_audio";
215	};
216
217	pll_ddr: clk-pll-932m {
218	compatible = "fixed-clock";
219	#clock-cells = <0>;
220	clock-frequency = <932000000>;
221	clock-output-names = "pll_ddr";
222	};
223
224	pll_hsic: clk-pll-960m {
225	compatible = "fixed-clock";
226	#clock-cells = <0>;
227	clock-frequency = <960000000>;
228	clock-output-names = "pll_hsic";
229	};
230
231	pll_mac: clk-pll-1000m {
232	compatible = "fixed-clock";
233	#clock-cells = <0>;
234	clock-frequency = <1000000000>;
235	clock-output-names = "pll_mac";
236	};
237
2e673c7d JN	238	pll_mm0: clk-pll-1188m {
	239	compatible = "fixed-clock";
	240	#clock-cells = <0>;
	241	clock-frequency = <1188000000>;
	242	clock-output-names = "pll_mm0";
	243	};
	244
	245	pll_mm1: clk-pll-1296m {
	246	compatible = "fixed-clock";
	247	#clock-cells = <0>;
	248	clock-frequency = <1296000000>;
	249	clock-output-names = "pll_mm1";
	250	};
	251
	252	psci {
	253	compatible = "arm,psci-1.0";
	254	method = "smc";
	255	};
	256
	257	timer {
	258	compatible = "arm,armv8-timer";
	259	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	260	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	261	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	262	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	263	};
	264
	265	pmu {
	266	compatible = "arm,cortex-a53-pmu";
	267	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	268	};
	269
	270	gic: interrupt-controller@2a00000 {
	271	compatible = "arm,gic-v3";
	272	#interrupt-cells = <3>;
	273	#address-cells = <0>;
2e673c7d JN	274	interrupt-controller;
2e673c7d JN	275	reg = <0x02a00000 0x10000>,
fe901d35	276	<0x02b00000 0xc0000>;
2e673c7d JN	277	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	278	};
	279
	280	soc {
	281	#address-cells = <1>;
	282	#size-cells = <1>;
	283	compatible = "simple-bus";
	284	ranges;
	285
	286	aon_sysctrl: aon-sysctrl@116000 {
	287	compatible = "zte,zx296718-aon-sysctrl", "syscon";
	288	reg = <0x116000 0x1000>;
	289	};
	290
	291	uart0: uart@11f000 {
	292	compatible = "arm,pl011", "arm,primecell";
	293	arm,primecell-periphid = <0x001feffe>;
	294	reg = <0x11f000 0x1000>;
	295	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	296	clocks = <&osc24m>;
	297	clock-names = "apb_pclk";
	298	status = "disabled";
	299	};
	300
25798d52 JN	301	sd0: mmc@1110000 {
	302	compatible = "zte,zx296718-dw-mshc";
	303	#address-cells = <1>;
	304	#size-cells = <0>;
	305	reg = <0x01110000 0x1000>;
	306	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	307	fifo-depth = <32>;
	308	data-addr = <0x200>;
	309	fifo-watermark-aligned;
	310	bus-width = <4>;
	311	clock-frequency = <50000000>;
	312	clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
	313	clock-names = "biu", "ciu";
25798d52 JN	314	max-frequency = <50000000>;
	315	cap-sdio-irq;
	316	cap-sd-highspeed;
	317	sd-uhs-sdr12;
	318	sd-uhs-sdr25;
	319	sd-uhs-sdr50;
	320	sd-uhs-sdr104;
	321	sd-uhs-ddr50;
	322	status = "disabled";
	323	};
	324
	325	sd1: mmc@1111000 {
	326	compatible = "zte,zx296718-dw-mshc";
	327	#address-cells = <1>;
	328	#size-cells = <0>;
	329	reg = <0x01111000 0x1000>;
	330	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	331	fifo-depth = <32>;
	332	data-addr = <0x200>;
	333	fifo-watermark-aligned;
	334	bus-width = <4>;
	335	clock-frequency = <167000000>;
	336	clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
	337	clock-names = "biu", "ciu";
25798d52 JN	338	max-frequency = <167000000>;
	339	cap-sdio-irq;
	340	cap-sd-highspeed;
	341	status = "disabled";
	342	};
	343
2e673c7d JN	344	dma: dma-controller@1460000 {
	345	compatible = "zte,zx296702-dma";
	346	reg = <0x01460000 0x1000>;
	347	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	348	clocks = <&osc24m>;
	349	clock-names = "dmaclk";
	350	#dma-cells = <1>;
	351	dma-channels = <32>;
	352	dma-requests = <32>;
	353	};
	354
392ce382 JN	355	lsp0crm: clock-controller@1420000 {
	356	compatible = "zte,zx296718-lsp0crm";
	357	reg = <0x01420000 0x1000>;
	358	#clock-cells = <1>;
	359	};
	360
	361	lsp1crm: clock-controller@1430000 {
	362	compatible = "zte,zx296718-lsp1crm";
	363	reg = <0x01430000 0x1000>;
	364	#clock-cells = <1>;
	365	};
	366
25bd9d5e SG	367	vou: vou@1440000 {
	368	compatible = "zte,zx296718-vou";
	369	#address-cells = <1>;
	370	#size-cells = <1>;
	371	ranges = <0 0x1440000 0x10000>;
	372
	373	dpc: dpc@0 {
	374	compatible = "zte,zx296718-dpc";
	375	reg = <0x0000 0x1000>, <0x1000 0x1000>,
	376	<0x5000 0x1000>, <0x6000 0x1000>,
	377	<0xa000 0x1000>;
	378	reg-names = "osd", "timing_ctrl",
	379	"dtrc", "vou_ctrl",
	380	"otfppu";
	381	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	382	clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
	383	<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
	384	clock-names = "aclk", "ppu_wclk",
	385	"main_wclk", "aux_wclk";
	386	};
	387
0d348d53 SG	388	vga: vga@8000 {
	389	compatible = "zte,zx296718-vga";
	390	reg = <0x8000 0x1000>;
	391	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	392	clocks = <&topcrm VGA_I2C_WCLK>;
	393	clock-names = "i2c_wclk";
	394	zte,vga-power-control = <&sysctrl 0x170 0xe0>;
	395	status = "disabled";
	396	};
	397
25bd9d5e SG	398	hdmi: hdmi@c000 {
	399	compatible = "zte,zx296718-hdmi";
	400	reg = <0xc000 0x4000>;
	401	interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
	402	clocks = <&topcrm HDMI_OSC_CEC>,
	403	<&topcrm HDMI_OSC_CLK>,
	404	<&topcrm HDMI_XCLK>;
	405	clock-names = "osc_cec", "osc_clk", "xclk";
	406	#sound-dai-cells = <0>;
	407	status = "disabled";
	408	};
f006aaf7 SG	409
	410	tvenc: tvenc@2000 {
	411	compatible = "zte,zx296718-tvenc";
	412	reg = <0x2000 0x1000>;
	413	zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
	414	status = "disabled";
	415	};
25bd9d5e SG	416	};
25bd9d5e SG	417
392ce382 JN	418	topcrm: clock-controller@1461000 {
	419	compatible = "zte,zx296718-topcrm";
	420	reg = <0x01461000 0x1000>;
	421	#clock-cells = <1>;
	422	};
	423
2e673c7d JN	424	sysctrl: sysctrl@1463000 {
	425	compatible = "zte,zx296718-sysctrl", "syscon";
	426	reg = <0x1463000 0x1000>;
	427	};
392ce382	428
25798d52 JN	429	emmc: mmc@1470000{
	430	compatible = "zte,zx296718-dw-mshc";
	431	reg = <0x01470000 0x1000>;
	432	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	433	zte,aon-syscon = <&aon_sysctrl>;
	434	bus-width = <8>;
	435	fifo-depth = <128>;
	436	data-addr = <0x200>;
	437	fifo-watermark-aligned;
	438	clock-frequency = <167000000>;
	439	clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>;
	440	clock-names = "biu", "ciu";
	441	max-frequency = <167000000>;
	442	cap-mmc-highspeed;
	443	mmc-ddr-1_8v;
	444	mmc-hs200-1_8v;
	445	non-removable;
	446	disable-wp;
	447	status = "disabled";
	448	};
	449
392ce382 JN	450	audiocrm: clock-controller@1480000 {
	451	compatible = "zte,zx296718-audiocrm";
	452	reg = <0x01480000 0x1000>;
	453	#clock-cells = <1>;
	454	};
25bd9d5e SG	455
	456	spdif0: spdif@1488000 {
	457	compatible = "zte,zx296702-spdif";
	458	reg = <0x1488000 0x1000>;
	459	clocks = <&audiocrm AUDIO_SPDIF0_WCLK>;
	460	clock-names = "tx";
	461	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	462	#sound-dai-cells = <0>;
	463	dmas = <&dma 30>;
	464	dma-names = "tx";
	465	status = "disabled";
	466	};
2e673c7d JN	467	};
2e673c7d JN	468	};