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0369f6a3 MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ARM64_KVM_ARM_H__ | |
19 | #define __ARM64_KVM_ARM_H__ | |
20 | ||
286fb1cc | 21 | #include <asm/memory.h> |
0369f6a3 MZ |
22 | #include <asm/types.h> |
23 | ||
24 | /* Hyp Configuration Register (HCR) bits */ | |
25 | #define HCR_ID (UL(1) << 33) | |
26 | #define HCR_CD (UL(1) << 32) | |
27 | #define HCR_RW_SHIFT 31 | |
28 | #define HCR_RW (UL(1) << HCR_RW_SHIFT) | |
29 | #define HCR_TRVM (UL(1) << 30) | |
30 | #define HCR_HCD (UL(1) << 29) | |
31 | #define HCR_TDZ (UL(1) << 28) | |
32 | #define HCR_TGE (UL(1) << 27) | |
33 | #define HCR_TVM (UL(1) << 26) | |
34 | #define HCR_TTLB (UL(1) << 25) | |
35 | #define HCR_TPU (UL(1) << 24) | |
36 | #define HCR_TPC (UL(1) << 23) | |
37 | #define HCR_TSW (UL(1) << 22) | |
38 | #define HCR_TAC (UL(1) << 21) | |
39 | #define HCR_TIDCP (UL(1) << 20) | |
40 | #define HCR_TSC (UL(1) << 19) | |
41 | #define HCR_TID3 (UL(1) << 18) | |
42 | #define HCR_TID2 (UL(1) << 17) | |
43 | #define HCR_TID1 (UL(1) << 16) | |
44 | #define HCR_TID0 (UL(1) << 15) | |
45 | #define HCR_TWE (UL(1) << 14) | |
46 | #define HCR_TWI (UL(1) << 13) | |
47 | #define HCR_DC (UL(1) << 12) | |
48 | #define HCR_BSU (3 << 10) | |
49 | #define HCR_BSU_IS (UL(1) << 10) | |
50 | #define HCR_FB (UL(1) << 9) | |
51 | #define HCR_VA (UL(1) << 8) | |
52 | #define HCR_VI (UL(1) << 7) | |
53 | #define HCR_VF (UL(1) << 6) | |
54 | #define HCR_AMO (UL(1) << 5) | |
55 | #define HCR_IMO (UL(1) << 4) | |
56 | #define HCR_FMO (UL(1) << 3) | |
57 | #define HCR_PTW (UL(1) << 2) | |
58 | #define HCR_SWIO (UL(1) << 1) | |
59 | #define HCR_VM (UL(1) << 0) | |
60 | ||
61 | /* | |
62 | * The bits we set in HCR: | |
63 | * RW: 64bit by default, can be overriden for 32bit VMs | |
64 | * TAC: Trap ACTLR | |
65 | * TSC: Trap SMC | |
4d44923b | 66 | * TVM: Trap VM ops (until M+C set in SCTLR_EL1) |
0369f6a3 | 67 | * TSW: Trap cache operations by set/way |
d241aac7 | 68 | * TWE: Trap WFE |
0369f6a3 MZ |
69 | * TWI: Trap WFI |
70 | * TIDCP: Trap L2CTLR/L2ECTLR | |
71 | * BSU_IS: Upgrade barriers to the inner shareable domain | |
72 | * FB: Force broadcast of all maintainance operations | |
73 | * AMO: Override CPSR.A and enable signaling with VA | |
74 | * IMO: Override CPSR.I and enable signaling with VI | |
75 | * FMO: Override CPSR.F and enable signaling with VF | |
76 | * SWIO: Turn set/way invalidates into set/way clean+invalidate | |
77 | */ | |
d241aac7 | 78 | #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ |
4d44923b | 79 | HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \ |
ac3c3747 | 80 | HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW) |
0369f6a3 | 81 | #define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) |
ac3c3747 MZ |
82 | #define HCR_INT_OVERRIDE (HCR_FMO | HCR_IMO) |
83 | ||
0369f6a3 MZ |
84 | |
85 | /* Hyp System Control Register (SCTLR_EL2) bits */ | |
86 | #define SCTLR_EL2_EE (1 << 25) | |
87 | #define SCTLR_EL2_WXN (1 << 19) | |
88 | #define SCTLR_EL2_I (1 << 12) | |
89 | #define SCTLR_EL2_SA (1 << 3) | |
90 | #define SCTLR_EL2_C (1 << 2) | |
91 | #define SCTLR_EL2_A (1 << 1) | |
92 | #define SCTLR_EL2_M 1 | |
93 | #define SCTLR_EL2_FLAGS (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C | \ | |
94 | SCTLR_EL2_SA | SCTLR_EL2_I) | |
95 | ||
96 | /* TCR_EL2 Registers bits */ | |
97 | #define TCR_EL2_TBI (1 << 20) | |
98 | #define TCR_EL2_PS (7 << 16) | |
99 | #define TCR_EL2_PS_40B (2 << 16) | |
100 | #define TCR_EL2_TG0 (1 << 14) | |
101 | #define TCR_EL2_SH0 (3 << 12) | |
102 | #define TCR_EL2_ORGN0 (3 << 10) | |
103 | #define TCR_EL2_IRGN0 (3 << 8) | |
104 | #define TCR_EL2_T0SZ 0x3f | |
105 | #define TCR_EL2_MASK (TCR_EL2_TG0 | TCR_EL2_SH0 | \ | |
106 | TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ) | |
107 | ||
108 | #define TCR_EL2_FLAGS (TCR_EL2_PS_40B) | |
109 | ||
110 | /* VTCR_EL2 Registers bits */ | |
111 | #define VTCR_EL2_PS_MASK (7 << 16) | |
0369f6a3 MZ |
112 | #define VTCR_EL2_TG0_MASK (1 << 14) |
113 | #define VTCR_EL2_TG0_4K (0 << 14) | |
114 | #define VTCR_EL2_TG0_64K (1 << 14) | |
115 | #define VTCR_EL2_SH0_MASK (3 << 12) | |
116 | #define VTCR_EL2_SH0_INNER (3 << 12) | |
117 | #define VTCR_EL2_ORGN0_MASK (3 << 10) | |
118 | #define VTCR_EL2_ORGN0_WBWA (1 << 10) | |
119 | #define VTCR_EL2_IRGN0_MASK (3 << 8) | |
120 | #define VTCR_EL2_IRGN0_WBWA (1 << 8) | |
121 | #define VTCR_EL2_SL0_MASK (3 << 6) | |
122 | #define VTCR_EL2_SL0_LVL1 (1 << 6) | |
123 | #define VTCR_EL2_T0SZ_MASK 0x3f | |
124 | #define VTCR_EL2_T0SZ_40B 24 | |
125 | ||
dbff124e JS |
126 | /* |
127 | * We configure the Stage-2 page tables to always restrict the IPA space to be | |
128 | * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are | |
129 | * not known to exist and will break with this configuration. | |
130 | * | |
131 | * Note that when using 4K pages, we concatenate two first level page tables | |
132 | * together. | |
133 | * | |
134 | * The magic numbers used for VTTBR_X in this patch can be found in Tables | |
135 | * D4-23 and D4-25 in ARM DDI 0487A.b. | |
136 | */ | |
0369f6a3 MZ |
137 | #ifdef CONFIG_ARM64_64K_PAGES |
138 | /* | |
139 | * Stage2 translation configuration: | |
140 | * 40bits output (PS = 2) | |
141 | * 40bits input (T0SZ = 24) | |
142 | * 64kB pages (TG0 = 1) | |
143 | * 2 level page tables (SL = 1) | |
144 | */ | |
87366d8c RMC |
145 | #define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \ |
146 | VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ | |
147 | VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B) | |
0369f6a3 MZ |
148 | #define VTTBR_X (38 - VTCR_EL2_T0SZ_40B) |
149 | #else | |
150 | /* | |
151 | * Stage2 translation configuration: | |
152 | * 40bits output (PS = 2) | |
153 | * 40bits input (T0SZ = 24) | |
154 | * 4kB pages (TG0 = 0) | |
155 | * 3 level page tables (SL = 1) | |
156 | */ | |
87366d8c RMC |
157 | #define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ |
158 | VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ | |
159 | VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B) | |
0369f6a3 MZ |
160 | #define VTTBR_X (37 - VTCR_EL2_T0SZ_40B) |
161 | #endif | |
162 | ||
163 | #define VTTBR_BADDR_SHIFT (VTTBR_X - 1) | |
286fb1cc GL |
164 | #define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) |
165 | #define VTTBR_VMID_SHIFT (UL(48)) | |
166 | #define VTTBR_VMID_MASK (UL(0xFF) << VTTBR_VMID_SHIFT) | |
0369f6a3 MZ |
167 | |
168 | /* Hyp System Trap Register */ | |
169 | #define HSTR_EL2_TTEE (1 << 16) | |
170 | #define HSTR_EL2_T(x) (1 << x) | |
171 | ||
172 | /* Hyp Coprocessor Trap Register */ | |
173 | #define CPTR_EL2_TCPAC (1 << 31) | |
174 | #define CPTR_EL2_TTA (1 << 20) | |
175 | #define CPTR_EL2_TFP (1 << 10) | |
176 | ||
177 | /* Hyp Debug Configuration Register bits */ | |
178 | #define MDCR_EL2_TDRA (1 << 11) | |
179 | #define MDCR_EL2_TDOSA (1 << 10) | |
180 | #define MDCR_EL2_TDA (1 << 9) | |
181 | #define MDCR_EL2_TDE (1 << 8) | |
182 | #define MDCR_EL2_HPME (1 << 7) | |
183 | #define MDCR_EL2_TPM (1 << 6) | |
184 | #define MDCR_EL2_TPMCR (1 << 5) | |
185 | #define MDCR_EL2_HPMN_MASK (0x1F) | |
186 | ||
187 | /* Exception Syndrome Register (ESR) bits */ | |
188 | #define ESR_EL2_EC_SHIFT (26) | |
286fb1cc GL |
189 | #define ESR_EL2_EC (UL(0x3f) << ESR_EL2_EC_SHIFT) |
190 | #define ESR_EL2_IL (UL(1) << 25) | |
0369f6a3 MZ |
191 | #define ESR_EL2_ISS (ESR_EL2_IL - 1) |
192 | #define ESR_EL2_ISV_SHIFT (24) | |
286fb1cc | 193 | #define ESR_EL2_ISV (UL(1) << ESR_EL2_ISV_SHIFT) |
0369f6a3 | 194 | #define ESR_EL2_SAS_SHIFT (22) |
286fb1cc | 195 | #define ESR_EL2_SAS (UL(3) << ESR_EL2_SAS_SHIFT) |
0369f6a3 MZ |
196 | #define ESR_EL2_SSE (1 << 21) |
197 | #define ESR_EL2_SRT_SHIFT (16) | |
198 | #define ESR_EL2_SRT_MASK (0x1f << ESR_EL2_SRT_SHIFT) | |
199 | #define ESR_EL2_SF (1 << 15) | |
200 | #define ESR_EL2_AR (1 << 14) | |
201 | #define ESR_EL2_EA (1 << 9) | |
202 | #define ESR_EL2_CM (1 << 8) | |
203 | #define ESR_EL2_S1PTW (1 << 7) | |
204 | #define ESR_EL2_WNR (1 << 6) | |
205 | #define ESR_EL2_FSC (0x3f) | |
206 | #define ESR_EL2_FSC_TYPE (0x3c) | |
207 | ||
208 | #define ESR_EL2_CV_SHIFT (24) | |
286fb1cc | 209 | #define ESR_EL2_CV (UL(1) << ESR_EL2_CV_SHIFT) |
0369f6a3 | 210 | #define ESR_EL2_COND_SHIFT (20) |
286fb1cc | 211 | #define ESR_EL2_COND (UL(0xf) << ESR_EL2_COND_SHIFT) |
0369f6a3 MZ |
212 | |
213 | ||
214 | #define FSC_FAULT (0x04) | |
215 | #define FSC_PERM (0x0c) | |
216 | ||
217 | /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ | |
286fb1cc | 218 | #define HPFAR_MASK (~UL(0xf)) |
0369f6a3 MZ |
219 | |
220 | #define ESR_EL2_EC_UNKNOWN (0x00) | |
221 | #define ESR_EL2_EC_WFI (0x01) | |
222 | #define ESR_EL2_EC_CP15_32 (0x03) | |
223 | #define ESR_EL2_EC_CP15_64 (0x04) | |
224 | #define ESR_EL2_EC_CP14_MR (0x05) | |
225 | #define ESR_EL2_EC_CP14_LS (0x06) | |
226 | #define ESR_EL2_EC_FP_ASIMD (0x07) | |
227 | #define ESR_EL2_EC_CP10_ID (0x08) | |
228 | #define ESR_EL2_EC_CP14_64 (0x0C) | |
229 | #define ESR_EL2_EC_ILL_ISS (0x0E) | |
230 | #define ESR_EL2_EC_SVC32 (0x11) | |
231 | #define ESR_EL2_EC_HVC32 (0x12) | |
232 | #define ESR_EL2_EC_SMC32 (0x13) | |
233 | #define ESR_EL2_EC_SVC64 (0x15) | |
234 | #define ESR_EL2_EC_HVC64 (0x16) | |
235 | #define ESR_EL2_EC_SMC64 (0x17) | |
236 | #define ESR_EL2_EC_SYS64 (0x18) | |
237 | #define ESR_EL2_EC_IABT (0x20) | |
238 | #define ESR_EL2_EC_IABT_HYP (0x21) | |
239 | #define ESR_EL2_EC_PC_ALIGN (0x22) | |
240 | #define ESR_EL2_EC_DABT (0x24) | |
241 | #define ESR_EL2_EC_DABT_HYP (0x25) | |
242 | #define ESR_EL2_EC_SP_ALIGN (0x26) | |
243 | #define ESR_EL2_EC_FP_EXC32 (0x28) | |
244 | #define ESR_EL2_EC_FP_EXC64 (0x2C) | |
bfb67a56 | 245 | #define ESR_EL2_EC_SERROR (0x2F) |
0369f6a3 MZ |
246 | #define ESR_EL2_EC_BREAKPT (0x30) |
247 | #define ESR_EL2_EC_BREAKPT_HYP (0x31) | |
248 | #define ESR_EL2_EC_SOFTSTP (0x32) | |
249 | #define ESR_EL2_EC_SOFTSTP_HYP (0x33) | |
250 | #define ESR_EL2_EC_WATCHPT (0x34) | |
251 | #define ESR_EL2_EC_WATCHPT_HYP (0x35) | |
252 | #define ESR_EL2_EC_BKPT32 (0x38) | |
253 | #define ESR_EL2_EC_VECTOR32 (0x3A) | |
254 | #define ESR_EL2_EC_BRK64 (0x3C) | |
255 | ||
256 | #define ESR_EL2_EC_xABT_xFSR_EXTABT 0x10 | |
257 | ||
d241aac7 MZ |
258 | #define ESR_EL2_EC_WFI_ISS_WFE (1 << 0) |
259 | ||
0369f6a3 | 260 | #endif /* __ARM64_KVM_ARM_H__ */ |