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72c58395 CM |
1 | /* |
2 | * Macros for accessing system registers with older binutils. | |
3 | * | |
4 | * Copyright (C) 2014 ARM Ltd. | |
5 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef __ASM_SYSREG_H | |
21 | #define __ASM_SYSREG_H | |
22 | ||
3600c2fd MR |
23 | #include <linux/stringify.h> |
24 | ||
9ded63aa SP |
25 | /* |
26 | * ARMv8 ARM reserves the following encoding for system registers: | |
27 | * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", | |
28 | * C5.2, version:ARM DDI 0487A.f) | |
29 | * [20-19] : Op0 | |
30 | * [18-16] : Op1 | |
31 | * [15-12] : CRn | |
32 | * [11-8] : CRm | |
33 | * [7-5] : Op2 | |
34 | */ | |
c9ee0f98 SP |
35 | #define Op0_shift 19 |
36 | #define Op0_mask 0x3 | |
37 | #define Op1_shift 16 | |
38 | #define Op1_mask 0x7 | |
39 | #define CRn_shift 12 | |
40 | #define CRn_mask 0xf | |
41 | #define CRm_shift 8 | |
42 | #define CRm_mask 0xf | |
43 | #define Op2_shift 5 | |
44 | #define Op2_mask 0x7 | |
45 | ||
72c58395 | 46 | #define sys_reg(op0, op1, crn, crm, op2) \ |
c9ee0f98 SP |
47 | (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ |
48 | ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ | |
49 | ((op2) << Op2_shift)) | |
50 | ||
51 | #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) | |
52 | #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) | |
53 | #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) | |
54 | #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) | |
55 | #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) | |
72c58395 | 56 | |
cd9e1927 MZ |
57 | #ifndef CONFIG_BROKEN_GAS_INST |
58 | ||
bca8f17f MZ |
59 | #ifdef __ASSEMBLY__ |
60 | #define __emit_inst(x) .inst (x) | |
61 | #else | |
62 | #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" | |
63 | #endif | |
64 | ||
cd9e1927 MZ |
65 | #else /* CONFIG_BROKEN_GAS_INST */ |
66 | ||
67 | #ifndef CONFIG_CPU_BIG_ENDIAN | |
68 | #define __INSTR_BSWAP(x) (x) | |
69 | #else /* CONFIG_CPU_BIG_ENDIAN */ | |
70 | #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ | |
71 | (((x) << 8) & 0x00ff0000) | \ | |
72 | (((x) >> 8) & 0x0000ff00) | \ | |
73 | (((x) >> 24) & 0x000000ff)) | |
74 | #endif /* CONFIG_CPU_BIG_ENDIAN */ | |
75 | ||
76 | #ifdef __ASSEMBLY__ | |
77 | #define __emit_inst(x) .long __INSTR_BSWAP(x) | |
78 | #else /* __ASSEMBLY__ */ | |
79 | #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" | |
80 | #endif /* __ASSEMBLY__ */ | |
81 | ||
82 | #endif /* CONFIG_BROKEN_GAS_INST */ | |
83 | ||
47863d41 MR |
84 | #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) |
85 | #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) | |
86 | ||
87 | #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \ | |
88 | (!!x)<<8 | 0x1f) | |
89 | #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \ | |
90 | (!!x)<<8 | 0x1f) | |
91 | ||
3c739b57 SP |
92 | #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) |
93 | #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) | |
94 | #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) | |
95 | ||
96 | #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) | |
97 | #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) | |
98 | #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) | |
99 | #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) | |
100 | #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) | |
101 | #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) | |
102 | #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) | |
103 | ||
104 | #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) | |
105 | #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) | |
106 | #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) | |
107 | #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) | |
108 | #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) | |
109 | #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) | |
110 | #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) | |
111 | ||
112 | #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) | |
113 | #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) | |
114 | #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) | |
115 | ||
116 | #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) | |
117 | #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) | |
118 | ||
119 | #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) | |
120 | #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) | |
121 | ||
122 | #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) | |
123 | #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) | |
124 | ||
125 | #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) | |
126 | #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) | |
406e3087 | 127 | #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) |
3c739b57 | 128 | |
3c739b57 SP |
129 | #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) |
130 | #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) | |
131 | ||
47863d41 | 132 | #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) |
338d4f49 | 133 | |
e7227d0e GL |
134 | /* Common SCTLR_ELx flags. */ |
135 | #define SCTLR_ELx_EE (1 << 25) | |
136 | #define SCTLR_ELx_I (1 << 12) | |
137 | #define SCTLR_ELx_SA (1 << 3) | |
138 | #define SCTLR_ELx_C (1 << 2) | |
139 | #define SCTLR_ELx_A (1 << 1) | |
140 | #define SCTLR_ELx_M 1 | |
141 | ||
142 | #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ | |
143 | SCTLR_ELx_SA | SCTLR_ELx_I) | |
144 | ||
145 | /* SCTLR_EL1 specific flags. */ | |
7dd01aef | 146 | #define SCTLR_EL1_UCI (1 << 26) |
e7227d0e | 147 | #define SCTLR_EL1_SPAN (1 << 23) |
116c81f4 | 148 | #define SCTLR_EL1_UCT (1 << 15) |
e7227d0e GL |
149 | #define SCTLR_EL1_SED (1 << 8) |
150 | #define SCTLR_EL1_CP15BEN (1 << 5) | |
3c739b57 | 151 | |
3c739b57 SP |
152 | /* id_aa64isar0 */ |
153 | #define ID_AA64ISAR0_RDM_SHIFT 28 | |
154 | #define ID_AA64ISAR0_ATOMICS_SHIFT 20 | |
155 | #define ID_AA64ISAR0_CRC32_SHIFT 16 | |
156 | #define ID_AA64ISAR0_SHA2_SHIFT 12 | |
157 | #define ID_AA64ISAR0_SHA1_SHIFT 8 | |
158 | #define ID_AA64ISAR0_AES_SHIFT 4 | |
159 | ||
160 | /* id_aa64pfr0 */ | |
161 | #define ID_AA64PFR0_GIC_SHIFT 24 | |
162 | #define ID_AA64PFR0_ASIMD_SHIFT 20 | |
163 | #define ID_AA64PFR0_FP_SHIFT 16 | |
164 | #define ID_AA64PFR0_EL3_SHIFT 12 | |
165 | #define ID_AA64PFR0_EL2_SHIFT 8 | |
166 | #define ID_AA64PFR0_EL1_SHIFT 4 | |
167 | #define ID_AA64PFR0_EL0_SHIFT 0 | |
168 | ||
169 | #define ID_AA64PFR0_FP_NI 0xf | |
170 | #define ID_AA64PFR0_FP_SUPPORTED 0x0 | |
171 | #define ID_AA64PFR0_ASIMD_NI 0xf | |
172 | #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 | |
173 | #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 | |
174 | #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 | |
c80aba80 | 175 | #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 |
3c739b57 SP |
176 | |
177 | /* id_aa64mmfr0 */ | |
178 | #define ID_AA64MMFR0_TGRAN4_SHIFT 28 | |
179 | #define ID_AA64MMFR0_TGRAN64_SHIFT 24 | |
180 | #define ID_AA64MMFR0_TGRAN16_SHIFT 20 | |
cdcf817b | 181 | #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 |
3c739b57 | 182 | #define ID_AA64MMFR0_SNSMEM_SHIFT 12 |
cdcf817b | 183 | #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 |
3c739b57 SP |
184 | #define ID_AA64MMFR0_ASID_SHIFT 4 |
185 | #define ID_AA64MMFR0_PARANGE_SHIFT 0 | |
186 | ||
187 | #define ID_AA64MMFR0_TGRAN4_NI 0xf | |
188 | #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 | |
189 | #define ID_AA64MMFR0_TGRAN64_NI 0xf | |
190 | #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 | |
191 | #define ID_AA64MMFR0_TGRAN16_NI 0x0 | |
192 | #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 | |
193 | ||
194 | /* id_aa64mmfr1 */ | |
195 | #define ID_AA64MMFR1_PAN_SHIFT 20 | |
196 | #define ID_AA64MMFR1_LOR_SHIFT 16 | |
197 | #define ID_AA64MMFR1_HPD_SHIFT 12 | |
198 | #define ID_AA64MMFR1_VHE_SHIFT 8 | |
199 | #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 | |
200 | #define ID_AA64MMFR1_HADBS_SHIFT 0 | |
201 | ||
cb678d60 SP |
202 | #define ID_AA64MMFR1_VMIDBITS_8 0 |
203 | #define ID_AA64MMFR1_VMIDBITS_16 2 | |
204 | ||
406e3087 | 205 | /* id_aa64mmfr2 */ |
7d7b4ae4 KW |
206 | #define ID_AA64MMFR2_LVA_SHIFT 16 |
207 | #define ID_AA64MMFR2_IESB_SHIFT 12 | |
208 | #define ID_AA64MMFR2_LSM_SHIFT 8 | |
406e3087 | 209 | #define ID_AA64MMFR2_UAO_SHIFT 4 |
7d7b4ae4 | 210 | #define ID_AA64MMFR2_CNP_SHIFT 0 |
406e3087 | 211 | |
3c739b57 | 212 | /* id_aa64dfr0 */ |
f31deaad | 213 | #define ID_AA64DFR0_PMSVER_SHIFT 32 |
3c739b57 SP |
214 | #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 |
215 | #define ID_AA64DFR0_WRPS_SHIFT 20 | |
216 | #define ID_AA64DFR0_BRPS_SHIFT 12 | |
217 | #define ID_AA64DFR0_PMUVER_SHIFT 8 | |
218 | #define ID_AA64DFR0_TRACEVER_SHIFT 4 | |
219 | #define ID_AA64DFR0_DEBUGVER_SHIFT 0 | |
220 | ||
221 | #define ID_ISAR5_RDM_SHIFT 24 | |
222 | #define ID_ISAR5_CRC32_SHIFT 16 | |
223 | #define ID_ISAR5_SHA2_SHIFT 12 | |
224 | #define ID_ISAR5_SHA1_SHIFT 8 | |
225 | #define ID_ISAR5_AES_SHIFT 4 | |
226 | #define ID_ISAR5_SEVL_SHIFT 0 | |
227 | ||
228 | #define MVFR0_FPROUND_SHIFT 28 | |
229 | #define MVFR0_FPSHVEC_SHIFT 24 | |
230 | #define MVFR0_FPSQRT_SHIFT 20 | |
231 | #define MVFR0_FPDIVIDE_SHIFT 16 | |
232 | #define MVFR0_FPTRAP_SHIFT 12 | |
233 | #define MVFR0_FPDP_SHIFT 8 | |
234 | #define MVFR0_FPSP_SHIFT 4 | |
235 | #define MVFR0_SIMD_SHIFT 0 | |
236 | ||
237 | #define MVFR1_SIMDFMAC_SHIFT 28 | |
238 | #define MVFR1_FPHP_SHIFT 24 | |
239 | #define MVFR1_SIMDHP_SHIFT 20 | |
240 | #define MVFR1_SIMDSP_SHIFT 16 | |
241 | #define MVFR1_SIMDINT_SHIFT 12 | |
242 | #define MVFR1_SIMDLS_SHIFT 8 | |
243 | #define MVFR1_FPDNAN_SHIFT 4 | |
244 | #define MVFR1_FPFTZ_SHIFT 0 | |
245 | ||
4bf8b96e SP |
246 | |
247 | #define ID_AA64MMFR0_TGRAN4_SHIFT 28 | |
248 | #define ID_AA64MMFR0_TGRAN64_SHIFT 24 | |
249 | #define ID_AA64MMFR0_TGRAN16_SHIFT 20 | |
250 | ||
251 | #define ID_AA64MMFR0_TGRAN4_NI 0xf | |
252 | #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 | |
253 | #define ID_AA64MMFR0_TGRAN64_NI 0xf | |
254 | #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 | |
255 | #define ID_AA64MMFR0_TGRAN16_NI 0x0 | |
256 | #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 | |
257 | ||
258 | #if defined(CONFIG_ARM64_4K_PAGES) | |
259 | #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT | |
260 | #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED | |
44eaacf1 SP |
261 | #elif defined(CONFIG_ARM64_16K_PAGES) |
262 | #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT | |
263 | #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED | |
4bf8b96e SP |
264 | #elif defined(CONFIG_ARM64_64K_PAGES) |
265 | #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT | |
266 | #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED | |
267 | #endif | |
268 | ||
77c97b4e SP |
269 | |
270 | /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ | |
271 | #define SYS_MPIDR_SAFE_VAL (1UL << 31) | |
272 | ||
72c58395 CM |
273 | #ifdef __ASSEMBLY__ |
274 | ||
275 | .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 | |
7abc7d83 | 276 | .equ .L__reg_num_x\num, \num |
72c58395 | 277 | .endr |
7abc7d83 | 278 | .equ .L__reg_num_xzr, 31 |
72c58395 CM |
279 | |
280 | .macro mrs_s, rt, sreg | |
cd9e1927 | 281 | __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) |
72c58395 CM |
282 | .endm |
283 | ||
284 | .macro msr_s, sreg, rt | |
cd9e1927 | 285 | __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) |
72c58395 CM |
286 | .endm |
287 | ||
288 | #else | |
289 | ||
3600c2fd MR |
290 | #include <linux/types.h> |
291 | ||
72c58395 CM |
292 | asm( |
293 | " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" | |
7abc7d83 | 294 | " .equ .L__reg_num_x\\num, \\num\n" |
72c58395 | 295 | " .endr\n" |
7abc7d83 | 296 | " .equ .L__reg_num_xzr, 31\n" |
72c58395 CM |
297 | "\n" |
298 | " .macro mrs_s, rt, sreg\n" | |
cd9e1927 | 299 | __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) |
72c58395 CM |
300 | " .endm\n" |
301 | "\n" | |
302 | " .macro msr_s, sreg, rt\n" | |
cd9e1927 | 303 | __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) |
72c58395 CM |
304 | " .endm\n" |
305 | ); | |
306 | ||
3600c2fd MR |
307 | /* |
308 | * Unlike read_cpuid, calls to read_sysreg are never expected to be | |
309 | * optimized away or replaced with synthetic values. | |
310 | */ | |
311 | #define read_sysreg(r) ({ \ | |
312 | u64 __val; \ | |
313 | asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ | |
314 | __val; \ | |
315 | }) | |
316 | ||
7aff4a2d MR |
317 | /* |
318 | * The "Z" constraint normally means a zero immediate, but when combined with | |
319 | * the "%x0" template means XZR. | |
320 | */ | |
3600c2fd MR |
321 | #define write_sysreg(v, r) do { \ |
322 | u64 __val = (u64)v; \ | |
7aff4a2d MR |
323 | asm volatile("msr " __stringify(r) ", %x0" \ |
324 | : : "rZ" (__val)); \ | |
3600c2fd MR |
325 | } while (0) |
326 | ||
8a71f0c6 WD |
327 | /* |
328 | * For registers without architectural names, or simply unsupported by | |
329 | * GAS. | |
330 | */ | |
331 | #define read_sysreg_s(r) ({ \ | |
332 | u64 __val; \ | |
333 | asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \ | |
334 | __val; \ | |
335 | }) | |
336 | ||
337 | #define write_sysreg_s(v, r) do { \ | |
338 | u64 __val = (u64)v; \ | |
91cb163e | 339 | asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ |
8a71f0c6 WD |
340 | } while (0) |
341 | ||
adf75899 MR |
342 | static inline void config_sctlr_el1(u32 clear, u32 set) |
343 | { | |
344 | u32 val; | |
345 | ||
346 | val = read_sysreg(sctlr_el1); | |
347 | val &= ~clear; | |
348 | val |= set; | |
349 | write_sysreg(val, sctlr_el1); | |
350 | } | |
351 | ||
72c58395 CM |
352 | #endif |
353 | ||
354 | #endif /* __ASM_SYSREG_H */ |