[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / include / asm / sysreg.h

/*
 * Macros for accessing system registers with older binutils.
 *
 * Copyright (C) 2014 ARM Ltd.
 * Author: Catalin Marinas <catalin.marinas@arm.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ASM_SYSREG_H
#define __ASM_SYSREG_H

#include <asm/opcodes.h>

#define SCTLR_EL1_CP15BEN	(0x1 << 5)
#define SCTLR_EL1_SED		(0x1 << 8)

/*
 * ARMv8 ARM reserves the following encoding for system registers:
 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
 *  C5.2, version:ARM DDI 0487A.f)
 *	[20-19] : Op0
 *	[18-16] : Op1
 *	[15-12] : CRn
 *	[11-8]  : CRm
 *	[7-5]   : Op2
 */
#define sys_reg(op0, op1, crn, crm, op2) \
	((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))

#define REG_PSTATE_PAN_IMM                     sys_reg(0, 0, 4, 0, 4)
#define SCTLR_EL1_SPAN                         (1 << 23)

#define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
				     (!!x)<<8 | 0x1f)


#define ID_AA64MMFR0_TGRAN4_SHIFT	28
#define ID_AA64MMFR0_TGRAN64_SHIFT	24
#define ID_AA64MMFR0_TGRAN16_SHIFT	20

#define ID_AA64MMFR0_TGRAN4_NI		0xf
#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
#define ID_AA64MMFR0_TGRAN64_NI		0xf
#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
#define ID_AA64MMFR0_TGRAN16_NI		0x0
#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1

#if defined(CONFIG_ARM64_4K_PAGES)
#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN4_SHIFT
#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN4_SUPPORTED
#elif defined(CONFIG_ARM64_16K_PAGES)
#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN16_SHIFT
#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN16_SUPPORTED
#elif defined(CONFIG_ARM64_64K_PAGES)
#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN64_SHIFT
#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN64_SUPPORTED
#endif

#ifdef __ASSEMBLY__

	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
	.equ	__reg_num_x\num, \num
	.endr
	.equ	__reg_num_xzr, 31

	.macro	mrs_s, rt, sreg
	.inst	0xd5200000|(\sreg)|(__reg_num_\rt)
	.endm

	.macro	msr_s, sreg, rt
	.inst	0xd5000000|(\sreg)|(__reg_num_\rt)
	.endm

#else

asm(
"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
"	.equ	__reg_num_x\\num, \\num\n"
"	.endr\n"
"	.equ	__reg_num_xzr, 31\n"
"\n"
"	.macro	mrs_s, rt, sreg\n"
"	.inst	0xd5200000|(\\sreg)|(__reg_num_\\rt)\n"
"	.endm\n"
"\n"
"	.macro	msr_s, sreg, rt\n"
"	.inst	0xd5000000|(\\sreg)|(__reg_num_\\rt)\n"
"	.endm\n"
);

static inline void config_sctlr_el1(u32 clear, u32 set)
{
	u32 val;

	asm volatile("mrs %0, sctlr_el1" : "=r" (val));
	val &= ~clear;
	val |= set;
	asm volatile("msr sctlr_el1, %0" : : "r" (val));
}
#endif

#endif	/* __ASM_SYSREG_H */
Commit	Line	Data
72c58395 CM	1	/*
	2	* Macros for accessing system registers with older binutils.
	3	*
	4	* Copyright (C) 2014 ARM Ltd.
	5	* Author: Catalin Marinas <catalin.marinas@arm.com>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef __ASM_SYSREG_H
	21	#define __ASM_SYSREG_H
	22
338d4f49 JM	23	#include <asm/opcodes.h>
338d4f49 JM	24
870828e5 JM	25	#define SCTLR_EL1_CP15BEN (0x1 << 5)
	26	#define SCTLR_EL1_SED (0x1 << 8)
	27
9ded63aa SP	28	/*
	29	* ARMv8 ARM reserves the following encoding for system registers:
	30	* (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
	31	* C5.2, version:ARM DDI 0487A.f)
	32	* [20-19] : Op0
	33	* [18-16] : Op1
	34	* [15-12] : CRn
	35	* [11-8] : CRm
	36	* [7-5] : Op2
	37	*/
72c58395	38	#define sys_reg(op0, op1, crn, crm, op2) \
9ded63aa	39	((((op0)&3)<<19)\|((op1)<<16)\|((crn)<<12)\|((crm)<<8)\|((op2)<<5))
72c58395	40
338d4f49 JM	41	#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
	42	#define SCTLR_EL1_SPAN (1 << 23)
	43
	44	#define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 \| REG_PSTATE_PAN_IMM \|\
	45	(!!x)<<8 \| 0x1f)
	46
4bf8b96e SP	47
	48	#define ID_AA64MMFR0_TGRAN4_SHIFT 28
	49	#define ID_AA64MMFR0_TGRAN64_SHIFT 24
	50	#define ID_AA64MMFR0_TGRAN16_SHIFT 20
	51
	52	#define ID_AA64MMFR0_TGRAN4_NI 0xf
	53	#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
	54	#define ID_AA64MMFR0_TGRAN64_NI 0xf
	55	#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
	56	#define ID_AA64MMFR0_TGRAN16_NI 0x0
	57	#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
	58
	59	#if defined(CONFIG_ARM64_4K_PAGES)
	60	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
	61	#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
44eaacf1 SP	62	#elif defined(CONFIG_ARM64_16K_PAGES)
	63	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
	64	#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
4bf8b96e SP	65	#elif defined(CONFIG_ARM64_64K_PAGES)
	66	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
	67	#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
	68	#endif
	69
72c58395 CM	70	#ifdef __ASSEMBLY__
	71
	72	.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
	73	.equ __reg_num_x\num, \num
	74	.endr
	75	.equ __reg_num_xzr, 31
	76
	77	.macro mrs_s, rt, sreg
9ded63aa	78	.inst 0xd5200000\|(\sreg)\|(__reg_num_\rt)
72c58395 CM	79	.endm
	80
	81	.macro msr_s, sreg, rt
9ded63aa	82	.inst 0xd5000000\|(\sreg)\|(__reg_num_\rt)
72c58395 CM	83	.endm
	84
	85	#else
	86
	87	asm(
	88	" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
	89	" .equ __reg_num_x\\num, \\num\n"
	90	" .endr\n"
	91	" .equ __reg_num_xzr, 31\n"
	92	"\n"
	93	" .macro mrs_s, rt, sreg\n"
9ded63aa	94	" .inst 0xd5200000\|(\\sreg)\|(__reg_num_\\rt)\n"
72c58395 CM	95	" .endm\n"
	96	"\n"
	97	" .macro msr_s, sreg, rt\n"
9ded63aa	98	" .inst 0xd5000000\|(\\sreg)\|(__reg_num_\\rt)\n"
72c58395 CM	99	" .endm\n"
	100	);
	101
870828e5 JM	102	static inline void config_sctlr_el1(u32 clear, u32 set)
	103	{
	104	u32 val;
	105
	106	asm volatile("mrs %0, sctlr_el1" : "=r" (val));
	107	val &= ~clear;
	108	val \|= set;
	109	asm volatile("msr sctlr_el1, %0" : : "r" (val));
	110	}
72c58395 CM	111	#endif
	112
	113	#endif /* __ASM_SYSREG_H */