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72c58395 CM |
1 | /* |
2 | * Macros for accessing system registers with older binutils. | |
3 | * | |
4 | * Copyright (C) 2014 ARM Ltd. | |
5 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef __ASM_SYSREG_H | |
21 | #define __ASM_SYSREG_H | |
22 | ||
99501991 | 23 | #include <asm/compiler.h> |
3600c2fd MR |
24 | #include <linux/stringify.h> |
25 | ||
9ded63aa SP |
26 | /* |
27 | * ARMv8 ARM reserves the following encoding for system registers: | |
28 | * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", | |
29 | * C5.2, version:ARM DDI 0487A.f) | |
30 | * [20-19] : Op0 | |
31 | * [18-16] : Op1 | |
32 | * [15-12] : CRn | |
33 | * [11-8] : CRm | |
34 | * [7-5] : Op2 | |
35 | */ | |
c9ee0f98 SP |
36 | #define Op0_shift 19 |
37 | #define Op0_mask 0x3 | |
38 | #define Op1_shift 16 | |
39 | #define Op1_mask 0x7 | |
40 | #define CRn_shift 12 | |
41 | #define CRn_mask 0xf | |
42 | #define CRm_shift 8 | |
43 | #define CRm_mask 0xf | |
44 | #define Op2_shift 5 | |
45 | #define Op2_mask 0x7 | |
46 | ||
72c58395 | 47 | #define sys_reg(op0, op1, crn, crm, op2) \ |
c9ee0f98 SP |
48 | (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ |
49 | ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ | |
50 | ((op2) << Op2_shift)) | |
51 | ||
4dc52925 MR |
52 | #define sys_insn sys_reg |
53 | ||
c9ee0f98 SP |
54 | #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) |
55 | #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) | |
56 | #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) | |
57 | #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) | |
58 | #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) | |
72c58395 | 59 | |
cd9e1927 MZ |
60 | #ifndef CONFIG_BROKEN_GAS_INST |
61 | ||
bca8f17f MZ |
62 | #ifdef __ASSEMBLY__ |
63 | #define __emit_inst(x) .inst (x) | |
64 | #else | |
65 | #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" | |
66 | #endif | |
67 | ||
cd9e1927 MZ |
68 | #else /* CONFIG_BROKEN_GAS_INST */ |
69 | ||
70 | #ifndef CONFIG_CPU_BIG_ENDIAN | |
71 | #define __INSTR_BSWAP(x) (x) | |
72 | #else /* CONFIG_CPU_BIG_ENDIAN */ | |
73 | #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ | |
74 | (((x) << 8) & 0x00ff0000) | \ | |
75 | (((x) >> 8) & 0x0000ff00) | \ | |
76 | (((x) >> 24) & 0x000000ff)) | |
77 | #endif /* CONFIG_CPU_BIG_ENDIAN */ | |
78 | ||
79 | #ifdef __ASSEMBLY__ | |
80 | #define __emit_inst(x) .long __INSTR_BSWAP(x) | |
81 | #else /* __ASSEMBLY__ */ | |
82 | #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" | |
83 | #endif /* __ASSEMBLY__ */ | |
84 | ||
85 | #endif /* CONFIG_BROKEN_GAS_INST */ | |
86 | ||
47863d41 MR |
87 | #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) |
88 | #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) | |
fd872fd8 | 89 | #define REG_PSTATE_SSBS_IMM sys_reg(0, 3, 4, 0, 1) |
47863d41 MR |
90 | |
91 | #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \ | |
92 | (!!x)<<8 | 0x1f) | |
93 | #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \ | |
94 | (!!x)<<8 | 0x1f) | |
fd872fd8 WD |
95 | #define SET_PSTATE_SSBS(x) __emit_inst(0xd5000000 | REG_PSTATE_SSBS_IMM | \ |
96 | (!!x)<<8 | 0x1f) | |
47863d41 | 97 | |
4dc52925 MR |
98 | #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) |
99 | #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) | |
100 | #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) | |
101 | ||
d9801207 MR |
102 | #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) |
103 | #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) | |
104 | #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) | |
105 | #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) | |
106 | #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) | |
107 | #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) | |
108 | #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) | |
109 | #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) | |
110 | #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) | |
111 | #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) | |
112 | #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) | |
113 | #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) | |
114 | #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) | |
115 | #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) | |
116 | #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) | |
117 | #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) | |
118 | #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) | |
119 | #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) | |
120 | #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) | |
121 | #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) | |
122 | #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) | |
123 | #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) | |
124 | ||
3c739b57 SP |
125 | #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) |
126 | #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) | |
127 | #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) | |
128 | ||
129 | #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) | |
130 | #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) | |
131 | #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) | |
14ae7518 | 132 | #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) |
3c739b57 SP |
133 | #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) |
134 | #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) | |
135 | #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) | |
136 | #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) | |
137 | ||
138 | #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) | |
139 | #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) | |
140 | #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) | |
141 | #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) | |
142 | #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) | |
143 | #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) | |
144 | #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) | |
145 | ||
146 | #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) | |
147 | #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) | |
148 | #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) | |
149 | ||
150 | #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) | |
151 | #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) | |
67236564 | 152 | #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) |
3c739b57 SP |
153 | |
154 | #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) | |
155 | #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) | |
156 | ||
93390c0a DM |
157 | #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) |
158 | #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) | |
159 | ||
3c739b57 SP |
160 | #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) |
161 | #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) | |
162 | ||
163 | #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) | |
164 | #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) | |
406e3087 | 165 | #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) |
3c739b57 | 166 | |
14ae7518 MR |
167 | #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) |
168 | #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) | |
169 | #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) | |
170 | ||
67236564 DM |
171 | #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) |
172 | ||
14ae7518 MR |
173 | #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) |
174 | #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) | |
175 | #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) | |
176 | ||
0e9884fe MR |
177 | #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) |
178 | ||
14ae7518 MR |
179 | #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) |
180 | #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) | |
181 | #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) | |
72ea802d DG |
182 | |
183 | #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) | |
184 | #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) | |
185 | #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) | |
186 | #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) | |
187 | #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) | |
188 | #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) | |
189 | #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) | |
190 | #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) | |
191 | ||
14ae7518 MR |
192 | #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) |
193 | #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) | |
194 | ||
a173c390 WD |
195 | /*** Statistical Profiling Extension ***/ |
196 | /* ID registers */ | |
197 | #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) | |
198 | #define SYS_PMSIDR_EL1_FE_SHIFT 0 | |
199 | #define SYS_PMSIDR_EL1_FT_SHIFT 1 | |
200 | #define SYS_PMSIDR_EL1_FL_SHIFT 2 | |
201 | #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 | |
202 | #define SYS_PMSIDR_EL1_LDS_SHIFT 4 | |
203 | #define SYS_PMSIDR_EL1_ERND_SHIFT 5 | |
204 | #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 | |
205 | #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL | |
206 | #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 | |
207 | #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL | |
208 | #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 | |
209 | #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL | |
210 | ||
211 | #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) | |
212 | #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 | |
213 | #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU | |
214 | #define SYS_PMBIDR_EL1_P_SHIFT 4 | |
215 | #define SYS_PMBIDR_EL1_F_SHIFT 5 | |
216 | ||
217 | /* Sampling controls */ | |
218 | #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) | |
219 | #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 | |
220 | #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 | |
221 | #define SYS_PMSCR_EL1_CX_SHIFT 3 | |
222 | #define SYS_PMSCR_EL1_PA_SHIFT 4 | |
223 | #define SYS_PMSCR_EL1_TS_SHIFT 5 | |
224 | #define SYS_PMSCR_EL1_PCT_SHIFT 6 | |
225 | ||
226 | #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) | |
227 | #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 | |
228 | #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 | |
229 | #define SYS_PMSCR_EL2_CX_SHIFT 3 | |
230 | #define SYS_PMSCR_EL2_PA_SHIFT 4 | |
231 | #define SYS_PMSCR_EL2_TS_SHIFT 5 | |
232 | #define SYS_PMSCR_EL2_PCT_SHIFT 6 | |
233 | ||
234 | #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) | |
235 | ||
236 | #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) | |
237 | #define SYS_PMSIRR_EL1_RND_SHIFT 0 | |
238 | #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 | |
239 | #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL | |
240 | ||
241 | /* Filtering controls */ | |
242 | #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) | |
243 | #define SYS_PMSFCR_EL1_FE_SHIFT 0 | |
244 | #define SYS_PMSFCR_EL1_FT_SHIFT 1 | |
245 | #define SYS_PMSFCR_EL1_FL_SHIFT 2 | |
246 | #define SYS_PMSFCR_EL1_B_SHIFT 16 | |
247 | #define SYS_PMSFCR_EL1_LD_SHIFT 17 | |
248 | #define SYS_PMSFCR_EL1_ST_SHIFT 18 | |
249 | ||
250 | #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) | |
251 | #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL | |
252 | ||
253 | #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) | |
254 | #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 | |
255 | ||
256 | /* Buffer controls */ | |
257 | #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) | |
258 | #define SYS_PMBLIMITR_EL1_E_SHIFT 0 | |
259 | #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 | |
260 | #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL | |
261 | #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) | |
262 | ||
263 | #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) | |
264 | ||
265 | /* Buffer error reporting */ | |
266 | #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) | |
267 | #define SYS_PMBSR_EL1_COLL_SHIFT 16 | |
268 | #define SYS_PMBSR_EL1_S_SHIFT 17 | |
269 | #define SYS_PMBSR_EL1_EA_SHIFT 18 | |
270 | #define SYS_PMBSR_EL1_DL_SHIFT 19 | |
271 | #define SYS_PMBSR_EL1_EC_SHIFT 26 | |
272 | #define SYS_PMBSR_EL1_EC_MASK 0x3fUL | |
273 | ||
274 | #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) | |
275 | #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) | |
276 | #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) | |
277 | ||
278 | #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 | |
279 | #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL | |
280 | ||
281 | #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 | |
282 | #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL | |
283 | ||
284 | #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) | |
285 | ||
286 | /*** End of Statistical Profiling Extension ***/ | |
287 | ||
c7a3c61f MR |
288 | #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) |
289 | #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) | |
290 | ||
14ae7518 MR |
291 | #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) |
292 | #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) | |
293 | ||
294 | #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) | |
47be510b | 295 | #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) |
14ae7518 | 296 | |
eab0b2dc MZ |
297 | #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) |
298 | #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) | |
299 | #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) | |
423de85a | 300 | #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) |
eab0b2dc | 301 | #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) |
0959db6c MR |
302 | #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) |
303 | #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) | |
304 | #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) | |
305 | #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) | |
f9e7449c | 306 | #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) |
0959db6c MR |
307 | #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) |
308 | #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) | |
309 | #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) | |
310 | #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) | |
0e9884fe | 311 | #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) |
43515894 | 312 | #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) |
0e9884fe MR |
313 | #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) |
314 | #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) | |
315 | #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) | |
2724c11a | 316 | #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) |
0e9884fe MR |
317 | #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) |
318 | #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) | |
319 | #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) | |
21bc5281 MR |
320 | #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) |
321 | #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) | |
0e9884fe | 322 | |
14ae7518 MR |
323 | #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) |
324 | #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) | |
325 | ||
326 | #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) | |
327 | ||
328 | #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) | |
329 | #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) | |
330 | ||
331 | #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) | |
332 | ||
3c739b57 SP |
333 | #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) |
334 | #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) | |
335 | ||
c7a3c61f MR |
336 | #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) |
337 | #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) | |
338 | #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) | |
339 | #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) | |
340 | #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) | |
341 | #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) | |
342 | #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) | |
343 | #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) | |
344 | #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) | |
345 | #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) | |
346 | #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) | |
347 | #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) | |
348 | #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) | |
338d4f49 | 349 | |
14ae7518 MR |
350 | #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) |
351 | #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) | |
352 | ||
47863d41 | 353 | #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) |
338d4f49 | 354 | |
147a70ce MR |
355 | #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) |
356 | #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) | |
357 | #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) | |
358 | ||
c7a3c61f MR |
359 | #define __PMEV_op2(n) ((n) & 0x7) |
360 | #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) | |
361 | #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) | |
362 | #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) | |
363 | #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) | |
364 | ||
365 | #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7) | |
366 | ||
67236564 DM |
367 | #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) |
368 | ||
14ae7518 MR |
369 | #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) |
370 | #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) | |
b9da0f1a | 371 | #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) |
14ae7518 MR |
372 | #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) |
373 | ||
dd627dd4 | 374 | #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) |
0e9884fe MR |
375 | #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) |
376 | #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) | |
377 | #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) | |
378 | #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) | |
379 | #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) | |
380 | ||
381 | #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) | |
382 | #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) | |
383 | #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) | |
384 | #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) | |
385 | #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) | |
386 | ||
387 | #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) | |
388 | #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) | |
389 | #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) | |
390 | #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) | |
391 | #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) | |
392 | #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) | |
393 | #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5) | |
394 | #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) | |
395 | ||
396 | #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) | |
397 | #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) | |
398 | #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) | |
399 | #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) | |
400 | #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) | |
401 | #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) | |
402 | #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) | |
403 | #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) | |
404 | #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) | |
405 | ||
406 | #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) | |
407 | #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) | |
408 | #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) | |
409 | #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) | |
410 | #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) | |
411 | #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) | |
412 | #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) | |
413 | #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) | |
414 | #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) | |
338d4f49 | 415 | |
e7227d0e | 416 | /* Common SCTLR_ELx flags. */ |
2a3135c3 | 417 | #define SCTLR_ELx_DSSBS (1UL << 44) |
e7227d0e | 418 | #define SCTLR_ELx_EE (1 << 25) |
5593b09b | 419 | #define SCTLR_ELx_IESB (1 << 21) |
99501991 | 420 | #define SCTLR_ELx_WXN (1 << 19) |
e7227d0e GL |
421 | #define SCTLR_ELx_I (1 << 12) |
422 | #define SCTLR_ELx_SA (1 << 3) | |
423 | #define SCTLR_ELx_C (1 << 2) | |
424 | #define SCTLR_ELx_A (1 << 1) | |
425 | #define SCTLR_ELx_M 1 | |
426 | ||
5593b09b JM |
427 | #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ |
428 | SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) | |
99501991 JM |
429 | |
430 | /* SCTLR_EL2 specific flags. */ | |
d68c1f7f | 431 | #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \ |
d38338e3 ST |
432 | (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \ |
433 | (1 << 29)) | |
99501991 JM |
434 | #define SCTLR_EL2_RES0 ((1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | \ |
435 | (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \ | |
5593b09b | 436 | (1 << 17) | (1 << 20) | (1 << 24) | (1 << 26) | \ |
203515b0 | 437 | (1 << 27) | (1 << 30) | (1 << 31) | \ |
2a3135c3 | 438 | (0xffffefffUL << 32)) |
99501991 JM |
439 | |
440 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
441 | #define ENDIAN_SET_EL2 SCTLR_ELx_EE | |
442 | #define ENDIAN_CLEAR_EL2 0 | |
443 | #else | |
444 | #define ENDIAN_SET_EL2 0 | |
445 | #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE | |
446 | #endif | |
447 | ||
448 | /* SCTLR_EL2 value used for the hyp-stub */ | |
5593b09b | 449 | #define SCTLR_EL2_SET (SCTLR_ELx_IESB | ENDIAN_SET_EL2 | SCTLR_EL2_RES1) |
99501991 JM |
450 | #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ |
451 | SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \ | |
2a3135c3 | 452 | SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0) |
99501991 | 453 | |
203515b0 MR |
454 | #if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffff |
455 | #error "Inconsistent SCTLR_EL2 set/clear bits" | |
456 | #endif | |
e7227d0e GL |
457 | |
458 | /* SCTLR_EL1 specific flags. */ | |
7dd01aef | 459 | #define SCTLR_EL1_UCI (1 << 26) |
99501991 | 460 | #define SCTLR_EL1_E0E (1 << 24) |
e7227d0e | 461 | #define SCTLR_EL1_SPAN (1 << 23) |
99501991 JM |
462 | #define SCTLR_EL1_NTWE (1 << 18) |
463 | #define SCTLR_EL1_NTWI (1 << 16) | |
116c81f4 | 464 | #define SCTLR_EL1_UCT (1 << 15) |
99501991 JM |
465 | #define SCTLR_EL1_DZE (1 << 14) |
466 | #define SCTLR_EL1_UMA (1 << 9) | |
e7227d0e | 467 | #define SCTLR_EL1_SED (1 << 8) |
99501991 | 468 | #define SCTLR_EL1_ITD (1 << 7) |
e7227d0e | 469 | #define SCTLR_EL1_CP15BEN (1 << 5) |
99501991 JM |
470 | #define SCTLR_EL1_SA0 (1 << 4) |
471 | ||
472 | #define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \ | |
473 | (1 << 29)) | |
474 | #define SCTLR_EL1_RES0 ((1 << 6) | (1 << 10) | (1 << 13) | (1 << 17) | \ | |
203515b0 | 475 | (1 << 27) | (1 << 30) | (1 << 31) | \ |
2a3135c3 | 476 | (0xffffefffUL << 32)) |
99501991 JM |
477 | |
478 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
479 | #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) | |
480 | #define ENDIAN_CLEAR_EL1 0 | |
481 | #else | |
482 | #define ENDIAN_SET_EL1 0 | |
483 | #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) | |
484 | #endif | |
485 | ||
486 | #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\ | |
487 | SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\ | |
488 | SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_NTWI |\ | |
5593b09b JM |
489 | SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\ |
490 | ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1) | |
99501991 JM |
491 | #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\ |
492 | SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\ | |
2a3135c3 | 493 | SCTLR_ELx_DSSBS | SCTLR_EL1_RES0) |
99501991 | 494 | |
203515b0 MR |
495 | #if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffff |
496 | #error "Inconsistent SCTLR_EL1 set/clear bits" | |
497 | #endif | |
3c739b57 | 498 | |
3c739b57 | 499 | /* id_aa64isar0 */ |
a060f8f2 | 500 | #define ID_AA64ISAR0_TS_SHIFT 52 |
fb0e26e9 | 501 | #define ID_AA64ISAR0_FHM_SHIFT 48 |
f5e035f8 SP |
502 | #define ID_AA64ISAR0_DP_SHIFT 44 |
503 | #define ID_AA64ISAR0_SM4_SHIFT 40 | |
504 | #define ID_AA64ISAR0_SM3_SHIFT 36 | |
505 | #define ID_AA64ISAR0_SHA3_SHIFT 32 | |
3c739b57 SP |
506 | #define ID_AA64ISAR0_RDM_SHIFT 28 |
507 | #define ID_AA64ISAR0_ATOMICS_SHIFT 20 | |
508 | #define ID_AA64ISAR0_CRC32_SHIFT 16 | |
509 | #define ID_AA64ISAR0_SHA2_SHIFT 12 | |
510 | #define ID_AA64ISAR0_SHA1_SHIFT 8 | |
511 | #define ID_AA64ISAR0_AES_SHIFT 4 | |
512 | ||
c8c3798d | 513 | /* id_aa64isar1 */ |
c651aae5 | 514 | #define ID_AA64ISAR1_LRCPC_SHIFT 20 |
cb567e79 | 515 | #define ID_AA64ISAR1_FCMA_SHIFT 16 |
c8c3798d | 516 | #define ID_AA64ISAR1_JSCVT_SHIFT 12 |
7aac405e | 517 | #define ID_AA64ISAR1_DPB_SHIFT 0 |
c8c3798d | 518 | |
3c739b57 | 519 | /* id_aa64pfr0 */ |
d272070a | 520 | #define ID_AA64PFR0_CSV3_SHIFT 60 |
9a5fa750 | 521 | #define ID_AA64PFR0_CSV2_SHIFT 56 |
a060f8f2 | 522 | #define ID_AA64PFR0_DIT_SHIFT 48 |
67236564 | 523 | #define ID_AA64PFR0_SVE_SHIFT 32 |
9207a173 | 524 | #define ID_AA64PFR0_RAS_SHIFT 28 |
3c739b57 SP |
525 | #define ID_AA64PFR0_GIC_SHIFT 24 |
526 | #define ID_AA64PFR0_ASIMD_SHIFT 20 | |
527 | #define ID_AA64PFR0_FP_SHIFT 16 | |
528 | #define ID_AA64PFR0_EL3_SHIFT 12 | |
529 | #define ID_AA64PFR0_EL2_SHIFT 8 | |
530 | #define ID_AA64PFR0_EL1_SHIFT 4 | |
531 | #define ID_AA64PFR0_EL0_SHIFT 0 | |
532 | ||
67236564 | 533 | #define ID_AA64PFR0_SVE 0x1 |
9207a173 | 534 | #define ID_AA64PFR0_RAS_V1 0x1 |
3c739b57 SP |
535 | #define ID_AA64PFR0_FP_NI 0xf |
536 | #define ID_AA64PFR0_FP_SUPPORTED 0x0 | |
537 | #define ID_AA64PFR0_ASIMD_NI 0xf | |
538 | #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 | |
539 | #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 | |
540 | #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 | |
c80aba80 | 541 | #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 |
3c739b57 | 542 | |
2a3135c3 WD |
543 | /* id_aa64pfr1 */ |
544 | #define ID_AA64PFR1_SSBS_SHIFT 4 | |
545 | ||
546 | #define ID_AA64PFR1_SSBS_PSTATE_NI 0 | |
547 | #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 | |
548 | #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 | |
549 | ||
3c739b57 SP |
550 | /* id_aa64mmfr0 */ |
551 | #define ID_AA64MMFR0_TGRAN4_SHIFT 28 | |
552 | #define ID_AA64MMFR0_TGRAN64_SHIFT 24 | |
553 | #define ID_AA64MMFR0_TGRAN16_SHIFT 20 | |
cdcf817b | 554 | #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 |
3c739b57 | 555 | #define ID_AA64MMFR0_SNSMEM_SHIFT 12 |
cdcf817b | 556 | #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 |
3c739b57 SP |
557 | #define ID_AA64MMFR0_ASID_SHIFT 4 |
558 | #define ID_AA64MMFR0_PARANGE_SHIFT 0 | |
559 | ||
560 | #define ID_AA64MMFR0_TGRAN4_NI 0xf | |
561 | #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 | |
562 | #define ID_AA64MMFR0_TGRAN64_NI 0xf | |
563 | #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 | |
564 | #define ID_AA64MMFR0_TGRAN16_NI 0x0 | |
565 | #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 | |
566 | ||
567 | /* id_aa64mmfr1 */ | |
568 | #define ID_AA64MMFR1_PAN_SHIFT 20 | |
569 | #define ID_AA64MMFR1_LOR_SHIFT 16 | |
570 | #define ID_AA64MMFR1_HPD_SHIFT 12 | |
571 | #define ID_AA64MMFR1_VHE_SHIFT 8 | |
572 | #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 | |
573 | #define ID_AA64MMFR1_HADBS_SHIFT 0 | |
574 | ||
cb678d60 SP |
575 | #define ID_AA64MMFR1_VMIDBITS_8 0 |
576 | #define ID_AA64MMFR1_VMIDBITS_16 2 | |
577 | ||
406e3087 | 578 | /* id_aa64mmfr2 */ |
a060f8f2 | 579 | #define ID_AA64MMFR2_AT_SHIFT 32 |
7d7b4ae4 KW |
580 | #define ID_AA64MMFR2_LVA_SHIFT 16 |
581 | #define ID_AA64MMFR2_IESB_SHIFT 12 | |
582 | #define ID_AA64MMFR2_LSM_SHIFT 8 | |
406e3087 | 583 | #define ID_AA64MMFR2_UAO_SHIFT 4 |
7d7b4ae4 | 584 | #define ID_AA64MMFR2_CNP_SHIFT 0 |
406e3087 | 585 | |
3c739b57 | 586 | /* id_aa64dfr0 */ |
f31deaad | 587 | #define ID_AA64DFR0_PMSVER_SHIFT 32 |
3c739b57 SP |
588 | #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 |
589 | #define ID_AA64DFR0_WRPS_SHIFT 20 | |
590 | #define ID_AA64DFR0_BRPS_SHIFT 12 | |
591 | #define ID_AA64DFR0_PMUVER_SHIFT 8 | |
592 | #define ID_AA64DFR0_TRACEVER_SHIFT 4 | |
593 | #define ID_AA64DFR0_DEBUGVER_SHIFT 0 | |
594 | ||
595 | #define ID_ISAR5_RDM_SHIFT 24 | |
596 | #define ID_ISAR5_CRC32_SHIFT 16 | |
597 | #define ID_ISAR5_SHA2_SHIFT 12 | |
598 | #define ID_ISAR5_SHA1_SHIFT 8 | |
599 | #define ID_ISAR5_AES_SHIFT 4 | |
600 | #define ID_ISAR5_SEVL_SHIFT 0 | |
601 | ||
602 | #define MVFR0_FPROUND_SHIFT 28 | |
603 | #define MVFR0_FPSHVEC_SHIFT 24 | |
604 | #define MVFR0_FPSQRT_SHIFT 20 | |
605 | #define MVFR0_FPDIVIDE_SHIFT 16 | |
606 | #define MVFR0_FPTRAP_SHIFT 12 | |
607 | #define MVFR0_FPDP_SHIFT 8 | |
608 | #define MVFR0_FPSP_SHIFT 4 | |
609 | #define MVFR0_SIMD_SHIFT 0 | |
610 | ||
611 | #define MVFR1_SIMDFMAC_SHIFT 28 | |
612 | #define MVFR1_FPHP_SHIFT 24 | |
613 | #define MVFR1_SIMDHP_SHIFT 20 | |
614 | #define MVFR1_SIMDSP_SHIFT 16 | |
615 | #define MVFR1_SIMDINT_SHIFT 12 | |
616 | #define MVFR1_SIMDLS_SHIFT 8 | |
617 | #define MVFR1_FPDNAN_SHIFT 4 | |
618 | #define MVFR1_FPFTZ_SHIFT 0 | |
619 | ||
4bf8b96e SP |
620 | |
621 | #define ID_AA64MMFR0_TGRAN4_SHIFT 28 | |
622 | #define ID_AA64MMFR0_TGRAN64_SHIFT 24 | |
623 | #define ID_AA64MMFR0_TGRAN16_SHIFT 20 | |
624 | ||
625 | #define ID_AA64MMFR0_TGRAN4_NI 0xf | |
626 | #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 | |
627 | #define ID_AA64MMFR0_TGRAN64_NI 0xf | |
628 | #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 | |
629 | #define ID_AA64MMFR0_TGRAN16_NI 0x0 | |
630 | #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 | |
631 | ||
632 | #if defined(CONFIG_ARM64_4K_PAGES) | |
633 | #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT | |
634 | #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED | |
44eaacf1 SP |
635 | #elif defined(CONFIG_ARM64_16K_PAGES) |
636 | #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT | |
637 | #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED | |
4bf8b96e SP |
638 | #elif defined(CONFIG_ARM64_64K_PAGES) |
639 | #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT | |
640 | #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED | |
641 | #endif | |
642 | ||
77c97b4e | 643 | |
67236564 DM |
644 | /* |
645 | * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which | |
646 | * are reserved by the SVE architecture for future expansion of the LEN | |
647 | * field, with compatible semantics. | |
648 | */ | |
649 | #define ZCR_ELx_LEN_SHIFT 0 | |
650 | #define ZCR_ELx_LEN_SIZE 9 | |
651 | #define ZCR_ELx_LEN_MASK 0x1ff | |
652 | ||
653 | #define CPACR_EL1_ZEN_EL1EN (1 << 16) /* enable EL1 access */ | |
654 | #define CPACR_EL1_ZEN_EL0EN (1 << 17) /* enable EL0 access, if EL1EN set */ | |
655 | #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) | |
656 | ||
657 | ||
77c97b4e SP |
658 | /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ |
659 | #define SYS_MPIDR_SAFE_VAL (1UL << 31) | |
660 | ||
72c58395 CM |
661 | #ifdef __ASSEMBLY__ |
662 | ||
663 | .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 | |
7abc7d83 | 664 | .equ .L__reg_num_x\num, \num |
72c58395 | 665 | .endr |
7abc7d83 | 666 | .equ .L__reg_num_xzr, 31 |
72c58395 CM |
667 | |
668 | .macro mrs_s, rt, sreg | |
cd9e1927 | 669 | __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) |
72c58395 CM |
670 | .endm |
671 | ||
672 | .macro msr_s, sreg, rt | |
cd9e1927 | 673 | __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) |
72c58395 CM |
674 | .endm |
675 | ||
676 | #else | |
677 | ||
99501991 | 678 | #include <linux/build_bug.h> |
3600c2fd MR |
679 | #include <linux/types.h> |
680 | ||
72c58395 CM |
681 | asm( |
682 | " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" | |
7abc7d83 | 683 | " .equ .L__reg_num_x\\num, \\num\n" |
72c58395 | 684 | " .endr\n" |
7abc7d83 | 685 | " .equ .L__reg_num_xzr, 31\n" |
72c58395 CM |
686 | "\n" |
687 | " .macro mrs_s, rt, sreg\n" | |
cd9e1927 | 688 | __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) |
72c58395 CM |
689 | " .endm\n" |
690 | "\n" | |
691 | " .macro msr_s, sreg, rt\n" | |
cd9e1927 | 692 | __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) |
72c58395 CM |
693 | " .endm\n" |
694 | ); | |
695 | ||
3600c2fd MR |
696 | /* |
697 | * Unlike read_cpuid, calls to read_sysreg are never expected to be | |
698 | * optimized away or replaced with synthetic values. | |
699 | */ | |
700 | #define read_sysreg(r) ({ \ | |
701 | u64 __val; \ | |
702 | asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ | |
703 | __val; \ | |
704 | }) | |
705 | ||
7aff4a2d MR |
706 | /* |
707 | * The "Z" constraint normally means a zero immediate, but when combined with | |
708 | * the "%x0" template means XZR. | |
709 | */ | |
3600c2fd | 710 | #define write_sysreg(v, r) do { \ |
d0153c7f | 711 | u64 __val = (u64)(v); \ |
7aff4a2d MR |
712 | asm volatile("msr " __stringify(r) ", %x0" \ |
713 | : : "rZ" (__val)); \ | |
3600c2fd MR |
714 | } while (0) |
715 | ||
8a71f0c6 WD |
716 | /* |
717 | * For registers without architectural names, or simply unsupported by | |
718 | * GAS. | |
719 | */ | |
720 | #define read_sysreg_s(r) ({ \ | |
721 | u64 __val; \ | |
722 | asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \ | |
723 | __val; \ | |
724 | }) | |
725 | ||
726 | #define write_sysreg_s(v, r) do { \ | |
d0153c7f | 727 | u64 __val = (u64)(v); \ |
91cb163e | 728 | asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ |
8a71f0c6 WD |
729 | } while (0) |
730 | ||
99dcb0bc MR |
731 | /* |
732 | * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the | |
733 | * set mask are set. Other bits are left as-is. | |
734 | */ | |
735 | #define sysreg_clear_set(sysreg, clear, set) do { \ | |
736 | u64 __scs_val = read_sysreg(sysreg); \ | |
737 | u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ | |
738 | if (__scs_new != __scs_val) \ | |
739 | write_sysreg(__scs_new, sysreg); \ | |
740 | } while (0) | |
741 | ||
adf75899 MR |
742 | static inline void config_sctlr_el1(u32 clear, u32 set) |
743 | { | |
744 | u32 val; | |
745 | ||
746 | val = read_sysreg(sctlr_el1); | |
747 | val &= ~clear; | |
748 | val |= set; | |
749 | write_sysreg(val, sctlr_el1); | |
750 | } | |
751 | ||
72c58395 CM |
752 | #endif |
753 | ||
754 | #endif /* __ASM_SYSREG_H */ |