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0be7320a CM |
1 | /* |
2 | * Based on arch/arm/kernel/asm-offsets.c | |
3 | * | |
4 | * Copyright (C) 1995-2003 Russell King | |
5 | * 2001-2002 Keith Owens | |
6 | * Copyright (C) 2012 ARM Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/sched.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/dma-mapping.h> | |
c3eb5b14 | 24 | #include <linux/kvm_host.h> |
0be7320a CM |
25 | #include <asm/thread_info.h> |
26 | #include <asm/memory.h> | |
95322526 LP |
27 | #include <asm/smp_plat.h> |
28 | #include <asm/suspend.h> | |
0be7320a CM |
29 | #include <asm/vdso_datapage.h> |
30 | #include <linux/kbuild.h> | |
31 | ||
32 | int main(void) | |
33 | { | |
34 | DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); | |
35 | BLANK(); | |
36 | DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); | |
37 | DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); | |
38 | DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); | |
39 | DEFINE(TI_TASK, offsetof(struct thread_info, task)); | |
0be7320a CM |
40 | DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); |
41 | BLANK(); | |
42 | DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context)); | |
43 | BLANK(); | |
44 | DEFINE(S_X0, offsetof(struct pt_regs, regs[0])); | |
45 | DEFINE(S_X1, offsetof(struct pt_regs, regs[1])); | |
46 | DEFINE(S_X2, offsetof(struct pt_regs, regs[2])); | |
47 | DEFINE(S_X3, offsetof(struct pt_regs, regs[3])); | |
48 | DEFINE(S_X4, offsetof(struct pt_regs, regs[4])); | |
49 | DEFINE(S_X5, offsetof(struct pt_regs, regs[5])); | |
50 | DEFINE(S_X6, offsetof(struct pt_regs, regs[6])); | |
51 | DEFINE(S_X7, offsetof(struct pt_regs, regs[7])); | |
52 | DEFINE(S_LR, offsetof(struct pt_regs, regs[30])); | |
53 | DEFINE(S_SP, offsetof(struct pt_regs, sp)); | |
54 | #ifdef CONFIG_COMPAT | |
55 | DEFINE(S_COMPAT_SP, offsetof(struct pt_regs, compat_sp)); | |
56 | #endif | |
57 | DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate)); | |
58 | DEFINE(S_PC, offsetof(struct pt_regs, pc)); | |
59 | DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0)); | |
60 | DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno)); | |
61 | DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); | |
62 | BLANK(); | |
63 | DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); | |
64 | BLANK(); | |
65 | DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm)); | |
66 | DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags)); | |
67 | BLANK(); | |
68 | DEFINE(VM_EXEC, VM_EXEC); | |
69 | BLANK(); | |
70 | DEFINE(PAGE_SZ, PAGE_SIZE); | |
71 | BLANK(); | |
0be7320a CM |
72 | DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); |
73 | DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); | |
74 | DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE); | |
75 | BLANK(); | |
76 | DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); | |
77 | DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC); | |
78 | DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC); | |
79 | DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE); | |
80 | DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE); | |
81 | DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC); | |
82 | DEFINE(NSEC_PER_SEC, NSEC_PER_SEC); | |
83 | BLANK(); | |
84 | DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last)); | |
85 | DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec)); | |
86 | DEFINE(VDSO_XTIME_CLK_NSEC, offsetof(struct vdso_data, xtime_clock_nsec)); | |
87 | DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec)); | |
88 | DEFINE(VDSO_XTIME_CRS_NSEC, offsetof(struct vdso_data, xtime_coarse_nsec)); | |
89 | DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec)); | |
90 | DEFINE(VDSO_WTM_CLK_NSEC, offsetof(struct vdso_data, wtm_clock_nsec)); | |
91 | DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count)); | |
92 | DEFINE(VDSO_CS_MULT, offsetof(struct vdso_data, cs_mult)); | |
93 | DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift)); | |
94 | DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest)); | |
95 | DEFINE(VDSO_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime)); | |
96 | DEFINE(VDSO_USE_SYSCALL, offsetof(struct vdso_data, use_syscall)); | |
97 | BLANK(); | |
98 | DEFINE(TVAL_TV_SEC, offsetof(struct timeval, tv_sec)); | |
99 | DEFINE(TVAL_TV_USEC, offsetof(struct timeval, tv_usec)); | |
100 | DEFINE(TSPEC_TV_SEC, offsetof(struct timespec, tv_sec)); | |
101 | DEFINE(TSPEC_TV_NSEC, offsetof(struct timespec, tv_nsec)); | |
102 | BLANK(); | |
103 | DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest)); | |
104 | DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime)); | |
55c7401d MZ |
105 | BLANK(); |
106 | #ifdef CONFIG_KVM_ARM_HOST | |
107 | DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt)); | |
108 | DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs)); | |
109 | DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs)); | |
110 | DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs)); | |
111 | DEFINE(CPU_SP_EL1, offsetof(struct kvm_regs, sp_el1)); | |
112 | DEFINE(CPU_ELR_EL1, offsetof(struct kvm_regs, elr_el1)); | |
113 | DEFINE(CPU_SPSR, offsetof(struct kvm_regs, spsr)); | |
114 | DEFINE(CPU_SYSREGS, offsetof(struct kvm_cpu_context, sys_regs)); | |
115 | DEFINE(VCPU_ESR_EL2, offsetof(struct kvm_vcpu, arch.fault.esr_el2)); | |
116 | DEFINE(VCPU_FAR_EL2, offsetof(struct kvm_vcpu, arch.fault.far_el2)); | |
117 | DEFINE(VCPU_HPFAR_EL2, offsetof(struct kvm_vcpu, arch.fault.hpfar_el2)); | |
b0e626b3 | 118 | DEFINE(VCPU_DEBUG_FLAGS, offsetof(struct kvm_vcpu, arch.debug_flags)); |
84e690bf AB |
119 | DEFINE(VCPU_DEBUG_PTR, offsetof(struct kvm_vcpu, arch.debug_ptr)); |
120 | DEFINE(DEBUG_BCR, offsetof(struct kvm_guest_debug_arch, dbg_bcr)); | |
121 | DEFINE(DEBUG_BVR, offsetof(struct kvm_guest_debug_arch, dbg_bvr)); | |
122 | DEFINE(DEBUG_WCR, offsetof(struct kvm_guest_debug_arch, dbg_wcr)); | |
123 | DEFINE(DEBUG_WVR, offsetof(struct kvm_guest_debug_arch, dbg_wvr)); | |
55c7401d | 124 | DEFINE(VCPU_HCR_EL2, offsetof(struct kvm_vcpu, arch.hcr_el2)); |
56c7f5e7 | 125 | DEFINE(VCPU_MDCR_EL2, offsetof(struct kvm_vcpu, arch.mdcr_el2)); |
55c7401d MZ |
126 | DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines)); |
127 | DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context)); | |
84e690bf | 128 | DEFINE(VCPU_HOST_DEBUG_STATE, offsetof(struct kvm_vcpu, arch.host_debug_state)); |
55c7401d MZ |
129 | DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl)); |
130 | DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval)); | |
131 | DEFINE(KVM_TIMER_CNTVOFF, offsetof(struct kvm, arch.timer.cntvoff)); | |
132 | DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled)); | |
133 | DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm)); | |
134 | DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu)); | |
eede821d MZ |
135 | DEFINE(VGIC_V2_CPU_HCR, offsetof(struct vgic_cpu, vgic_v2.vgic_hcr)); |
136 | DEFINE(VGIC_V2_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr)); | |
137 | DEFINE(VGIC_V2_CPU_MISR, offsetof(struct vgic_cpu, vgic_v2.vgic_misr)); | |
138 | DEFINE(VGIC_V2_CPU_EISR, offsetof(struct vgic_cpu, vgic_v2.vgic_eisr)); | |
139 | DEFINE(VGIC_V2_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr)); | |
140 | DEFINE(VGIC_V2_CPU_APR, offsetof(struct vgic_cpu, vgic_v2.vgic_apr)); | |
141 | DEFINE(VGIC_V2_CPU_LR, offsetof(struct vgic_cpu, vgic_v2.vgic_lr)); | |
2f5fa41a | 142 | DEFINE(VGIC_V3_CPU_SRE, offsetof(struct vgic_cpu, vgic_v3.vgic_sre)); |
754d3772 MZ |
143 | DEFINE(VGIC_V3_CPU_HCR, offsetof(struct vgic_cpu, vgic_v3.vgic_hcr)); |
144 | DEFINE(VGIC_V3_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v3.vgic_vmcr)); | |
145 | DEFINE(VGIC_V3_CPU_MISR, offsetof(struct vgic_cpu, vgic_v3.vgic_misr)); | |
146 | DEFINE(VGIC_V3_CPU_EISR, offsetof(struct vgic_cpu, vgic_v3.vgic_eisr)); | |
147 | DEFINE(VGIC_V3_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v3.vgic_elrsr)); | |
148 | DEFINE(VGIC_V3_CPU_AP0R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap0r)); | |
149 | DEFINE(VGIC_V3_CPU_AP1R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap1r)); | |
150 | DEFINE(VGIC_V3_CPU_LR, offsetof(struct vgic_cpu, vgic_v3.vgic_lr)); | |
55c7401d MZ |
151 | DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr)); |
152 | DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr)); | |
153 | DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base)); | |
95322526 | 154 | #endif |
af3cfdbf | 155 | #ifdef CONFIG_CPU_PM |
95322526 LP |
156 | DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx)); |
157 | DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp)); | |
158 | DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask)); | |
159 | DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff)); | |
160 | DEFINE(SLEEP_SAVE_SP_SZ, sizeof(struct sleep_save_sp)); | |
161 | DEFINE(SLEEP_SAVE_SP_PHYS, offsetof(struct sleep_save_sp, save_ptr_stash_phys)); | |
162 | DEFINE(SLEEP_SAVE_SP_VIRT, offsetof(struct sleep_save_sp, save_ptr_stash)); | |
55c7401d | 163 | #endif |
0be7320a CM |
164 | return 0; |
165 | } |