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359b7064 MZ |
1 | /* |
2 | * Contains CPU feature definitions | |
3 | * | |
4 | * Copyright (C) 2015 ARM Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
9cdf8ec4 | 19 | #define pr_fmt(fmt) "CPU features: " fmt |
359b7064 | 20 | |
3c739b57 | 21 | #include <linux/bsearch.h> |
2a6dcb2b | 22 | #include <linux/cpumask.h> |
3c739b57 | 23 | #include <linux/sort.h> |
2a6dcb2b | 24 | #include <linux/stop_machine.h> |
359b7064 | 25 | #include <linux/types.h> |
2077be67 | 26 | #include <linux/mm.h> |
359b7064 MZ |
27 | #include <asm/cpu.h> |
28 | #include <asm/cpufeature.h> | |
dbb4e152 | 29 | #include <asm/cpu_ops.h> |
13f417f3 | 30 | #include <asm/mmu_context.h> |
338d4f49 | 31 | #include <asm/processor.h> |
cdcf817b | 32 | #include <asm/sysreg.h> |
77c97b4e | 33 | #include <asm/traps.h> |
d88701be | 34 | #include <asm/virt.h> |
359b7064 | 35 | |
9cdf8ec4 SP |
36 | unsigned long elf_hwcap __read_mostly; |
37 | EXPORT_SYMBOL_GPL(elf_hwcap); | |
38 | ||
39 | #ifdef CONFIG_COMPAT | |
40 | #define COMPAT_ELF_HWCAP_DEFAULT \ | |
41 | (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ | |
42 | COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ | |
43 | COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ | |
44 | COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ | |
45 | COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ | |
46 | COMPAT_HWCAP_LPAE) | |
47 | unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; | |
48 | unsigned int compat_elf_hwcap2 __read_mostly; | |
49 | #endif | |
50 | ||
51 | DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); | |
4b65a5db | 52 | EXPORT_SYMBOL(cpu_hwcaps); |
9cdf8ec4 | 53 | |
8effeaaf MR |
54 | static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p) |
55 | { | |
56 | /* file-wide pr_fmt adds "CPU features: " prefix */ | |
57 | pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); | |
58 | return 0; | |
59 | } | |
60 | ||
61 | static struct notifier_block cpu_hwcaps_notifier = { | |
62 | .notifier_call = dump_cpu_hwcaps | |
63 | }; | |
64 | ||
65 | static int __init register_cpu_hwcaps_dumper(void) | |
66 | { | |
67 | atomic_notifier_chain_register(&panic_notifier_list, | |
68 | &cpu_hwcaps_notifier); | |
69 | return 0; | |
70 | } | |
71 | __initcall(register_cpu_hwcaps_dumper); | |
72 | ||
efd9e03f CM |
73 | DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); |
74 | EXPORT_SYMBOL(cpu_hwcap_keys); | |
75 | ||
fe4fbdbc | 76 | #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
3c739b57 | 77 | { \ |
4f0a606b | 78 | .sign = SIGNED, \ |
fe4fbdbc | 79 | .visible = VISIBLE, \ |
3c739b57 SP |
80 | .strict = STRICT, \ |
81 | .type = TYPE, \ | |
82 | .shift = SHIFT, \ | |
83 | .width = WIDTH, \ | |
84 | .safe_val = SAFE_VAL, \ | |
85 | } | |
86 | ||
0710cfdb | 87 | /* Define a feature with unsigned values */ |
fe4fbdbc SP |
88 | #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
89 | __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) | |
4f0a606b | 90 | |
0710cfdb | 91 | /* Define a feature with a signed value */ |
fe4fbdbc SP |
92 | #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
93 | __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) | |
0710cfdb | 94 | |
3c739b57 SP |
95 | #define ARM64_FTR_END \ |
96 | { \ | |
97 | .width = 0, \ | |
98 | } | |
99 | ||
70544196 JM |
100 | /* meta feature for alternatives */ |
101 | static bool __maybe_unused | |
92406f0c SP |
102 | cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); |
103 | ||
70544196 | 104 | |
4aa8a472 SP |
105 | /* |
106 | * NOTE: Any changes to the visibility of features should be kept in | |
107 | * sync with the documentation of the CPU feature register ABI. | |
108 | */ | |
5e49d73c | 109 | static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { |
fe4fbdbc SP |
110 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), |
111 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), | |
112 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), | |
113 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), | |
114 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), | |
115 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), | |
3c739b57 SP |
116 | ARM64_FTR_END, |
117 | }; | |
118 | ||
c8c3798d | 119 | static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { |
c651aae5 | 120 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), |
cb567e79 | 121 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), |
c8c3798d | 122 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), |
8795ded3 | 123 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_DPB_SHIFT, 4, 0), |
c8c3798d SP |
124 | ARM64_FTR_END, |
125 | }; | |
126 | ||
5e49d73c | 127 | static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { |
78b89248 | 128 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), |
fe4fbdbc SP |
129 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), |
130 | S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), | |
131 | S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), | |
3c739b57 | 132 | /* Linux doesn't care about the EL3 */ |
fe4fbdbc SP |
133 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0), |
134 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0), | |
135 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), | |
136 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), | |
3c739b57 SP |
137 | ARM64_FTR_END, |
138 | }; | |
139 | ||
5e49d73c | 140 | static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { |
fe4fbdbc SP |
141 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), |
142 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), | |
143 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), | |
144 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), | |
3c739b57 | 145 | /* Linux shouldn't care about secure memory */ |
fe4fbdbc SP |
146 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), |
147 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), | |
148 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0), | |
3c739b57 SP |
149 | /* |
150 | * Differing PARange is fine as long as all peripherals and memory are mapped | |
151 | * within the minimum PARange of all CPUs | |
152 | */ | |
fe4fbdbc | 153 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), |
3c739b57 SP |
154 | ARM64_FTR_END, |
155 | }; | |
156 | ||
5e49d73c | 157 | static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { |
fe4fbdbc SP |
158 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), |
159 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0), | |
160 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0), | |
161 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0), | |
162 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), | |
163 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), | |
3c739b57 SP |
164 | ARM64_FTR_END, |
165 | }; | |
166 | ||
5e49d73c | 167 | static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { |
fe4fbdbc SP |
168 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0), |
169 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0), | |
170 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0), | |
171 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0), | |
172 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0), | |
406e3087 JM |
173 | ARM64_FTR_END, |
174 | }; | |
175 | ||
5e49d73c | 176 | static const struct arm64_ftr_bits ftr_ctr[] = { |
fe4fbdbc SP |
177 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ |
178 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ | |
179 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ | |
180 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ | |
3c739b57 SP |
181 | /* |
182 | * Linux can handle differing I-cache policies. Userspace JITs will | |
ee7bc638 | 183 | * make use of *minLine. |
155433cb | 184 | * If we have differing I-cache policies, report it as the weakest - VIPT. |
3c739b57 | 185 | */ |
155433cb | 186 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ |
fe4fbdbc | 187 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */ |
3c739b57 SP |
188 | ARM64_FTR_END, |
189 | }; | |
190 | ||
675b0563 AB |
191 | struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { |
192 | .name = "SYS_CTR_EL0", | |
193 | .ftr_bits = ftr_ctr | |
194 | }; | |
195 | ||
5e49d73c | 196 | static const struct arm64_ftr_bits ftr_id_mmfr0[] = { |
fe4fbdbc SP |
197 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */ |
198 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */ | |
199 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ | |
200 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */ | |
201 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */ | |
202 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */ | |
203 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */ | |
204 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */ | |
3c739b57 SP |
205 | ARM64_FTR_END, |
206 | }; | |
207 | ||
5e49d73c | 208 | static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { |
fe4fbdbc SP |
209 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), |
210 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), | |
211 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), | |
212 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), | |
213 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), | |
b20d1ba3 WD |
214 | /* |
215 | * We can instantiate multiple PMU instances with different levels | |
216 | * of support. | |
fe4fbdbc SP |
217 | */ |
218 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), | |
219 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), | |
220 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), | |
3c739b57 SP |
221 | ARM64_FTR_END, |
222 | }; | |
223 | ||
5e49d73c | 224 | static const struct arm64_ftr_bits ftr_mvfr2[] = { |
fe4fbdbc SP |
225 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */ |
226 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */ | |
3c739b57 SP |
227 | ARM64_FTR_END, |
228 | }; | |
229 | ||
5e49d73c | 230 | static const struct arm64_ftr_bits ftr_dczid[] = { |
fe4fbdbc SP |
231 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ |
232 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ | |
3c739b57 SP |
233 | ARM64_FTR_END, |
234 | }; | |
235 | ||
236 | ||
5e49d73c | 237 | static const struct arm64_ftr_bits ftr_id_isar5[] = { |
fe4fbdbc SP |
238 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0), |
239 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0), | |
240 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0), | |
241 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0), | |
242 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0), | |
243 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0), | |
3c739b57 SP |
244 | ARM64_FTR_END, |
245 | }; | |
246 | ||
5e49d73c | 247 | static const struct arm64_ftr_bits ftr_id_mmfr4[] = { |
fe4fbdbc | 248 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */ |
3c739b57 SP |
249 | ARM64_FTR_END, |
250 | }; | |
251 | ||
5e49d73c | 252 | static const struct arm64_ftr_bits ftr_id_pfr0[] = { |
fe4fbdbc SP |
253 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */ |
254 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */ | |
255 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */ | |
256 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */ | |
3c739b57 SP |
257 | ARM64_FTR_END, |
258 | }; | |
259 | ||
5e49d73c | 260 | static const struct arm64_ftr_bits ftr_id_dfr0[] = { |
fe4fbdbc SP |
261 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), |
262 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ | |
263 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), | |
264 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), | |
265 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), | |
266 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), | |
267 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), | |
268 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), | |
e5343503 SP |
269 | ARM64_FTR_END, |
270 | }; | |
271 | ||
3c739b57 SP |
272 | /* |
273 | * Common ftr bits for a 32bit register with all hidden, strict | |
274 | * attributes, with 4bit feature fields and a default safe value of | |
275 | * 0. Covers the following 32bit registers: | |
276 | * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] | |
277 | */ | |
5e49d73c | 278 | static const struct arm64_ftr_bits ftr_generic_32bits[] = { |
fe4fbdbc SP |
279 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), |
280 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), | |
281 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), | |
282 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), | |
283 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), | |
284 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), | |
285 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), | |
286 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), | |
3c739b57 SP |
287 | ARM64_FTR_END, |
288 | }; | |
289 | ||
eab43e88 SP |
290 | /* Table for a single 32bit feature value */ |
291 | static const struct arm64_ftr_bits ftr_single32[] = { | |
fe4fbdbc | 292 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), |
3c739b57 SP |
293 | ARM64_FTR_END, |
294 | }; | |
295 | ||
eab43e88 | 296 | static const struct arm64_ftr_bits ftr_raz[] = { |
3c739b57 SP |
297 | ARM64_FTR_END, |
298 | }; | |
299 | ||
6f2b7eef AB |
300 | #define ARM64_FTR_REG(id, table) { \ |
301 | .sys_id = id, \ | |
302 | .reg = &(struct arm64_ftr_reg){ \ | |
3c739b57 SP |
303 | .name = #id, \ |
304 | .ftr_bits = &((table)[0]), \ | |
6f2b7eef | 305 | }} |
3c739b57 | 306 | |
6f2b7eef AB |
307 | static const struct __ftr_reg_entry { |
308 | u32 sys_id; | |
309 | struct arm64_ftr_reg *reg; | |
310 | } arm64_ftr_regs[] = { | |
3c739b57 SP |
311 | |
312 | /* Op1 = 0, CRn = 0, CRm = 1 */ | |
313 | ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), | |
314 | ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), | |
e5343503 | 315 | ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), |
3c739b57 SP |
316 | ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), |
317 | ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), | |
318 | ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), | |
319 | ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), | |
320 | ||
321 | /* Op1 = 0, CRn = 0, CRm = 2 */ | |
322 | ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), | |
323 | ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), | |
324 | ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), | |
325 | ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), | |
326 | ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), | |
327 | ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), | |
328 | ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), | |
329 | ||
330 | /* Op1 = 0, CRn = 0, CRm = 3 */ | |
331 | ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), | |
332 | ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), | |
333 | ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), | |
334 | ||
335 | /* Op1 = 0, CRn = 0, CRm = 4 */ | |
336 | ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), | |
eab43e88 | 337 | ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz), |
3c739b57 SP |
338 | |
339 | /* Op1 = 0, CRn = 0, CRm = 5 */ | |
340 | ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), | |
eab43e88 | 341 | ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), |
3c739b57 SP |
342 | |
343 | /* Op1 = 0, CRn = 0, CRm = 6 */ | |
344 | ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), | |
c8c3798d | 345 | ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), |
3c739b57 SP |
346 | |
347 | /* Op1 = 0, CRn = 0, CRm = 7 */ | |
348 | ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), | |
349 | ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), | |
406e3087 | 350 | ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), |
3c739b57 SP |
351 | |
352 | /* Op1 = 3, CRn = 0, CRm = 0 */ | |
675b0563 | 353 | { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, |
3c739b57 SP |
354 | ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), |
355 | ||
356 | /* Op1 = 3, CRn = 14, CRm = 0 */ | |
eab43e88 | 357 | ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), |
3c739b57 SP |
358 | }; |
359 | ||
360 | static int search_cmp_ftr_reg(const void *id, const void *regp) | |
361 | { | |
6f2b7eef | 362 | return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; |
3c739b57 SP |
363 | } |
364 | ||
365 | /* | |
366 | * get_arm64_ftr_reg - Lookup a feature register entry using its | |
367 | * sys_reg() encoding. With the array arm64_ftr_regs sorted in the | |
368 | * ascending order of sys_id , we use binary search to find a matching | |
369 | * entry. | |
370 | * | |
371 | * returns - Upon success, matching ftr_reg entry for id. | |
372 | * - NULL on failure. It is upto the caller to decide | |
373 | * the impact of a failure. | |
374 | */ | |
375 | static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) | |
376 | { | |
6f2b7eef AB |
377 | const struct __ftr_reg_entry *ret; |
378 | ||
379 | ret = bsearch((const void *)(unsigned long)sys_id, | |
3c739b57 SP |
380 | arm64_ftr_regs, |
381 | ARRAY_SIZE(arm64_ftr_regs), | |
382 | sizeof(arm64_ftr_regs[0]), | |
383 | search_cmp_ftr_reg); | |
6f2b7eef AB |
384 | if (ret) |
385 | return ret->reg; | |
386 | return NULL; | |
3c739b57 SP |
387 | } |
388 | ||
5e49d73c AB |
389 | static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, |
390 | s64 ftr_val) | |
3c739b57 SP |
391 | { |
392 | u64 mask = arm64_ftr_mask(ftrp); | |
393 | ||
394 | reg &= ~mask; | |
395 | reg |= (ftr_val << ftrp->shift) & mask; | |
396 | return reg; | |
397 | } | |
398 | ||
5e49d73c AB |
399 | static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, |
400 | s64 cur) | |
3c739b57 SP |
401 | { |
402 | s64 ret = 0; | |
403 | ||
404 | switch (ftrp->type) { | |
405 | case FTR_EXACT: | |
406 | ret = ftrp->safe_val; | |
407 | break; | |
408 | case FTR_LOWER_SAFE: | |
409 | ret = new < cur ? new : cur; | |
410 | break; | |
411 | case FTR_HIGHER_SAFE: | |
412 | ret = new > cur ? new : cur; | |
413 | break; | |
414 | default: | |
415 | BUG(); | |
416 | } | |
417 | ||
418 | return ret; | |
419 | } | |
420 | ||
3c739b57 SP |
421 | static void __init sort_ftr_regs(void) |
422 | { | |
6f2b7eef AB |
423 | int i; |
424 | ||
425 | /* Check that the array is sorted so that we can do the binary search */ | |
426 | for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) | |
427 | BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); | |
3c739b57 SP |
428 | } |
429 | ||
430 | /* | |
431 | * Initialise the CPU feature register from Boot CPU values. | |
432 | * Also initiliases the strict_mask for the register. | |
b389d799 MR |
433 | * Any bits that are not covered by an arm64_ftr_bits entry are considered |
434 | * RES0 for the system-wide value, and must strictly match. | |
3c739b57 SP |
435 | */ |
436 | static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) | |
437 | { | |
438 | u64 val = 0; | |
439 | u64 strict_mask = ~0x0ULL; | |
fe4fbdbc | 440 | u64 user_mask = 0; |
b389d799 MR |
441 | u64 valid_mask = 0; |
442 | ||
5e49d73c | 443 | const struct arm64_ftr_bits *ftrp; |
3c739b57 SP |
444 | struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); |
445 | ||
446 | BUG_ON(!reg); | |
447 | ||
448 | for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { | |
b389d799 | 449 | u64 ftr_mask = arm64_ftr_mask(ftrp); |
3c739b57 SP |
450 | s64 ftr_new = arm64_ftr_value(ftrp, new); |
451 | ||
452 | val = arm64_ftr_set_value(ftrp, val, ftr_new); | |
b389d799 MR |
453 | |
454 | valid_mask |= ftr_mask; | |
3c739b57 | 455 | if (!ftrp->strict) |
b389d799 | 456 | strict_mask &= ~ftr_mask; |
fe4fbdbc SP |
457 | if (ftrp->visible) |
458 | user_mask |= ftr_mask; | |
459 | else | |
460 | reg->user_val = arm64_ftr_set_value(ftrp, | |
461 | reg->user_val, | |
462 | ftrp->safe_val); | |
3c739b57 | 463 | } |
b389d799 MR |
464 | |
465 | val &= valid_mask; | |
466 | ||
3c739b57 SP |
467 | reg->sys_val = val; |
468 | reg->strict_mask = strict_mask; | |
fe4fbdbc | 469 | reg->user_mask = user_mask; |
3c739b57 SP |
470 | } |
471 | ||
472 | void __init init_cpu_features(struct cpuinfo_arm64 *info) | |
473 | { | |
474 | /* Before we start using the tables, make sure it is sorted */ | |
475 | sort_ftr_regs(); | |
476 | ||
477 | init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); | |
478 | init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); | |
479 | init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); | |
480 | init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); | |
481 | init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); | |
482 | init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); | |
483 | init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); | |
484 | init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); | |
485 | init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); | |
406e3087 | 486 | init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); |
3c739b57 SP |
487 | init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); |
488 | init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); | |
a6dc3cd7 SP |
489 | |
490 | if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { | |
491 | init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); | |
492 | init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); | |
493 | init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); | |
494 | init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); | |
495 | init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); | |
496 | init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); | |
497 | init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); | |
498 | init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); | |
499 | init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); | |
500 | init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); | |
501 | init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); | |
502 | init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); | |
503 | init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); | |
504 | init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); | |
505 | init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); | |
506 | init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); | |
507 | } | |
508 | ||
3c739b57 SP |
509 | } |
510 | ||
3086d391 | 511 | static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) |
3c739b57 | 512 | { |
5e49d73c | 513 | const struct arm64_ftr_bits *ftrp; |
3c739b57 SP |
514 | |
515 | for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { | |
516 | s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); | |
517 | s64 ftr_new = arm64_ftr_value(ftrp, new); | |
518 | ||
519 | if (ftr_cur == ftr_new) | |
520 | continue; | |
521 | /* Find a safe value */ | |
522 | ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); | |
523 | reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); | |
524 | } | |
525 | ||
526 | } | |
527 | ||
3086d391 | 528 | static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) |
cdcf817b | 529 | { |
3086d391 SP |
530 | struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); |
531 | ||
532 | BUG_ON(!regp); | |
533 | update_cpu_ftr_reg(regp, val); | |
534 | if ((boot & regp->strict_mask) == (val & regp->strict_mask)) | |
535 | return 0; | |
536 | pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", | |
537 | regp->name, boot, cpu, val); | |
538 | return 1; | |
539 | } | |
540 | ||
541 | /* | |
542 | * Update system wide CPU feature registers with the values from a | |
543 | * non-boot CPU. Also performs SANITY checks to make sure that there | |
544 | * aren't any insane variations from that of the boot CPU. | |
545 | */ | |
546 | void update_cpu_features(int cpu, | |
547 | struct cpuinfo_arm64 *info, | |
548 | struct cpuinfo_arm64 *boot) | |
549 | { | |
550 | int taint = 0; | |
551 | ||
552 | /* | |
553 | * The kernel can handle differing I-cache policies, but otherwise | |
554 | * caches should look identical. Userspace JITs will make use of | |
555 | * *minLine. | |
556 | */ | |
557 | taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, | |
558 | info->reg_ctr, boot->reg_ctr); | |
559 | ||
560 | /* | |
561 | * Userspace may perform DC ZVA instructions. Mismatched block sizes | |
562 | * could result in too much or too little memory being zeroed if a | |
563 | * process is preempted and migrated between CPUs. | |
564 | */ | |
565 | taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, | |
566 | info->reg_dczid, boot->reg_dczid); | |
567 | ||
568 | /* If different, timekeeping will be broken (especially with KVM) */ | |
569 | taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, | |
570 | info->reg_cntfrq, boot->reg_cntfrq); | |
571 | ||
572 | /* | |
573 | * The kernel uses self-hosted debug features and expects CPUs to | |
574 | * support identical debug features. We presently need CTX_CMPs, WRPs, | |
575 | * and BRPs to be identical. | |
576 | * ID_AA64DFR1 is currently RES0. | |
577 | */ | |
578 | taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, | |
579 | info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); | |
580 | taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, | |
581 | info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); | |
582 | /* | |
583 | * Even in big.LITTLE, processors should be identical instruction-set | |
584 | * wise. | |
585 | */ | |
586 | taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, | |
587 | info->reg_id_aa64isar0, boot->reg_id_aa64isar0); | |
588 | taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, | |
589 | info->reg_id_aa64isar1, boot->reg_id_aa64isar1); | |
590 | ||
591 | /* | |
592 | * Differing PARange support is fine as long as all peripherals and | |
593 | * memory are mapped within the minimum PARange of all CPUs. | |
594 | * Linux should not care about secure memory. | |
595 | */ | |
596 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, | |
597 | info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); | |
598 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, | |
599 | info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); | |
406e3087 JM |
600 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, |
601 | info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); | |
3086d391 SP |
602 | |
603 | /* | |
604 | * EL3 is not our concern. | |
605 | * ID_AA64PFR1 is currently RES0. | |
606 | */ | |
607 | taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, | |
608 | info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); | |
609 | taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, | |
610 | info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); | |
611 | ||
612 | /* | |
a6dc3cd7 SP |
613 | * If we have AArch32, we care about 32-bit features for compat. |
614 | * If the system doesn't support AArch32, don't update them. | |
3086d391 | 615 | */ |
46823dd1 | 616 | if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && |
a6dc3cd7 SP |
617 | id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { |
618 | ||
619 | taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, | |
3086d391 | 620 | info->reg_id_dfr0, boot->reg_id_dfr0); |
a6dc3cd7 | 621 | taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, |
3086d391 | 622 | info->reg_id_isar0, boot->reg_id_isar0); |
a6dc3cd7 | 623 | taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, |
3086d391 | 624 | info->reg_id_isar1, boot->reg_id_isar1); |
a6dc3cd7 | 625 | taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, |
3086d391 | 626 | info->reg_id_isar2, boot->reg_id_isar2); |
a6dc3cd7 | 627 | taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, |
3086d391 | 628 | info->reg_id_isar3, boot->reg_id_isar3); |
a6dc3cd7 | 629 | taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, |
3086d391 | 630 | info->reg_id_isar4, boot->reg_id_isar4); |
a6dc3cd7 | 631 | taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, |
3086d391 SP |
632 | info->reg_id_isar5, boot->reg_id_isar5); |
633 | ||
a6dc3cd7 SP |
634 | /* |
635 | * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and | |
636 | * ACTLR formats could differ across CPUs and therefore would have to | |
637 | * be trapped for virtualization anyway. | |
638 | */ | |
639 | taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, | |
3086d391 | 640 | info->reg_id_mmfr0, boot->reg_id_mmfr0); |
a6dc3cd7 | 641 | taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, |
3086d391 | 642 | info->reg_id_mmfr1, boot->reg_id_mmfr1); |
a6dc3cd7 | 643 | taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, |
3086d391 | 644 | info->reg_id_mmfr2, boot->reg_id_mmfr2); |
a6dc3cd7 | 645 | taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, |
3086d391 | 646 | info->reg_id_mmfr3, boot->reg_id_mmfr3); |
a6dc3cd7 | 647 | taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, |
3086d391 | 648 | info->reg_id_pfr0, boot->reg_id_pfr0); |
a6dc3cd7 | 649 | taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, |
3086d391 | 650 | info->reg_id_pfr1, boot->reg_id_pfr1); |
a6dc3cd7 | 651 | taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, |
3086d391 | 652 | info->reg_mvfr0, boot->reg_mvfr0); |
a6dc3cd7 | 653 | taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, |
3086d391 | 654 | info->reg_mvfr1, boot->reg_mvfr1); |
a6dc3cd7 | 655 | taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, |
3086d391 | 656 | info->reg_mvfr2, boot->reg_mvfr2); |
a6dc3cd7 | 657 | } |
3086d391 SP |
658 | |
659 | /* | |
660 | * Mismatched CPU features are a recipe for disaster. Don't even | |
661 | * pretend to support them. | |
662 | */ | |
8dd0ee65 WD |
663 | if (taint) { |
664 | pr_warn_once("Unsupported CPU feature variation detected.\n"); | |
665 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); | |
666 | } | |
cdcf817b SP |
667 | } |
668 | ||
46823dd1 | 669 | u64 read_sanitised_ftr_reg(u32 id) |
b3f15378 SP |
670 | { |
671 | struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); | |
672 | ||
673 | /* We shouldn't get a request for an unsupported register */ | |
674 | BUG_ON(!regp); | |
675 | return regp->sys_val; | |
676 | } | |
359b7064 | 677 | |
965861d6 MR |
678 | #define read_sysreg_case(r) \ |
679 | case r: return read_sysreg_s(r) | |
680 | ||
92406f0c | 681 | /* |
46823dd1 | 682 | * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. |
92406f0c SP |
683 | * Read the system register on the current CPU |
684 | */ | |
46823dd1 | 685 | static u64 __read_sysreg_by_encoding(u32 sys_id) |
92406f0c SP |
686 | { |
687 | switch (sys_id) { | |
965861d6 MR |
688 | read_sysreg_case(SYS_ID_PFR0_EL1); |
689 | read_sysreg_case(SYS_ID_PFR1_EL1); | |
690 | read_sysreg_case(SYS_ID_DFR0_EL1); | |
691 | read_sysreg_case(SYS_ID_MMFR0_EL1); | |
692 | read_sysreg_case(SYS_ID_MMFR1_EL1); | |
693 | read_sysreg_case(SYS_ID_MMFR2_EL1); | |
694 | read_sysreg_case(SYS_ID_MMFR3_EL1); | |
695 | read_sysreg_case(SYS_ID_ISAR0_EL1); | |
696 | read_sysreg_case(SYS_ID_ISAR1_EL1); | |
697 | read_sysreg_case(SYS_ID_ISAR2_EL1); | |
698 | read_sysreg_case(SYS_ID_ISAR3_EL1); | |
699 | read_sysreg_case(SYS_ID_ISAR4_EL1); | |
700 | read_sysreg_case(SYS_ID_ISAR5_EL1); | |
701 | read_sysreg_case(SYS_MVFR0_EL1); | |
702 | read_sysreg_case(SYS_MVFR1_EL1); | |
703 | read_sysreg_case(SYS_MVFR2_EL1); | |
704 | ||
705 | read_sysreg_case(SYS_ID_AA64PFR0_EL1); | |
706 | read_sysreg_case(SYS_ID_AA64PFR1_EL1); | |
707 | read_sysreg_case(SYS_ID_AA64DFR0_EL1); | |
708 | read_sysreg_case(SYS_ID_AA64DFR1_EL1); | |
709 | read_sysreg_case(SYS_ID_AA64MMFR0_EL1); | |
710 | read_sysreg_case(SYS_ID_AA64MMFR1_EL1); | |
711 | read_sysreg_case(SYS_ID_AA64MMFR2_EL1); | |
712 | read_sysreg_case(SYS_ID_AA64ISAR0_EL1); | |
713 | read_sysreg_case(SYS_ID_AA64ISAR1_EL1); | |
714 | ||
715 | read_sysreg_case(SYS_CNTFRQ_EL0); | |
716 | read_sysreg_case(SYS_CTR_EL0); | |
717 | read_sysreg_case(SYS_DCZID_EL0); | |
718 | ||
92406f0c SP |
719 | default: |
720 | BUG(); | |
721 | return 0; | |
722 | } | |
723 | } | |
724 | ||
963fcd40 MZ |
725 | #include <linux/irqchip/arm-gic-v3.h> |
726 | ||
18ffa046 JM |
727 | static bool |
728 | feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) | |
729 | { | |
28c5dcb2 | 730 | int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); |
18ffa046 JM |
731 | |
732 | return val >= entry->min_field_value; | |
733 | } | |
734 | ||
da8d02d1 | 735 | static bool |
92406f0c | 736 | has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) |
da8d02d1 SP |
737 | { |
738 | u64 val; | |
94a9e04a | 739 | |
92406f0c SP |
740 | WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); |
741 | if (scope == SCOPE_SYSTEM) | |
46823dd1 | 742 | val = read_sanitised_ftr_reg(entry->sys_reg); |
92406f0c | 743 | else |
46823dd1 | 744 | val = __read_sysreg_by_encoding(entry->sys_reg); |
92406f0c | 745 | |
da8d02d1 SP |
746 | return feature_matches(val, entry); |
747 | } | |
338d4f49 | 748 | |
92406f0c | 749 | static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) |
963fcd40 MZ |
750 | { |
751 | bool has_sre; | |
752 | ||
92406f0c | 753 | if (!has_cpuid_feature(entry, scope)) |
963fcd40 MZ |
754 | return false; |
755 | ||
756 | has_sre = gic_enable_sre(); | |
757 | if (!has_sre) | |
758 | pr_warn_once("%s present but disabled by higher exception level\n", | |
759 | entry->desc); | |
760 | ||
761 | return has_sre; | |
762 | } | |
763 | ||
92406f0c | 764 | static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) |
d5370f75 WD |
765 | { |
766 | u32 midr = read_cpuid_id(); | |
d5370f75 WD |
767 | |
768 | /* Cavium ThunderX pass 1.x and 2.x */ | |
fa5ce3d1 RR |
769 | return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, |
770 | MIDR_CPU_VAR_REV(0, 0), | |
771 | MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); | |
d5370f75 WD |
772 | } |
773 | ||
92406f0c | 774 | static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) |
d88701be MZ |
775 | { |
776 | return is_kernel_in_hyp_mode(); | |
777 | } | |
778 | ||
d1745910 MZ |
779 | static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry, |
780 | int __unused) | |
781 | { | |
2077be67 | 782 | phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start); |
d1745910 MZ |
783 | |
784 | /* | |
785 | * Activate the lower HYP offset only if: | |
786 | * - the idmap doesn't clash with it, | |
787 | * - the kernel is not running at EL2. | |
788 | */ | |
789 | return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode(); | |
790 | } | |
791 | ||
82e0191a SP |
792 | static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) |
793 | { | |
46823dd1 | 794 | u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); |
82e0191a SP |
795 | |
796 | return cpuid_feature_extract_signed_field(pfr0, | |
797 | ID_AA64PFR0_FP_SHIFT) < 0; | |
798 | } | |
799 | ||
95ba85b5 WD |
800 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
801 | static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ | |
802 | ||
803 | static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, | |
804 | int __unused) | |
805 | { | |
82a66aec | 806 | char const *str = "command line option"; |
78b89248 WD |
807 | u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); |
808 | ||
82a66aec MZ |
809 | /* |
810 | * For reasons that aren't entirely clear, enabling KPTI on Cavium | |
811 | * ThunderX leads to apparent I-cache corruption of kernel text, which | |
812 | * ends as well as you might imagine. Don't even try. | |
813 | */ | |
814 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { | |
815 | str = "ARM64_WORKAROUND_CAVIUM_27456"; | |
816 | __kpti_forced = -1; | |
817 | } | |
818 | ||
819 | /* Forced? */ | |
95ba85b5 | 820 | if (__kpti_forced) { |
82a66aec MZ |
821 | pr_info_once("kernel page table isolation forced %s by %s\n", |
822 | __kpti_forced > 0 ? "ON" : "OFF", str); | |
95ba85b5 WD |
823 | return __kpti_forced > 0; |
824 | } | |
825 | ||
826 | /* Useful for KASLR robustness */ | |
827 | if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) | |
828 | return true; | |
829 | ||
080cc3c2 J |
830 | /* Don't force KPTI for CPUs that are not vulnerable */ |
831 | switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) { | |
832 | case MIDR_CAVIUM_THUNDERX2: | |
833 | case MIDR_BRCM_VULCAN: | |
834 | return false; | |
835 | } | |
836 | ||
78b89248 WD |
837 | /* Defer to CPU feature registers */ |
838 | return !cpuid_feature_extract_unsigned_field(pfr0, | |
839 | ID_AA64PFR0_CSV3_SHIFT); | |
95ba85b5 WD |
840 | } |
841 | ||
9d82de84 WD |
842 | static int kpti_install_ng_mappings(void *__unused) |
843 | { | |
844 | typedef void (kpti_remap_fn)(int, int, phys_addr_t); | |
845 | extern kpti_remap_fn idmap_kpti_install_ng_mappings; | |
846 | kpti_remap_fn *remap_fn; | |
847 | ||
848 | static bool kpti_applied = false; | |
849 | int cpu = smp_processor_id(); | |
850 | ||
851 | if (kpti_applied) | |
852 | return 0; | |
853 | ||
854 | remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); | |
855 | ||
856 | cpu_install_idmap(); | |
857 | remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); | |
858 | cpu_uninstall_idmap(); | |
859 | ||
860 | if (!cpu) | |
861 | kpti_applied = true; | |
862 | ||
863 | return 0; | |
864 | } | |
865 | ||
95ba85b5 WD |
866 | static int __init parse_kpti(char *str) |
867 | { | |
868 | bool enabled; | |
869 | int ret = strtobool(str, &enabled); | |
870 | ||
871 | if (ret) | |
872 | return ret; | |
873 | ||
874 | __kpti_forced = enabled ? 1 : -1; | |
875 | return 0; | |
876 | } | |
877 | __setup("kpti=", parse_kpti); | |
878 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ | |
879 | ||
359b7064 | 880 | static const struct arm64_cpu_capabilities arm64_features[] = { |
94a9e04a MZ |
881 | { |
882 | .desc = "GIC system register CPU interface", | |
883 | .capability = ARM64_HAS_SYSREG_GIC_CPUIF, | |
92406f0c | 884 | .def_scope = SCOPE_SYSTEM, |
963fcd40 | 885 | .matches = has_useable_gicv3_cpuif, |
da8d02d1 SP |
886 | .sys_reg = SYS_ID_AA64PFR0_EL1, |
887 | .field_pos = ID_AA64PFR0_GIC_SHIFT, | |
ff96f7bc | 888 | .sign = FTR_UNSIGNED, |
18ffa046 | 889 | .min_field_value = 1, |
94a9e04a | 890 | }, |
338d4f49 JM |
891 | #ifdef CONFIG_ARM64_PAN |
892 | { | |
893 | .desc = "Privileged Access Never", | |
894 | .capability = ARM64_HAS_PAN, | |
92406f0c | 895 | .def_scope = SCOPE_SYSTEM, |
da8d02d1 SP |
896 | .matches = has_cpuid_feature, |
897 | .sys_reg = SYS_ID_AA64MMFR1_EL1, | |
898 | .field_pos = ID_AA64MMFR1_PAN_SHIFT, | |
ff96f7bc | 899 | .sign = FTR_UNSIGNED, |
338d4f49 JM |
900 | .min_field_value = 1, |
901 | .enable = cpu_enable_pan, | |
902 | }, | |
903 | #endif /* CONFIG_ARM64_PAN */ | |
2e94da13 WD |
904 | #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) |
905 | { | |
906 | .desc = "LSE atomic instructions", | |
907 | .capability = ARM64_HAS_LSE_ATOMICS, | |
92406f0c | 908 | .def_scope = SCOPE_SYSTEM, |
da8d02d1 SP |
909 | .matches = has_cpuid_feature, |
910 | .sys_reg = SYS_ID_AA64ISAR0_EL1, | |
911 | .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, | |
ff96f7bc | 912 | .sign = FTR_UNSIGNED, |
2e94da13 WD |
913 | .min_field_value = 2, |
914 | }, | |
915 | #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ | |
d5370f75 WD |
916 | { |
917 | .desc = "Software prefetching using PRFM", | |
918 | .capability = ARM64_HAS_NO_HW_PREFETCH, | |
92406f0c | 919 | .def_scope = SCOPE_SYSTEM, |
d5370f75 WD |
920 | .matches = has_no_hw_prefetch, |
921 | }, | |
57f4959b JM |
922 | #ifdef CONFIG_ARM64_UAO |
923 | { | |
924 | .desc = "User Access Override", | |
925 | .capability = ARM64_HAS_UAO, | |
92406f0c | 926 | .def_scope = SCOPE_SYSTEM, |
57f4959b JM |
927 | .matches = has_cpuid_feature, |
928 | .sys_reg = SYS_ID_AA64MMFR2_EL1, | |
929 | .field_pos = ID_AA64MMFR2_UAO_SHIFT, | |
930 | .min_field_value = 1, | |
c8b06e3f JM |
931 | /* |
932 | * We rely on stop_machine() calling uao_thread_switch() to set | |
933 | * UAO immediately after patching. | |
934 | */ | |
57f4959b JM |
935 | }, |
936 | #endif /* CONFIG_ARM64_UAO */ | |
70544196 JM |
937 | #ifdef CONFIG_ARM64_PAN |
938 | { | |
939 | .capability = ARM64_ALT_PAN_NOT_UAO, | |
92406f0c | 940 | .def_scope = SCOPE_SYSTEM, |
70544196 JM |
941 | .matches = cpufeature_pan_not_uao, |
942 | }, | |
943 | #endif /* CONFIG_ARM64_PAN */ | |
d88701be MZ |
944 | { |
945 | .desc = "Virtualization Host Extensions", | |
946 | .capability = ARM64_HAS_VIRT_HOST_EXTN, | |
92406f0c | 947 | .def_scope = SCOPE_SYSTEM, |
d88701be MZ |
948 | .matches = runs_at_el2, |
949 | }, | |
042446a3 SP |
950 | { |
951 | .desc = "32-bit EL0 Support", | |
952 | .capability = ARM64_HAS_32BIT_EL0, | |
92406f0c | 953 | .def_scope = SCOPE_SYSTEM, |
042446a3 SP |
954 | .matches = has_cpuid_feature, |
955 | .sys_reg = SYS_ID_AA64PFR0_EL1, | |
956 | .sign = FTR_UNSIGNED, | |
957 | .field_pos = ID_AA64PFR0_EL0_SHIFT, | |
958 | .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, | |
959 | }, | |
d1745910 MZ |
960 | { |
961 | .desc = "Reduced HYP mapping offset", | |
962 | .capability = ARM64_HYP_OFFSET_LOW, | |
963 | .def_scope = SCOPE_SYSTEM, | |
964 | .matches = hyp_offset_low, | |
965 | }, | |
95ba85b5 WD |
966 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
967 | { | |
78b89248 | 968 | .desc = "Kernel page table isolation (KPTI)", |
95ba85b5 WD |
969 | .capability = ARM64_UNMAP_KERNEL_AT_EL0, |
970 | .def_scope = SCOPE_SYSTEM, | |
971 | .matches = unmap_kernel_at_el0, | |
9d82de84 | 972 | .enable = kpti_install_ng_mappings, |
95ba85b5 WD |
973 | }, |
974 | #endif | |
82e0191a SP |
975 | { |
976 | /* FP/SIMD is not implemented */ | |
977 | .capability = ARM64_HAS_NO_FPSIMD, | |
978 | .def_scope = SCOPE_SYSTEM, | |
979 | .min_field_value = 0, | |
980 | .matches = has_no_fpsimd, | |
981 | }, | |
27119a3a RM |
982 | #ifdef CONFIG_ARM64_PMEM |
983 | { | |
984 | .desc = "Data cache clean to Point of Persistence", | |
985 | .capability = ARM64_HAS_DCPOP, | |
986 | .def_scope = SCOPE_SYSTEM, | |
987 | .matches = has_cpuid_feature, | |
988 | .sys_reg = SYS_ID_AA64ISAR1_EL1, | |
989 | .field_pos = ID_AA64ISAR1_DPB_SHIFT, | |
990 | .min_field_value = 1, | |
991 | }, | |
992 | #endif | |
359b7064 MZ |
993 | {}, |
994 | }; | |
995 | ||
ff96f7bc | 996 | #define HWCAP_CAP(reg, field, s, min_value, type, cap) \ |
37b01d53 SP |
997 | { \ |
998 | .desc = #cap, \ | |
92406f0c | 999 | .def_scope = SCOPE_SYSTEM, \ |
37b01d53 SP |
1000 | .matches = has_cpuid_feature, \ |
1001 | .sys_reg = reg, \ | |
1002 | .field_pos = field, \ | |
ff96f7bc | 1003 | .sign = s, \ |
37b01d53 SP |
1004 | .min_field_value = min_value, \ |
1005 | .hwcap_type = type, \ | |
1006 | .hwcap = cap, \ | |
1007 | } | |
1008 | ||
f3efb675 | 1009 | static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { |
ff96f7bc SP |
1010 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), |
1011 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), | |
1012 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), | |
1013 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), | |
1014 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), | |
1015 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), | |
f92f5ce0 | 1016 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), |
ff96f7bc | 1017 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), |
bf500618 | 1018 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), |
ff96f7bc | 1019 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), |
bf500618 | 1020 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), |
8795ded3 | 1021 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP), |
c8c3798d | 1022 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), |
cb567e79 | 1023 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), |
c651aae5 | 1024 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), |
75283501 SP |
1025 | {}, |
1026 | }; | |
1027 | ||
1028 | static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { | |
37b01d53 | 1029 | #ifdef CONFIG_COMPAT |
ff96f7bc SP |
1030 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), |
1031 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), | |
1032 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), | |
1033 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), | |
1034 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), | |
37b01d53 SP |
1035 | #endif |
1036 | {}, | |
1037 | }; | |
1038 | ||
f3efb675 | 1039 | static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) |
37b01d53 SP |
1040 | { |
1041 | switch (cap->hwcap_type) { | |
1042 | case CAP_HWCAP: | |
1043 | elf_hwcap |= cap->hwcap; | |
1044 | break; | |
1045 | #ifdef CONFIG_COMPAT | |
1046 | case CAP_COMPAT_HWCAP: | |
1047 | compat_elf_hwcap |= (u32)cap->hwcap; | |
1048 | break; | |
1049 | case CAP_COMPAT_HWCAP2: | |
1050 | compat_elf_hwcap2 |= (u32)cap->hwcap; | |
1051 | break; | |
1052 | #endif | |
1053 | default: | |
1054 | WARN_ON(1); | |
1055 | break; | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | /* Check if we have a particular HWCAP enabled */ | |
f3efb675 | 1060 | static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) |
37b01d53 SP |
1061 | { |
1062 | bool rc; | |
1063 | ||
1064 | switch (cap->hwcap_type) { | |
1065 | case CAP_HWCAP: | |
1066 | rc = (elf_hwcap & cap->hwcap) != 0; | |
1067 | break; | |
1068 | #ifdef CONFIG_COMPAT | |
1069 | case CAP_COMPAT_HWCAP: | |
1070 | rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; | |
1071 | break; | |
1072 | case CAP_COMPAT_HWCAP2: | |
1073 | rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; | |
1074 | break; | |
1075 | #endif | |
1076 | default: | |
1077 | WARN_ON(1); | |
1078 | rc = false; | |
1079 | } | |
1080 | ||
1081 | return rc; | |
1082 | } | |
1083 | ||
75283501 | 1084 | static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) |
37b01d53 | 1085 | { |
77c97b4e SP |
1086 | /* We support emulation of accesses to CPU ID feature registers */ |
1087 | elf_hwcap |= HWCAP_CPUID; | |
75283501 | 1088 | for (; hwcaps->matches; hwcaps++) |
92406f0c | 1089 | if (hwcaps->matches(hwcaps, hwcaps->def_scope)) |
75283501 | 1090 | cap_set_elf_hwcap(hwcaps); |
37b01d53 SP |
1091 | } |
1092 | ||
cda58dc4 SP |
1093 | /* |
1094 | * Check if the current CPU has a given feature capability. | |
1095 | * Should be called from non-preemptible context. | |
1096 | */ | |
1097 | static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array, | |
1098 | unsigned int cap) | |
1099 | { | |
1100 | const struct arm64_cpu_capabilities *caps; | |
1101 | ||
1102 | if (WARN_ON(preemptible())) | |
1103 | return false; | |
1104 | ||
516c124c | 1105 | for (caps = cap_array; caps->matches; caps++) |
cda58dc4 | 1106 | if (caps->capability == cap && |
cda58dc4 SP |
1107 | caps->matches(caps, SCOPE_LOCAL_CPU)) |
1108 | return true; | |
1109 | return false; | |
1110 | } | |
1111 | ||
ce8b602c | 1112 | void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, |
359b7064 MZ |
1113 | const char *info) |
1114 | { | |
75283501 | 1115 | for (; caps->matches; caps++) { |
92406f0c | 1116 | if (!caps->matches(caps, caps->def_scope)) |
359b7064 MZ |
1117 | continue; |
1118 | ||
75283501 SP |
1119 | if (!cpus_have_cap(caps->capability) && caps->desc) |
1120 | pr_info("%s %s\n", info, caps->desc); | |
1121 | cpus_set_cap(caps->capability); | |
359b7064 | 1122 | } |
ce8b602c SP |
1123 | } |
1124 | ||
1125 | /* | |
dbb4e152 SP |
1126 | * Run through the enabled capabilities and enable() it on all active |
1127 | * CPUs | |
ce8b602c | 1128 | */ |
8e231852 | 1129 | void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) |
ce8b602c | 1130 | { |
63a1e1c9 MR |
1131 | for (; caps->matches; caps++) { |
1132 | unsigned int num = caps->capability; | |
1133 | ||
1134 | if (!cpus_have_cap(num)) | |
1135 | continue; | |
1136 | ||
1137 | /* Ensure cpus_have_const_cap(num) works */ | |
1138 | static_branch_enable(&cpu_hwcap_keys[num]); | |
1139 | ||
1140 | if (caps->enable) { | |
2a6dcb2b JM |
1141 | /* |
1142 | * Use stop_machine() as it schedules the work allowing | |
1143 | * us to modify PSTATE, instead of on_each_cpu() which | |
1144 | * uses an IPI, giving us a PSTATE that disappears when | |
1145 | * we return. | |
1146 | */ | |
1147 | stop_machine(caps->enable, NULL, cpu_online_mask); | |
63a1e1c9 MR |
1148 | } |
1149 | } | |
dbb4e152 SP |
1150 | } |
1151 | ||
dbb4e152 SP |
1152 | /* |
1153 | * Flag to indicate if we have computed the system wide | |
1154 | * capabilities based on the boot time active CPUs. This | |
1155 | * will be used to determine if a new booting CPU should | |
1156 | * go through the verification process to make sure that it | |
1157 | * supports the system capabilities, without using a hotplug | |
1158 | * notifier. | |
1159 | */ | |
1160 | static bool sys_caps_initialised; | |
1161 | ||
1162 | static inline void set_sys_caps_initialised(void) | |
1163 | { | |
1164 | sys_caps_initialised = true; | |
1165 | } | |
1166 | ||
1167 | /* | |
13f417f3 SP |
1168 | * Check for CPU features that are used in early boot |
1169 | * based on the Boot CPU value. | |
dbb4e152 | 1170 | */ |
13f417f3 | 1171 | static void check_early_cpu_features(void) |
dbb4e152 | 1172 | { |
ac1ad20f | 1173 | verify_cpu_run_el(); |
13f417f3 | 1174 | verify_cpu_asid_bits(); |
dbb4e152 | 1175 | } |
1c076303 | 1176 | |
75283501 SP |
1177 | static void |
1178 | verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) | |
1179 | { | |
1180 | ||
92406f0c SP |
1181 | for (; caps->matches; caps++) |
1182 | if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { | |
75283501 SP |
1183 | pr_crit("CPU%d: missing HWCAP: %s\n", |
1184 | smp_processor_id(), caps->desc); | |
1185 | cpu_die_early(); | |
1186 | } | |
75283501 SP |
1187 | } |
1188 | ||
1189 | static void | |
cda58dc4 | 1190 | verify_local_cpu_features(const struct arm64_cpu_capabilities *caps_list) |
75283501 | 1191 | { |
cda58dc4 | 1192 | const struct arm64_cpu_capabilities *caps = caps_list; |
75283501 | 1193 | for (; caps->matches; caps++) { |
92406f0c | 1194 | if (!cpus_have_cap(caps->capability)) |
75283501 SP |
1195 | continue; |
1196 | /* | |
1197 | * If the new CPU misses an advertised feature, we cannot proceed | |
1198 | * further, park the cpu. | |
1199 | */ | |
cda58dc4 | 1200 | if (!__this_cpu_has_cap(caps_list, caps->capability)) { |
75283501 SP |
1201 | pr_crit("CPU%d: missing feature: %s\n", |
1202 | smp_processor_id(), caps->desc); | |
1203 | cpu_die_early(); | |
1204 | } | |
1205 | if (caps->enable) | |
1206 | caps->enable(NULL); | |
1207 | } | |
1208 | } | |
1209 | ||
dbb4e152 SP |
1210 | /* |
1211 | * Run through the enabled system capabilities and enable() it on this CPU. | |
1212 | * The capabilities were decided based on the available CPUs at the boot time. | |
1213 | * Any new CPU should match the system wide status of the capability. If the | |
1214 | * new CPU doesn't have a capability which the system now has enabled, we | |
1215 | * cannot do anything to fix it up and could cause unexpected failures. So | |
1216 | * we park the CPU. | |
1217 | */ | |
c47a1900 | 1218 | static void verify_local_cpu_capabilities(void) |
dbb4e152 | 1219 | { |
c47a1900 SP |
1220 | verify_local_cpu_errata_workarounds(); |
1221 | verify_local_cpu_features(arm64_features); | |
1222 | verify_local_elf_hwcaps(arm64_elf_hwcaps); | |
1223 | if (system_supports_32bit_el0()) | |
1224 | verify_local_elf_hwcaps(compat_elf_hwcaps); | |
1225 | } | |
dbb4e152 | 1226 | |
c47a1900 SP |
1227 | void check_local_cpu_capabilities(void) |
1228 | { | |
1229 | /* | |
1230 | * All secondary CPUs should conform to the early CPU features | |
1231 | * in use by the kernel based on boot CPU. | |
1232 | */ | |
13f417f3 SP |
1233 | check_early_cpu_features(); |
1234 | ||
dbb4e152 | 1235 | /* |
c47a1900 SP |
1236 | * If we haven't finalised the system capabilities, this CPU gets |
1237 | * a chance to update the errata work arounds. | |
1238 | * Otherwise, this CPU should verify that it has all the system | |
1239 | * advertised capabilities. | |
dbb4e152 SP |
1240 | */ |
1241 | if (!sys_caps_initialised) | |
c47a1900 SP |
1242 | update_cpu_errata_workarounds(); |
1243 | else | |
1244 | verify_local_cpu_capabilities(); | |
359b7064 MZ |
1245 | } |
1246 | ||
a7c61a34 | 1247 | static void __init setup_feature_capabilities(void) |
359b7064 | 1248 | { |
ce8b602c SP |
1249 | update_cpu_capabilities(arm64_features, "detected feature:"); |
1250 | enable_cpu_capabilities(arm64_features); | |
359b7064 MZ |
1251 | } |
1252 | ||
63a1e1c9 MR |
1253 | DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); |
1254 | EXPORT_SYMBOL(arm64_const_caps_ready); | |
1255 | ||
1256 | static void __init mark_const_caps_ready(void) | |
1257 | { | |
1258 | static_branch_enable(&arm64_const_caps_ready); | |
1259 | } | |
1260 | ||
8f413758 MZ |
1261 | extern const struct arm64_cpu_capabilities arm64_errata[]; |
1262 | ||
1263 | bool this_cpu_has_cap(unsigned int cap) | |
1264 | { | |
1265 | return (__this_cpu_has_cap(arm64_features, cap) || | |
1266 | __this_cpu_has_cap(arm64_errata, cap)); | |
1267 | } | |
1268 | ||
9cdf8ec4 | 1269 | void __init setup_cpu_features(void) |
359b7064 | 1270 | { |
9cdf8ec4 SP |
1271 | u32 cwg; |
1272 | int cls; | |
1273 | ||
dbb4e152 SP |
1274 | /* Set the CPU feature capabilies */ |
1275 | setup_feature_capabilities(); | |
8e231852 | 1276 | enable_errata_workarounds(); |
63a1e1c9 | 1277 | mark_const_caps_ready(); |
75283501 | 1278 | setup_elf_hwcaps(arm64_elf_hwcaps); |
643d703d SP |
1279 | |
1280 | if (system_supports_32bit_el0()) | |
1281 | setup_elf_hwcaps(compat_elf_hwcaps); | |
dbb4e152 SP |
1282 | |
1283 | /* Advertise that we have computed the system capabilities */ | |
1284 | set_sys_caps_initialised(); | |
1285 | ||
9cdf8ec4 SP |
1286 | /* |
1287 | * Check for sane CTR_EL0.CWG value. | |
1288 | */ | |
1289 | cwg = cache_type_cwg(); | |
1290 | cls = cache_line_size(); | |
1291 | if (!cwg) | |
1292 | pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", | |
1293 | cls); | |
1294 | if (L1_CACHE_BYTES < cls) | |
1295 | pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", | |
1296 | L1_CACHE_BYTES, cls); | |
359b7064 | 1297 | } |
70544196 JM |
1298 | |
1299 | static bool __maybe_unused | |
92406f0c | 1300 | cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) |
70544196 | 1301 | { |
a4023f68 | 1302 | return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); |
70544196 | 1303 | } |
77c97b4e SP |
1304 | |
1305 | /* | |
1306 | * We emulate only the following system register space. | |
1307 | * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] | |
1308 | * See Table C5-6 System instruction encodings for System register accesses, | |
1309 | * ARMv8 ARM(ARM DDI 0487A.f) for more details. | |
1310 | */ | |
1311 | static inline bool __attribute_const__ is_emulated(u32 id) | |
1312 | { | |
1313 | return (sys_reg_Op0(id) == 0x3 && | |
1314 | sys_reg_CRn(id) == 0x0 && | |
1315 | sys_reg_Op1(id) == 0x0 && | |
1316 | (sys_reg_CRm(id) == 0 || | |
1317 | ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); | |
1318 | } | |
1319 | ||
1320 | /* | |
1321 | * With CRm == 0, reg should be one of : | |
1322 | * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. | |
1323 | */ | |
1324 | static inline int emulate_id_reg(u32 id, u64 *valp) | |
1325 | { | |
1326 | switch (id) { | |
1327 | case SYS_MIDR_EL1: | |
1328 | *valp = read_cpuid_id(); | |
1329 | break; | |
1330 | case SYS_MPIDR_EL1: | |
1331 | *valp = SYS_MPIDR_SAFE_VAL; | |
1332 | break; | |
1333 | case SYS_REVIDR_EL1: | |
1334 | /* IMPLEMENTATION DEFINED values are emulated with 0 */ | |
1335 | *valp = 0; | |
1336 | break; | |
1337 | default: | |
1338 | return -EINVAL; | |
1339 | } | |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | static int emulate_sys_reg(u32 id, u64 *valp) | |
1345 | { | |
1346 | struct arm64_ftr_reg *regp; | |
1347 | ||
1348 | if (!is_emulated(id)) | |
1349 | return -EINVAL; | |
1350 | ||
1351 | if (sys_reg_CRm(id) == 0) | |
1352 | return emulate_id_reg(id, valp); | |
1353 | ||
1354 | regp = get_arm64_ftr_reg(id); | |
1355 | if (regp) | |
1356 | *valp = arm64_ftr_reg_user_value(regp); | |
1357 | else | |
1358 | /* | |
1359 | * The untracked registers are either IMPLEMENTATION DEFINED | |
1360 | * (e.g, ID_AFR0_EL1) or reserved RAZ. | |
1361 | */ | |
1362 | *valp = 0; | |
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | static int emulate_mrs(struct pt_regs *regs, u32 insn) | |
1367 | { | |
1368 | int rc; | |
1369 | u32 sys_reg, dst; | |
1370 | u64 val; | |
1371 | ||
1372 | /* | |
1373 | * sys_reg values are defined as used in mrs/msr instruction. | |
1374 | * shift the imm value to get the encoding. | |
1375 | */ | |
1376 | sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; | |
1377 | rc = emulate_sys_reg(sys_reg, &val); | |
1378 | if (!rc) { | |
1379 | dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); | |
521c6461 | 1380 | pt_regs_write_reg(regs, dst, val); |
77c97b4e SP |
1381 | regs->pc += 4; |
1382 | } | |
1383 | ||
1384 | return rc; | |
1385 | } | |
1386 | ||
1387 | static struct undef_hook mrs_hook = { | |
1388 | .instr_mask = 0xfff00000, | |
1389 | .instr_val = 0xd5300000, | |
1390 | .pstate_mask = COMPAT_PSR_MODE_MASK, | |
1391 | .pstate_val = PSR_MODE_EL0t, | |
1392 | .fn = emulate_mrs, | |
1393 | }; | |
1394 | ||
1395 | static int __init enable_mrs_emulation(void) | |
1396 | { | |
1397 | register_undef_hook(&mrs_hook); | |
1398 | return 0; | |
1399 | } | |
1400 | ||
ce1c3575 | 1401 | core_initcall(enable_mrs_emulation); |