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60ffc30d CM |
1 | /* |
2 | * Low-level exception handling code | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * Will Deacon <will.deacon@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | ||
8d883b23 | 24 | #include <asm/alternative.h> |
60ffc30d CM |
25 | #include <asm/assembler.h> |
26 | #include <asm/asm-offsets.h> | |
905e8c5d | 27 | #include <asm/cpufeature.h> |
60ffc30d | 28 | #include <asm/errno.h> |
5c1ce6f7 | 29 | #include <asm/esr.h> |
8e23dacd | 30 | #include <asm/irq.h> |
95a2833d WD |
31 | #include <asm/memory.h> |
32 | #include <asm/mmu.h> | |
9694c889 | 33 | #include <asm/processor.h> |
39bc88e5 | 34 | #include <asm/ptrace.h> |
60ffc30d | 35 | #include <asm/thread_info.h> |
b4b8664d | 36 | #include <asm/asm-uaccess.h> |
60ffc30d CM |
37 | #include <asm/unistd.h> |
38 | ||
6c81fe79 LB |
39 | /* |
40 | * Context tracking subsystem. Used to instrument transitions | |
41 | * between user and kernel mode. | |
42 | */ | |
43 | .macro ct_user_exit, syscall = 0 | |
44 | #ifdef CONFIG_CONTEXT_TRACKING | |
45 | bl context_tracking_user_exit | |
46 | .if \syscall == 1 | |
47 | /* | |
48 | * Save/restore needed during syscalls. Restore syscall arguments from | |
49 | * the values already saved on stack during kernel_entry. | |
50 | */ | |
51 | ldp x0, x1, [sp] | |
52 | ldp x2, x3, [sp, #S_X2] | |
53 | ldp x4, x5, [sp, #S_X4] | |
54 | ldp x6, x7, [sp, #S_X6] | |
55 | .endif | |
56 | #endif | |
57 | .endm | |
58 | ||
59 | .macro ct_user_enter | |
60 | #ifdef CONFIG_CONTEXT_TRACKING | |
61 | bl context_tracking_user_enter | |
62 | #endif | |
63 | .endm | |
64 | ||
60ffc30d CM |
65 | /* |
66 | * Bad Abort numbers | |
67 | *----------------- | |
68 | */ | |
69 | #define BAD_SYNC 0 | |
70 | #define BAD_IRQ 1 | |
71 | #define BAD_FIQ 2 | |
72 | #define BAD_ERROR 3 | |
73 | ||
204fcde9 | 74 | .macro kernel_ventry, el, label, regsize = 64 |
32c7b60c | 75 | .align 7 |
6c873091 WD |
76 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
77 | .if \el == 0 | |
78 | .if \regsize == 64 | |
79 | mrs x30, tpidrro_el0 | |
80 | msr tpidrro_el0, xzr | |
81 | .else | |
82 | mov x30, xzr | |
83 | .endif | |
84 | .endif | |
85 | #endif | |
86 | ||
63648dd2 | 87 | sub sp, sp, #S_FRAME_SIZE |
7b7dbeee MR |
88 | #ifdef CONFIG_VMAP_STACK |
89 | /* | |
90 | * Test whether the SP has overflowed, without corrupting a GPR. | |
91 | * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT). | |
92 | */ | |
93 | add sp, sp, x0 // sp' = sp + x0 | |
94 | sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp | |
95 | tbnz x0, #THREAD_SHIFT, 0f | |
96 | sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 | |
97 | sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp | |
204fcde9 | 98 | b el\()\el\()_\label |
7b7dbeee MR |
99 | |
100 | 0: | |
101 | /* | |
102 | * Either we've just detected an overflow, or we've taken an exception | |
103 | * while on the overflow stack. Either way, we won't return to | |
104 | * userspace, and can clobber EL0 registers to free up GPRs. | |
105 | */ | |
106 | ||
107 | /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */ | |
108 | msr tpidr_el0, x0 | |
109 | ||
110 | /* Recover the original x0 value and stash it in tpidrro_el0 */ | |
111 | sub x0, sp, x0 | |
112 | msr tpidrro_el0, x0 | |
113 | ||
114 | /* Switch to the overflow stack */ | |
115 | adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 | |
116 | ||
117 | /* | |
118 | * Check whether we were already on the overflow stack. This may happen | |
119 | * after panic() re-enables interrupts. | |
120 | */ | |
121 | mrs x0, tpidr_el0 // sp of interrupted context | |
122 | sub x0, sp, x0 // delta with top of overflow stack | |
123 | tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? | |
124 | b.ne __bad_stack // no? -> bad stack pointer | |
125 | ||
126 | /* We were already on the overflow stack. Restore sp/x0 and carry on. */ | |
127 | sub sp, sp, x0 | |
128 | mrs x0, tpidrro_el0 | |
129 | #endif | |
204fcde9 | 130 | b el\()\el\()_\label |
32c7b60c MR |
131 | .endm |
132 | ||
6c873091 WD |
133 | .macro tramp_alias, dst, sym |
134 | mov_q \dst, TRAMP_VALIAS | |
135 | add \dst, \dst, #(\sym - .entry.tramp.text) | |
136 | .endm | |
137 | ||
32c7b60c | 138 | .macro kernel_entry, el, regsize = 64 |
60ffc30d CM |
139 | .if \regsize == 32 |
140 | mov w0, w0 // zero upper 32 bits of x0 | |
141 | .endif | |
63648dd2 WD |
142 | stp x0, x1, [sp, #16 * 0] |
143 | stp x2, x3, [sp, #16 * 1] | |
144 | stp x4, x5, [sp, #16 * 2] | |
145 | stp x6, x7, [sp, #16 * 3] | |
146 | stp x8, x9, [sp, #16 * 4] | |
147 | stp x10, x11, [sp, #16 * 5] | |
148 | stp x12, x13, [sp, #16 * 6] | |
149 | stp x14, x15, [sp, #16 * 7] | |
150 | stp x16, x17, [sp, #16 * 8] | |
151 | stp x18, x19, [sp, #16 * 9] | |
152 | stp x20, x21, [sp, #16 * 10] | |
153 | stp x22, x23, [sp, #16 * 11] | |
154 | stp x24, x25, [sp, #16 * 12] | |
155 | stp x26, x27, [sp, #16 * 13] | |
156 | stp x28, x29, [sp, #16 * 14] | |
157 | ||
60ffc30d CM |
158 | .if \el == 0 |
159 | mrs x21, sp_el0 | |
c02433dd MR |
160 | ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear, |
161 | ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug | |
2a283070 | 162 | disable_step_tsk x19, x20 // exceptions when scheduling. |
49003a8d JM |
163 | |
164 | mov x29, xzr // fp pointed to user-space | |
60ffc30d CM |
165 | .else |
166 | add x21, sp, #S_FRAME_SIZE | |
e19a6ee2 JM |
167 | get_thread_info tsk |
168 | /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ | |
c02433dd | 169 | ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
170 | str x20, [sp, #S_ORIG_ADDR_LIMIT] |
171 | mov x20, #TASK_SIZE_64 | |
c02433dd | 172 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
563cada0 | 173 | /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ |
e19a6ee2 | 174 | .endif /* \el == 0 */ |
60ffc30d CM |
175 | mrs x22, elr_el1 |
176 | mrs x23, spsr_el1 | |
177 | stp lr, x21, [sp, #S_LR] | |
39bc88e5 | 178 | |
417d8004 AB |
179 | /* |
180 | * In order to be able to dump the contents of struct pt_regs at the | |
181 | * time the exception was taken (in case we attempt to walk the call | |
182 | * stack later), chain it together with the stack frames. | |
183 | */ | |
184 | .if \el == 0 | |
185 | stp xzr, xzr, [sp, #S_STACKFRAME] | |
186 | .else | |
187 | stp x29, x22, [sp, #S_STACKFRAME] | |
188 | .endif | |
189 | add x29, sp, #S_STACKFRAME | |
190 | ||
39bc88e5 CM |
191 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
192 | /* | |
193 | * Set the TTBR0 PAN bit in SPSR. When the exception is taken from | |
194 | * EL0, there is no need to check the state of TTBR0_EL1 since | |
195 | * accesses are always enabled. | |
196 | * Note that the meaning of this bit differs from the ARMv8.1 PAN | |
197 | * feature as all TTBR0_EL1 accesses are disabled, not just those to | |
198 | * user mappings. | |
199 | */ | |
200 | alternative_if ARM64_HAS_PAN | |
201 | b 1f // skip TTBR0 PAN | |
202 | alternative_else_nop_endif | |
203 | ||
204 | .if \el != 0 | |
ad5e86dc | 205 | mrs x21, ttbr1_el1 |
39bc88e5 CM |
206 | tst x21, #0xffff << 48 // Check for the reserved ASID |
207 | orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR | |
208 | b.eq 1f // TTBR0 access already disabled | |
209 | and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR | |
210 | .endif | |
211 | ||
212 | __uaccess_ttbr0_disable x21 | |
213 | 1: | |
214 | #endif | |
215 | ||
60ffc30d CM |
216 | stp x22, x23, [sp, #S_PC] |
217 | ||
218 | /* | |
219 | * Set syscallno to -1 by default (overridden later if real syscall). | |
220 | */ | |
221 | .if \el == 0 | |
a01a0518 DM |
222 | mvn w21, wzr |
223 | str w21, [sp, #S_SYSCALLNO] | |
60ffc30d CM |
224 | .endif |
225 | ||
6cdf9c7c JL |
226 | /* |
227 | * Set sp_el0 to current thread_info. | |
228 | */ | |
229 | .if \el == 0 | |
230 | msr sp_el0, tsk | |
231 | .endif | |
232 | ||
60ffc30d CM |
233 | /* |
234 | * Registers that may be useful after this macro is invoked: | |
235 | * | |
236 | * x21 - aborted SP | |
237 | * x22 - aborted PC | |
238 | * x23 - aborted PSTATE | |
239 | */ | |
240 | .endm | |
241 | ||
412fcb6c | 242 | .macro kernel_exit, el |
e19a6ee2 JM |
243 | .if \el != 0 |
244 | /* Restore the task's original addr_limit. */ | |
245 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] | |
c02433dd | 246 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
247 | |
248 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ | |
249 | .endif | |
250 | ||
60ffc30d CM |
251 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
252 | .if \el == 0 | |
6c81fe79 | 253 | ct_user_enter |
39bc88e5 CM |
254 | .endif |
255 | ||
256 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN | |
257 | /* | |
258 | * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR | |
259 | * PAN bit checking. | |
260 | */ | |
261 | alternative_if ARM64_HAS_PAN | |
262 | b 2f // skip TTBR0 PAN | |
263 | alternative_else_nop_endif | |
264 | ||
265 | .if \el != 0 | |
266 | tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set | |
267 | .endif | |
268 | ||
ad5e86dc | 269 | __uaccess_ttbr0_enable x0, x1 |
39bc88e5 CM |
270 | |
271 | .if \el == 0 | |
272 | /* | |
273 | * Enable errata workarounds only if returning to user. The only | |
274 | * workaround currently required for TTBR0_EL1 changes are for the | |
275 | * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache | |
276 | * corruption). | |
277 | */ | |
301e3bc5 | 278 | post_ttbr_update_workaround |
39bc88e5 CM |
279 | .endif |
280 | 1: | |
281 | .if \el != 0 | |
282 | and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit | |
283 | .endif | |
284 | 2: | |
285 | #endif | |
286 | ||
287 | .if \el == 0 | |
60ffc30d | 288 | ldr x23, [sp, #S_SP] // load return stack pointer |
63648dd2 | 289 | msr sp_el0, x23 |
6c873091 WD |
290 | tst x22, #PSR_MODE32_BIT // native task? |
291 | b.eq 3f | |
292 | ||
905e8c5d | 293 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
6ba3b554 | 294 | alternative_if ARM64_WORKAROUND_845719 |
e28cabf1 DT |
295 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
296 | mrs x29, contextidr_el1 | |
297 | msr contextidr_el1, x29 | |
905e8c5d | 298 | #else |
e28cabf1 | 299 | msr contextidr_el1, xzr |
905e8c5d | 300 | #endif |
6ba3b554 | 301 | alternative_else_nop_endif |
905e8c5d | 302 | #endif |
6c873091 | 303 | 3: |
60ffc30d | 304 | .endif |
39bc88e5 | 305 | |
63648dd2 WD |
306 | msr elr_el1, x21 // set up the return data |
307 | msr spsr_el1, x22 | |
63648dd2 | 308 | ldp x0, x1, [sp, #16 * 0] |
63648dd2 WD |
309 | ldp x2, x3, [sp, #16 * 1] |
310 | ldp x4, x5, [sp, #16 * 2] | |
311 | ldp x6, x7, [sp, #16 * 3] | |
312 | ldp x8, x9, [sp, #16 * 4] | |
313 | ldp x10, x11, [sp, #16 * 5] | |
314 | ldp x12, x13, [sp, #16 * 6] | |
315 | ldp x14, x15, [sp, #16 * 7] | |
316 | ldp x16, x17, [sp, #16 * 8] | |
317 | ldp x18, x19, [sp, #16 * 9] | |
318 | ldp x20, x21, [sp, #16 * 10] | |
319 | ldp x22, x23, [sp, #16 * 11] | |
320 | ldp x24, x25, [sp, #16 * 12] | |
321 | ldp x26, x27, [sp, #16 * 13] | |
322 | ldp x28, x29, [sp, #16 * 14] | |
323 | ldr lr, [sp, #S_LR] | |
324 | add sp, sp, #S_FRAME_SIZE // restore sp | |
6c873091 WD |
325 | |
326 | #ifndef CONFIG_UNMAP_KERNEL_AT_EL0 | |
327 | eret | |
328 | #else | |
329 | .if \el == 0 | |
330 | bne 4f | |
331 | msr far_el1, x30 | |
332 | tramp_alias x30, tramp_exit_native | |
333 | br x30 | |
334 | 4: | |
335 | tramp_alias x30, tramp_exit_compat | |
336 | br x30 | |
337 | .else | |
338 | eret | |
339 | .endif | |
340 | #endif | |
60ffc30d CM |
341 | .endm |
342 | ||
971c67ce | 343 | .macro irq_stack_entry |
8e23dacd JM |
344 | mov x19, sp // preserve the original sp |
345 | ||
8e23dacd | 346 | /* |
c02433dd MR |
347 | * Compare sp with the base of the task stack. |
348 | * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, | |
349 | * and should switch to the irq stack. | |
8e23dacd | 350 | */ |
c02433dd MR |
351 | ldr x25, [tsk, TSK_STACK] |
352 | eor x25, x25, x19 | |
353 | and x25, x25, #~(THREAD_SIZE - 1) | |
354 | cbnz x25, 9998f | |
8e23dacd | 355 | |
89b03e63 | 356 | ldr_this_cpu x25, irq_stack_ptr, x26 |
38710367 | 357 | mov x26, #IRQ_STACK_SIZE |
8e23dacd | 358 | add x26, x25, x26 |
d224a69e JM |
359 | |
360 | /* switch to the irq stack */ | |
8e23dacd | 361 | mov sp, x26 |
8e23dacd JM |
362 | 9998: |
363 | .endm | |
364 | ||
365 | /* | |
366 | * x19 should be preserved between irq_stack_entry and | |
367 | * irq_stack_exit. | |
368 | */ | |
369 | .macro irq_stack_exit | |
370 | mov sp, x19 | |
371 | .endm | |
372 | ||
60ffc30d CM |
373 | /* |
374 | * These are the registers used in the syscall handler, and allow us to | |
375 | * have in theory up to 7 arguments to a function - x0 to x6. | |
376 | * | |
377 | * x7 is reserved for the system call number in 32-bit mode. | |
378 | */ | |
a01a0518 DM |
379 | wsc_nr .req w25 // number of system calls |
380 | wscno .req w26 // syscall number | |
381 | xscno .req x26 // syscall number (zero-extended) | |
60ffc30d CM |
382 | stbl .req x27 // syscall table pointer |
383 | tsk .req x28 // current thread_info | |
384 | ||
385 | /* | |
386 | * Interrupt handling. | |
387 | */ | |
388 | .macro irq_handler | |
8e23dacd | 389 | ldr_l x1, handle_arch_irq |
60ffc30d | 390 | mov x0, sp |
971c67ce | 391 | irq_stack_entry |
60ffc30d | 392 | blr x1 |
8e23dacd | 393 | irq_stack_exit |
60ffc30d CM |
394 | .endm |
395 | ||
396 | .text | |
397 | ||
398 | /* | |
399 | * Exception vectors. | |
400 | */ | |
888b3c87 | 401 | .pushsection ".entry.text", "ax" |
60ffc30d CM |
402 | |
403 | .align 11 | |
404 | ENTRY(vectors) | |
204fcde9 WD |
405 | kernel_ventry 1, sync_invalid // Synchronous EL1t |
406 | kernel_ventry 1, irq_invalid // IRQ EL1t | |
407 | kernel_ventry 1, fiq_invalid // FIQ EL1t | |
408 | kernel_ventry 1, error_invalid // Error EL1t | |
60ffc30d | 409 | |
204fcde9 WD |
410 | kernel_ventry 1, sync // Synchronous EL1h |
411 | kernel_ventry 1, irq // IRQ EL1h | |
412 | kernel_ventry 1, fiq_invalid // FIQ EL1h | |
413 | kernel_ventry 1, error_invalid // Error EL1h | |
60ffc30d | 414 | |
204fcde9 WD |
415 | kernel_ventry 0, sync // Synchronous 64-bit EL0 |
416 | kernel_ventry 0, irq // IRQ 64-bit EL0 | |
417 | kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 | |
418 | kernel_ventry 0, error_invalid // Error 64-bit EL0 | |
60ffc30d CM |
419 | |
420 | #ifdef CONFIG_COMPAT | |
204fcde9 WD |
421 | kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 |
422 | kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 | |
423 | kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 | |
424 | kernel_ventry 0, error_invalid_compat, 32 // Error 32-bit EL0 | |
60ffc30d | 425 | #else |
204fcde9 WD |
426 | kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 |
427 | kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 | |
428 | kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 | |
429 | kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 | |
60ffc30d CM |
430 | #endif |
431 | END(vectors) | |
432 | ||
7b7dbeee MR |
433 | #ifdef CONFIG_VMAP_STACK |
434 | /* | |
435 | * We detected an overflow in kernel_ventry, which switched to the | |
436 | * overflow stack. Stash the exception regs, and head to our overflow | |
437 | * handler. | |
438 | */ | |
439 | __bad_stack: | |
440 | /* Restore the original x0 value */ | |
441 | mrs x0, tpidrro_el0 | |
442 | ||
443 | /* | |
444 | * Store the original GPRs to the new stack. The orginal SP (minus | |
445 | * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry. | |
446 | */ | |
447 | sub sp, sp, #S_FRAME_SIZE | |
448 | kernel_entry 1 | |
449 | mrs x0, tpidr_el0 | |
450 | add x0, x0, #S_FRAME_SIZE | |
451 | str x0, [sp, #S_SP] | |
452 | ||
453 | /* Stash the regs for handle_bad_stack */ | |
454 | mov x0, sp | |
455 | ||
456 | /* Time to die */ | |
457 | bl handle_bad_stack | |
458 | ASM_BUG() | |
459 | #endif /* CONFIG_VMAP_STACK */ | |
460 | ||
60ffc30d CM |
461 | /* |
462 | * Invalid mode handlers | |
463 | */ | |
464 | .macro inv_entry, el, reason, regsize = 64 | |
b660950c | 465 | kernel_entry \el, \regsize |
60ffc30d CM |
466 | mov x0, sp |
467 | mov x1, #\reason | |
468 | mrs x2, esr_el1 | |
34a84041 MR |
469 | bl bad_mode |
470 | ASM_BUG() | |
60ffc30d CM |
471 | .endm |
472 | ||
473 | el0_sync_invalid: | |
474 | inv_entry 0, BAD_SYNC | |
475 | ENDPROC(el0_sync_invalid) | |
476 | ||
477 | el0_irq_invalid: | |
478 | inv_entry 0, BAD_IRQ | |
479 | ENDPROC(el0_irq_invalid) | |
480 | ||
481 | el0_fiq_invalid: | |
482 | inv_entry 0, BAD_FIQ | |
483 | ENDPROC(el0_fiq_invalid) | |
484 | ||
485 | el0_error_invalid: | |
486 | inv_entry 0, BAD_ERROR | |
487 | ENDPROC(el0_error_invalid) | |
488 | ||
489 | #ifdef CONFIG_COMPAT | |
490 | el0_fiq_invalid_compat: | |
491 | inv_entry 0, BAD_FIQ, 32 | |
492 | ENDPROC(el0_fiq_invalid_compat) | |
493 | ||
494 | el0_error_invalid_compat: | |
495 | inv_entry 0, BAD_ERROR, 32 | |
496 | ENDPROC(el0_error_invalid_compat) | |
497 | #endif | |
498 | ||
499 | el1_sync_invalid: | |
500 | inv_entry 1, BAD_SYNC | |
501 | ENDPROC(el1_sync_invalid) | |
502 | ||
503 | el1_irq_invalid: | |
504 | inv_entry 1, BAD_IRQ | |
505 | ENDPROC(el1_irq_invalid) | |
506 | ||
507 | el1_fiq_invalid: | |
508 | inv_entry 1, BAD_FIQ | |
509 | ENDPROC(el1_fiq_invalid) | |
510 | ||
511 | el1_error_invalid: | |
512 | inv_entry 1, BAD_ERROR | |
513 | ENDPROC(el1_error_invalid) | |
514 | ||
515 | /* | |
516 | * EL1 mode handlers. | |
517 | */ | |
518 | .align 6 | |
519 | el1_sync: | |
520 | kernel_entry 1 | |
521 | mrs x1, esr_el1 // read the syndrome register | |
aed40e01 MR |
522 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
523 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 | |
60ffc30d | 524 | b.eq el1_da |
9adeb8e7 LA |
525 | cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 |
526 | b.eq el1_ia | |
aed40e01 | 527 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 528 | b.eq el1_undef |
aed40e01 | 529 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 530 | b.eq el1_sp_pc |
aed40e01 | 531 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 532 | b.eq el1_sp_pc |
aed40e01 | 533 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
60ffc30d | 534 | b.eq el1_undef |
aed40e01 | 535 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
60ffc30d CM |
536 | b.ge el1_dbg |
537 | b el1_inv | |
9adeb8e7 LA |
538 | |
539 | el1_ia: | |
540 | /* | |
541 | * Fall through to the Data abort case | |
542 | */ | |
60ffc30d CM |
543 | el1_da: |
544 | /* | |
545 | * Data abort handling | |
546 | */ | |
276e9327 | 547 | mrs x3, far_el1 |
2a283070 | 548 | enable_dbg |
60ffc30d CM |
549 | // re-enable interrupts if they were enabled in the aborted context |
550 | tbnz x23, #7, 1f // PSR_I_BIT | |
551 | enable_irq | |
552 | 1: | |
276e9327 | 553 | clear_address_tag x0, x3 |
60ffc30d CM |
554 | mov x2, sp // struct pt_regs |
555 | bl do_mem_abort | |
556 | ||
557 | // disable interrupts before pulling preserved data off the stack | |
558 | disable_irq | |
559 | kernel_exit 1 | |
560 | el1_sp_pc: | |
561 | /* | |
562 | * Stack or PC alignment exception handling | |
563 | */ | |
564 | mrs x0, far_el1 | |
2a283070 | 565 | enable_dbg |
60ffc30d | 566 | mov x2, sp |
34a84041 MR |
567 | bl do_sp_pc_abort |
568 | ASM_BUG() | |
60ffc30d CM |
569 | el1_undef: |
570 | /* | |
571 | * Undefined instruction | |
572 | */ | |
2a283070 | 573 | enable_dbg |
60ffc30d | 574 | mov x0, sp |
34a84041 MR |
575 | bl do_undefinstr |
576 | ASM_BUG() | |
60ffc30d CM |
577 | el1_dbg: |
578 | /* | |
579 | * Debug exception handling | |
580 | */ | |
aed40e01 | 581 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
ee6214ce | 582 | cinc x24, x24, eq // set bit '0' |
60ffc30d CM |
583 | tbz x24, #0, el1_inv // EL1 only |
584 | mrs x0, far_el1 | |
585 | mov x2, sp // struct pt_regs | |
586 | bl do_debug_exception | |
60ffc30d CM |
587 | kernel_exit 1 |
588 | el1_inv: | |
589 | // TODO: add support for undefined instructions in kernel mode | |
2a283070 | 590 | enable_dbg |
60ffc30d | 591 | mov x0, sp |
1b42804d | 592 | mov x2, x1 |
60ffc30d | 593 | mov x1, #BAD_SYNC |
34a84041 MR |
594 | bl bad_mode |
595 | ASM_BUG() | |
60ffc30d CM |
596 | ENDPROC(el1_sync) |
597 | ||
598 | .align 6 | |
599 | el1_irq: | |
600 | kernel_entry 1 | |
2a283070 | 601 | enable_dbg |
60ffc30d CM |
602 | #ifdef CONFIG_TRACE_IRQFLAGS |
603 | bl trace_hardirqs_off | |
604 | #endif | |
64681787 | 605 | |
60ffc30d | 606 | irq_handler |
64681787 | 607 | |
60ffc30d | 608 | #ifdef CONFIG_PREEMPT |
c02433dd | 609 | ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count |
717321fc | 610 | cbnz w24, 1f // preempt count != 0 |
c02433dd | 611 | ldr x0, [tsk, #TSK_TI_FLAGS] // get flags |
60ffc30d CM |
612 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
613 | bl el1_preempt | |
614 | 1: | |
615 | #endif | |
616 | #ifdef CONFIG_TRACE_IRQFLAGS | |
617 | bl trace_hardirqs_on | |
618 | #endif | |
619 | kernel_exit 1 | |
620 | ENDPROC(el1_irq) | |
621 | ||
622 | #ifdef CONFIG_PREEMPT | |
623 | el1_preempt: | |
624 | mov x24, lr | |
2a283070 | 625 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
c02433dd | 626 | ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS |
60ffc30d CM |
627 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? |
628 | ret x24 | |
629 | #endif | |
630 | ||
631 | /* | |
632 | * EL0 mode handlers. | |
633 | */ | |
634 | .align 6 | |
635 | el0_sync: | |
636 | kernel_entry 0 | |
637 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
638 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
639 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state | |
60ffc30d | 640 | b.eq el0_svc |
aed40e01 | 641 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 642 | b.eq el0_da |
aed40e01 | 643 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 644 | b.eq el0_ia |
aed40e01 | 645 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 646 | b.eq el0_fpsimd_acc |
aed40e01 | 647 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
60ffc30d | 648 | b.eq el0_fpsimd_exc |
aed40e01 | 649 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
7dd01aef | 650 | b.eq el0_sys |
aed40e01 | 651 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 652 | b.eq el0_sp_pc |
aed40e01 | 653 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 654 | b.eq el0_sp_pc |
aed40e01 | 655 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 656 | b.eq el0_undef |
aed40e01 | 657 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
658 | b.ge el0_dbg |
659 | b el0_inv | |
660 | ||
661 | #ifdef CONFIG_COMPAT | |
662 | .align 6 | |
663 | el0_sync_compat: | |
664 | kernel_entry 0, 32 | |
665 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
666 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
667 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state | |
60ffc30d | 668 | b.eq el0_svc_compat |
aed40e01 | 669 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 670 | b.eq el0_da |
aed40e01 | 671 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 672 | b.eq el0_ia |
aed40e01 | 673 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 674 | b.eq el0_fpsimd_acc |
aed40e01 | 675 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
60ffc30d | 676 | b.eq el0_fpsimd_exc |
77f3228f MS |
677 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
678 | b.eq el0_sp_pc | |
aed40e01 | 679 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 680 | b.eq el0_undef |
aed40e01 | 681 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
381cc2b9 | 682 | b.eq el0_undef |
aed40e01 | 683 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
381cc2b9 | 684 | b.eq el0_undef |
aed40e01 | 685 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
381cc2b9 | 686 | b.eq el0_undef |
aed40e01 | 687 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
381cc2b9 | 688 | b.eq el0_undef |
aed40e01 | 689 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
381cc2b9 | 690 | b.eq el0_undef |
aed40e01 | 691 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
692 | b.ge el0_dbg |
693 | b el0_inv | |
694 | el0_svc_compat: | |
695 | /* | |
696 | * AArch32 syscall handling | |
697 | */ | |
0156411b | 698 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
a01a0518 DM |
699 | mov wscno, w7 // syscall number in w7 (r7) |
700 | mov wsc_nr, #__NR_compat_syscalls | |
60ffc30d CM |
701 | b el0_svc_naked |
702 | ||
703 | .align 6 | |
704 | el0_irq_compat: | |
705 | kernel_entry 0, 32 | |
706 | b el0_irq_naked | |
707 | #endif | |
708 | ||
709 | el0_da: | |
710 | /* | |
711 | * Data abort handling | |
712 | */ | |
6ab6463a | 713 | mrs x26, far_el1 |
60ffc30d | 714 | // enable interrupts before calling the main handler |
2a283070 | 715 | enable_dbg_and_irq |
6c81fe79 | 716 | ct_user_exit |
276e9327 | 717 | clear_address_tag x0, x26 |
60ffc30d CM |
718 | mov x1, x25 |
719 | mov x2, sp | |
d54e81f9 WD |
720 | bl do_mem_abort |
721 | b ret_to_user | |
60ffc30d CM |
722 | el0_ia: |
723 | /* | |
724 | * Instruction abort handling | |
725 | */ | |
6ab6463a | 726 | mrs x26, far_el1 |
60ffc30d | 727 | // enable interrupts before calling the main handler |
2a283070 | 728 | enable_dbg_and_irq |
6c81fe79 | 729 | ct_user_exit |
6ab6463a | 730 | mov x0, x26 |
541ec870 | 731 | mov x1, x25 |
60ffc30d | 732 | mov x2, sp |
d54e81f9 WD |
733 | bl do_mem_abort |
734 | b ret_to_user | |
60ffc30d CM |
735 | el0_fpsimd_acc: |
736 | /* | |
737 | * Floating Point or Advanced SIMD access | |
738 | */ | |
2a283070 | 739 | enable_dbg |
6c81fe79 | 740 | ct_user_exit |
60ffc30d CM |
741 | mov x0, x25 |
742 | mov x1, sp | |
d54e81f9 WD |
743 | bl do_fpsimd_acc |
744 | b ret_to_user | |
60ffc30d CM |
745 | el0_fpsimd_exc: |
746 | /* | |
747 | * Floating Point or Advanced SIMD exception | |
748 | */ | |
2a283070 | 749 | enable_dbg |
6c81fe79 | 750 | ct_user_exit |
60ffc30d CM |
751 | mov x0, x25 |
752 | mov x1, sp | |
d54e81f9 WD |
753 | bl do_fpsimd_exc |
754 | b ret_to_user | |
60ffc30d CM |
755 | el0_sp_pc: |
756 | /* | |
757 | * Stack or PC alignment exception handling | |
758 | */ | |
6ab6463a | 759 | mrs x26, far_el1 |
60ffc30d | 760 | // enable interrupts before calling the main handler |
2a283070 | 761 | enable_dbg_and_irq |
46b0567c | 762 | ct_user_exit |
6ab6463a | 763 | mov x0, x26 |
60ffc30d CM |
764 | mov x1, x25 |
765 | mov x2, sp | |
d54e81f9 WD |
766 | bl do_sp_pc_abort |
767 | b ret_to_user | |
60ffc30d CM |
768 | el0_undef: |
769 | /* | |
770 | * Undefined instruction | |
771 | */ | |
2600e130 | 772 | // enable interrupts before calling the main handler |
2a283070 | 773 | enable_dbg_and_irq |
6c81fe79 | 774 | ct_user_exit |
2a283070 | 775 | mov x0, sp |
d54e81f9 WD |
776 | bl do_undefinstr |
777 | b ret_to_user | |
7dd01aef AP |
778 | el0_sys: |
779 | /* | |
780 | * System instructions, for trapped cache maintenance instructions | |
781 | */ | |
782 | enable_dbg_and_irq | |
783 | ct_user_exit | |
784 | mov x0, x25 | |
785 | mov x1, sp | |
786 | bl do_sysinstr | |
787 | b ret_to_user | |
60ffc30d CM |
788 | el0_dbg: |
789 | /* | |
790 | * Debug exception handling | |
791 | */ | |
792 | tbnz x24, #0, el0_inv // EL0 only | |
793 | mrs x0, far_el1 | |
60ffc30d CM |
794 | mov x1, x25 |
795 | mov x2, sp | |
2a283070 WD |
796 | bl do_debug_exception |
797 | enable_dbg | |
6c81fe79 | 798 | ct_user_exit |
2a283070 | 799 | b ret_to_user |
60ffc30d | 800 | el0_inv: |
2a283070 | 801 | enable_dbg |
6c81fe79 | 802 | ct_user_exit |
60ffc30d CM |
803 | mov x0, sp |
804 | mov x1, #BAD_SYNC | |
1b42804d | 805 | mov x2, x25 |
7d9e8f71 | 806 | bl bad_el0_sync |
d54e81f9 | 807 | b ret_to_user |
60ffc30d CM |
808 | ENDPROC(el0_sync) |
809 | ||
810 | .align 6 | |
811 | el0_irq: | |
812 | kernel_entry 0 | |
813 | el0_irq_naked: | |
60ffc30d CM |
814 | enable_dbg |
815 | #ifdef CONFIG_TRACE_IRQFLAGS | |
816 | bl trace_hardirqs_off | |
817 | #endif | |
64681787 | 818 | |
6c81fe79 | 819 | ct_user_exit |
60ffc30d | 820 | irq_handler |
64681787 | 821 | |
60ffc30d CM |
822 | #ifdef CONFIG_TRACE_IRQFLAGS |
823 | bl trace_hardirqs_on | |
824 | #endif | |
825 | b ret_to_user | |
826 | ENDPROC(el0_irq) | |
827 | ||
60ffc30d CM |
828 | /* |
829 | * This is the fast syscall return path. We do as little as possible here, | |
830 | * and this includes saving x0 back into the kernel stack. | |
831 | */ | |
832 | ret_fast_syscall: | |
833 | disable_irq // disable interrupts | |
412fcb6c | 834 | str x0, [sp, #S_X0] // returned x0 |
c02433dd | 835 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing |
04d7e098 JS |
836 | and x2, x1, #_TIF_SYSCALL_WORK |
837 | cbnz x2, ret_fast_syscall_trace | |
60ffc30d | 838 | and x2, x1, #_TIF_WORK_MASK |
412fcb6c | 839 | cbnz x2, work_pending |
2a283070 | 840 | enable_step_tsk x1, x2 |
412fcb6c | 841 | kernel_exit 0 |
04d7e098 JS |
842 | ret_fast_syscall_trace: |
843 | enable_irq // enable interrupts | |
412fcb6c | 844 | b __sys_trace_return_skipped // we already saved x0 |
60ffc30d CM |
845 | |
846 | /* | |
847 | * Ok, we need to do extra processing, enter the slow path. | |
848 | */ | |
60ffc30d | 849 | work_pending: |
60ffc30d | 850 | mov x0, sp // 'regs' |
60ffc30d | 851 | bl do_notify_resume |
db3899a6 | 852 | #ifdef CONFIG_TRACE_IRQFLAGS |
421dd6fa | 853 | bl trace_hardirqs_on // enabled while in userspace |
db3899a6 | 854 | #endif |
c02433dd | 855 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step |
421dd6fa | 856 | b finish_ret_to_user |
60ffc30d CM |
857 | /* |
858 | * "slow" syscall return path. | |
859 | */ | |
59dc67b0 | 860 | ret_to_user: |
60ffc30d | 861 | disable_irq // disable interrupts |
c02433dd | 862 | ldr x1, [tsk, #TSK_TI_FLAGS] |
60ffc30d CM |
863 | and x2, x1, #_TIF_WORK_MASK |
864 | cbnz x2, work_pending | |
421dd6fa | 865 | finish_ret_to_user: |
2a283070 | 866 | enable_step_tsk x1, x2 |
412fcb6c | 867 | kernel_exit 0 |
60ffc30d CM |
868 | ENDPROC(ret_to_user) |
869 | ||
60ffc30d CM |
870 | /* |
871 | * SVC handler. | |
872 | */ | |
873 | .align 6 | |
874 | el0_svc: | |
875 | adrp stbl, sys_call_table // load syscall table pointer | |
a01a0518 DM |
876 | mov wscno, w8 // syscall number in w8 |
877 | mov wsc_nr, #__NR_syscalls | |
60ffc30d | 878 | el0_svc_naked: // compat entry point |
a01a0518 | 879 | stp x0, xscno, [sp, #S_ORIG_X0] // save the original x0 and syscall number |
2a283070 | 880 | enable_dbg_and_irq |
6c81fe79 | 881 | ct_user_exit 1 |
60ffc30d | 882 | |
c02433dd | 883 | ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks |
449f81a4 AT |
884 | tst x16, #_TIF_SYSCALL_WORK |
885 | b.ne __sys_trace | |
a01a0518 | 886 | cmp wscno, wsc_nr // check upper syscall limit |
60ffc30d | 887 | b.hs ni_sys |
a01a0518 | 888 | ldr x16, [stbl, xscno, lsl #3] // address in the syscall table |
d54e81f9 WD |
889 | blr x16 // call sys_* routine |
890 | b ret_fast_syscall | |
60ffc30d CM |
891 | ni_sys: |
892 | mov x0, sp | |
d54e81f9 WD |
893 | bl do_ni_syscall |
894 | b ret_fast_syscall | |
60ffc30d CM |
895 | ENDPROC(el0_svc) |
896 | ||
897 | /* | |
898 | * This is the really slow path. We're going to be doing context | |
899 | * switches, and waiting for our parent to respond. | |
900 | */ | |
901 | __sys_trace: | |
a01a0518 | 902 | cmp wscno, #-1 // user-issued syscall(-1)? |
1014c81d | 903 | b.ne 1f |
a01a0518 | 904 | mov x0, #-ENOSYS // set default errno if so |
1014c81d AT |
905 | str x0, [sp, #S_X0] |
906 | 1: mov x0, sp | |
3157858f | 907 | bl syscall_trace_enter |
1014c81d AT |
908 | cmp w0, #-1 // skip the syscall? |
909 | b.eq __sys_trace_return_skipped | |
a01a0518 | 910 | mov wscno, w0 // syscall number (possibly new) |
60ffc30d | 911 | mov x1, sp // pointer to regs |
a01a0518 | 912 | cmp wscno, wsc_nr // check upper syscall limit |
d54e81f9 | 913 | b.hs __ni_sys_trace |
60ffc30d CM |
914 | ldp x0, x1, [sp] // restore the syscall args |
915 | ldp x2, x3, [sp, #S_X2] | |
916 | ldp x4, x5, [sp, #S_X4] | |
917 | ldp x6, x7, [sp, #S_X6] | |
a01a0518 | 918 | ldr x16, [stbl, xscno, lsl #3] // address in the syscall table |
d54e81f9 | 919 | blr x16 // call sys_* routine |
60ffc30d CM |
920 | |
921 | __sys_trace_return: | |
1014c81d AT |
922 | str x0, [sp, #S_X0] // save returned x0 |
923 | __sys_trace_return_skipped: | |
3157858f AT |
924 | mov x0, sp |
925 | bl syscall_trace_exit | |
60ffc30d CM |
926 | b ret_to_user |
927 | ||
d54e81f9 WD |
928 | __ni_sys_trace: |
929 | mov x0, sp | |
930 | bl do_ni_syscall | |
931 | b __sys_trace_return | |
932 | ||
888b3c87 PA |
933 | .popsection // .entry.text |
934 | ||
95a2833d WD |
935 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
936 | /* | |
937 | * Exception vectors trampoline. | |
938 | */ | |
939 | .pushsection ".entry.tramp.text", "ax" | |
940 | ||
941 | .macro tramp_map_kernel, tmp | |
942 | mrs \tmp, ttbr1_el1 | |
943 | sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) | |
944 | bic \tmp, \tmp, #USER_ASID_FLAG | |
945 | msr ttbr1_el1, \tmp | |
7aa99b55 WD |
946 | #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 |
947 | alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 | |
948 | /* ASID already in \tmp[63:48] */ | |
949 | movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) | |
950 | movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) | |
951 | /* 2MB boundary containing the vectors, so we nobble the walk cache */ | |
952 | movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) | |
953 | isb | |
954 | tlbi vae1, \tmp | |
955 | dsb nsh | |
956 | alternative_else_nop_endif | |
957 | #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ | |
95a2833d WD |
958 | .endm |
959 | ||
960 | .macro tramp_unmap_kernel, tmp | |
961 | mrs \tmp, ttbr1_el1 | |
962 | add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) | |
963 | orr \tmp, \tmp, #USER_ASID_FLAG | |
964 | msr ttbr1_el1, \tmp | |
965 | /* | |
966 | * We avoid running the post_ttbr_update_workaround here because the | |
967 | * user and kernel ASIDs don't have conflicting mappings, so any | |
968 | * "blessing" as described in: | |
969 | * | |
970 | * http://lkml.kernel.org/r/56BB848A.6060603@caviumnetworks.com | |
971 | * | |
972 | * will not hurt correctness. Whilst this may partially defeat the | |
973 | * point of using split ASIDs in the first place, it avoids | |
974 | * the hit of invalidating the entire I-cache on every return to | |
975 | * userspace. | |
976 | */ | |
977 | .endm | |
978 | ||
979 | .macro tramp_ventry, regsize = 64 | |
980 | .align 7 | |
981 | 1: | |
982 | .if \regsize == 64 | |
983 | msr tpidrro_el0, x30 // Restored in kernel_ventry | |
984 | .endif | |
985 | tramp_map_kernel x30 | |
986 | ldr x30, =vectors | |
987 | prfm plil1strm, [x30, #(1b - tramp_vectors)] | |
988 | msr vbar_el1, x30 | |
989 | add x30, x30, #(1b - tramp_vectors) | |
990 | isb | |
991 | br x30 | |
992 | .endm | |
993 | ||
994 | .macro tramp_exit, regsize = 64 | |
995 | adr x30, tramp_vectors | |
996 | msr vbar_el1, x30 | |
997 | tramp_unmap_kernel x30 | |
998 | .if \regsize == 64 | |
999 | mrs x30, far_el1 | |
1000 | .endif | |
1001 | eret | |
1002 | .endm | |
1003 | ||
1004 | .align 11 | |
1005 | ENTRY(tramp_vectors) | |
1006 | .space 0x400 | |
1007 | ||
1008 | tramp_ventry | |
1009 | tramp_ventry | |
1010 | tramp_ventry | |
1011 | tramp_ventry | |
1012 | ||
1013 | tramp_ventry 32 | |
1014 | tramp_ventry 32 | |
1015 | tramp_ventry 32 | |
1016 | tramp_ventry 32 | |
1017 | END(tramp_vectors) | |
1018 | ||
1019 | ENTRY(tramp_exit_native) | |
1020 | tramp_exit | |
1021 | END(tramp_exit_native) | |
1022 | ||
1023 | ENTRY(tramp_exit_compat) | |
1024 | tramp_exit 32 | |
1025 | END(tramp_exit_compat) | |
1026 | ||
1027 | .ltorg | |
1028 | .popsection // .entry.tramp.text | |
1029 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ | |
1030 | ||
60ffc30d CM |
1031 | /* |
1032 | * Special system call wrappers. | |
1033 | */ | |
60ffc30d CM |
1034 | ENTRY(sys_rt_sigreturn_wrapper) |
1035 | mov x0, sp | |
1036 | b sys_rt_sigreturn | |
1037 | ENDPROC(sys_rt_sigreturn_wrapper) | |
0c478199 MR |
1038 | |
1039 | /* | |
1040 | * Register switch for AArch64. The callee-saved registers need to be saved | |
1041 | * and restored. On entry: | |
1042 | * x0 = previous task_struct (must be preserved across the switch) | |
1043 | * x1 = next task_struct | |
1044 | * Previous and next are guaranteed not to be the same. | |
1045 | * | |
1046 | */ | |
1047 | ENTRY(cpu_switch_to) | |
1048 | mov x10, #THREAD_CPU_CONTEXT | |
1049 | add x8, x0, x10 | |
1050 | mov x9, sp | |
1051 | stp x19, x20, [x8], #16 // store callee-saved registers | |
1052 | stp x21, x22, [x8], #16 | |
1053 | stp x23, x24, [x8], #16 | |
1054 | stp x25, x26, [x8], #16 | |
1055 | stp x27, x28, [x8], #16 | |
1056 | stp x29, x9, [x8], #16 | |
1057 | str lr, [x8] | |
1058 | add x8, x1, x10 | |
1059 | ldp x19, x20, [x8], #16 // restore callee-saved registers | |
1060 | ldp x21, x22, [x8], #16 | |
1061 | ldp x23, x24, [x8], #16 | |
1062 | ldp x25, x26, [x8], #16 | |
1063 | ldp x27, x28, [x8], #16 | |
1064 | ldp x29, x9, [x8], #16 | |
1065 | ldr lr, [x8] | |
1066 | mov sp, x9 | |
1067 | msr sp_el0, x1 | |
1068 | ret | |
1069 | ENDPROC(cpu_switch_to) | |
1070 | NOKPROBE(cpu_switch_to) | |
1071 | ||
1072 | /* | |
1073 | * This is how we return from a fork. | |
1074 | */ | |
1075 | ENTRY(ret_from_fork) | |
1076 | bl schedule_tail | |
1077 | cbz x19, 1f // not a kernel thread | |
1078 | mov x0, x20 | |
1079 | blr x19 | |
1080 | 1: get_thread_info tsk | |
1081 | b ret_to_user | |
1082 | ENDPROC(ret_from_fork) | |
1083 | NOKPROBE(ret_from_fork) |