[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / kernel / process.c

/*
 * Based on arch/arm/kernel/process.c
 *
 * Original Copyright (C) 1995  Linus Torvalds
 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <stdarg.h>

#include <linux/compat.h>
#include <linux/export.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/user.h>
#include <linux/delay.h>
#include <linux/reboot.h>
#include <linux/interrupt.h>
#include <linux/kallsyms.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/elfcore.h>
#include <linux/pm.h>
#include <linux/tick.h>
#include <linux/utsname.h>
#include <linux/uaccess.h>
#include <linux/random.h>
#include <linux/hw_breakpoint.h>
#include <linux/personality.h>
#include <linux/notifier.h>

#include <asm/compat.h>
#include <asm/cacheflush.h>
#include <asm/fpsimd.h>
#include <asm/mmu_context.h>
#include <asm/processor.h>
#include <asm/stacktrace.h>

#ifdef CONFIG_CC_STACKPROTECTOR
#include <linux/stackprotector.h>
unsigned long __stack_chk_guard __read_mostly;
EXPORT_SYMBOL(__stack_chk_guard);
#endif

void soft_restart(unsigned long addr)
{
	setup_mm_for_reboot();
	cpu_soft_restart(virt_to_phys(cpu_reset), addr);
	/* Should never get here */
	BUG();
}

/*
 * Function pointers to optional machine specific functions
 */
void (*pm_power_off)(void);
EXPORT_SYMBOL_GPL(pm_power_off);

void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);

/*
 * This is our default idle handler.
 */
void arch_cpu_idle(void)
{
	/*
	 * This should do all the clock switching and wait for interrupt
	 * tricks
	 */
	cpu_do_idle();
	local_irq_enable();
}

#ifdef CONFIG_HOTPLUG_CPU
void arch_cpu_idle_dead(void)
{
       cpu_die();
}
#endif

/*
 * Called by kexec, immediately prior to machine_kexec().
 *
 * This must completely disable all secondary CPUs; simply causing those CPUs
 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
 * kexec'd kernel to use any and all RAM as it sees fit, without having to
 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
 * functionality embodied in disable_nonboot_cpus() to achieve this.
 */
void machine_shutdown(void)
{
	disable_nonboot_cpus();
}

/*
 * Halting simply requires that the secondary CPUs stop performing any
 * activity (executing tasks, handling interrupts). smp_send_stop()
 * achieves this.
 */
void machine_halt(void)
{
	local_irq_disable();
	smp_send_stop();
	while (1);
}

/*
 * Power-off simply requires that the secondary CPUs stop performing any
 * activity (executing tasks, handling interrupts). smp_send_stop()
 * achieves this. When the system power is turned off, it will take all CPUs
 * with it.
 */
void machine_power_off(void)
{
	local_irq_disable();
	smp_send_stop();
	if (pm_power_off)
		pm_power_off();
}

/*
 * Restart requires that the secondary CPUs stop performing any activity
 * while the primary CPU resets the system. Systems with a single CPU can
 * use soft_restart() as their machine descriptor's .restart hook, since that
 * will cause the only available CPU to reset. Systems with multiple CPUs must
 * provide a HW restart implementation, to ensure that all CPUs reset at once.
 * This is required so that any code running after reset on the primary CPU
 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
 * executing pre-reset code, and using RAM that the primary CPU's code wishes
 * to use. Implementing such co-ordination would be essentially impossible.
 */
void machine_restart(char *cmd)
{
	/* Disable interrupts first */
	local_irq_disable();
	smp_send_stop();

	/* Now call the architecture specific reboot code. */
	if (arm_pm_restart)
		arm_pm_restart(reboot_mode, cmd);
	else
		do_kernel_restart(cmd);

	/*
	 * Whoops - the architecture was unable to reboot.
	 */
	printk("Reboot failed -- System halted\n");
	while (1);
}

void __show_regs(struct pt_regs *regs)
{
	int i, top_reg;
	u64 lr, sp;

	if (compat_user_mode(regs)) {
		lr = regs->compat_lr;
		sp = regs->compat_sp;
		top_reg = 12;
	} else {
		lr = regs->regs[30];
		sp = regs->sp;
		top_reg = 29;
	}

	show_regs_print_info(KERN_DEFAULT);
	print_symbol("PC is at %s\n", instruction_pointer(regs));
	print_symbol("LR is at %s\n", lr);
	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
	       regs->pc, lr, regs->pstate);
	printk("sp : %016llx\n", sp);
	for (i = top_reg; i >= 0; i--) {
		printk("x%-2d: %016llx ", i, regs->regs[i]);
		if (i % 2 == 0)
			printk("\n");
	}
	printk("\n");
}

void show_regs(struct pt_regs * regs)
{
	printk("\n");
	__show_regs(regs);
}

/*
 * Free current thread data structures etc..
 */
void exit_thread(void)
{
}

static void tls_thread_flush(void)
{
	asm ("msr tpidr_el0, xzr");

	if (is_compat_task()) {
		current->thread.tp_value = 0;

		/*
		 * We need to ensure ordering between the shadow state and the
		 * hardware state, so that we don't corrupt the hardware state
		 * with a stale shadow state during context switch.
		 */
		barrier();
		asm ("msr tpidrro_el0, xzr");
	}
}

void flush_thread(void)
{
	fpsimd_flush_thread();
	tls_thread_flush();
	flush_ptrace_hw_breakpoint(current);
}

void release_thread(struct task_struct *dead_task)
{
}

int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	fpsimd_preserve_current_state();
	*dst = *src;
	return 0;
}

asmlinkage void ret_from_fork(void) asm("ret_from_fork");

int copy_thread(unsigned long clone_flags, unsigned long stack_start,
		unsigned long stk_sz, struct task_struct *p)
{
	struct pt_regs *childregs = task_pt_regs(p);
	unsigned long tls = p->thread.tp_value;

	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));

	if (likely(!(p->flags & PF_KTHREAD))) {
		*childregs = *current_pt_regs();
		childregs->regs[0] = 0;
		if (is_compat_thread(task_thread_info(p))) {
			if (stack_start)
				childregs->compat_sp = stack_start;
		} else {
			/*
			 * Read the current TLS pointer from tpidr_el0 as it may be
			 * out-of-sync with the saved value.
			 */
			asm("mrs %0, tpidr_el0" : "=r" (tls));
			if (stack_start) {
				/* 16-byte aligned stack mandatory on AArch64 */
				if (stack_start & 15)
					return -EINVAL;
				childregs->sp = stack_start;
			}
		}
		/*
		 * If a TLS pointer was passed to clone (4th argument), use it
		 * for the new thread.
		 */
		if (clone_flags & CLONE_SETTLS)
			tls = childregs->regs[3];
	} else {
		memset(childregs, 0, sizeof(struct pt_regs));
		childregs->pstate = PSR_MODE_EL1h;
		p->thread.cpu_context.x19 = stack_start;
		p->thread.cpu_context.x20 = stk_sz;
	}
	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
	p->thread.cpu_context.sp = (unsigned long)childregs;
	p->thread.tp_value = tls;

	ptrace_hw_copy_thread(p);

	return 0;
}

static void tls_thread_switch(struct task_struct *next)
{
	unsigned long tpidr, tpidrro;

	if (!is_compat_task()) {
		asm("mrs %0, tpidr_el0" : "=r" (tpidr));
		current->thread.tp_value = tpidr;
	}

	if (is_compat_thread(task_thread_info(next))) {
		tpidr = 0;
		tpidrro = next->thread.tp_value;
	} else {
		tpidr = next->thread.tp_value;
		tpidrro = 0;
	}

	asm(
	"	msr	tpidr_el0, %0\n"
	"	msr	tpidrro_el0, %1"
	: : "r" (tpidr), "r" (tpidrro));
}

/*
 * Thread switching.
 */
struct task_struct *__switch_to(struct task_struct *prev,
				struct task_struct *next)
{
	struct task_struct *last;

	fpsimd_thread_switch(next);
	tls_thread_switch(next);
	hw_breakpoint_thread_switch(next);
	contextidr_thread_switch(next);

	/*
	 * Complete any pending TLB or cache maintenance on this CPU in case
	 * the thread migrates to a different CPU.
	 */
	dsb(ish);

	/* the actual thread switch */
	last = cpu_switch_to(prev, next);

	return last;
}

unsigned long get_wchan(struct task_struct *p)
{
	struct stackframe frame;
	unsigned long stack_page;
	int count = 0;
	if (!p || p == current || p->state == TASK_RUNNING)
		return 0;

	frame.fp = thread_saved_fp(p);
	frame.sp = thread_saved_sp(p);
	frame.pc = thread_saved_pc(p);
	stack_page = (unsigned long)task_stack_page(p);
	do {
		if (frame.sp < stack_page ||
		    frame.sp >= stack_page + THREAD_SIZE ||
		    unwind_frame(&frame))
			return 0;
		if (!in_sched_functions(frame.pc))
			return frame.pc;
	} while (count ++ < 16);
	return 0;
}

unsigned long arch_align_stack(unsigned long sp)
{
	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
		sp -= get_random_int() & ~PAGE_MASK;
	return sp & ~0xf;
}

static unsigned long randomize_base(unsigned long base)
{
	unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
	return randomize_range(base, range_end, 0) ? : base;
}

unsigned long arch_randomize_brk(struct mm_struct *mm)
{
	return randomize_base(mm->brk);
}
Commit	Line	Data
b3901d54 CM	1	/*
	2	* Based on arch/arm/kernel/process.c
	3	*
	4	* Original Copyright (C) 1995 Linus Torvalds
	5	* Copyright (C) 1996-2000 Russell King - Converted to ARM.
	6	* Copyright (C) 2012 ARM Ltd.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <stdarg.h>
	22
fd92d4a5	23	#include <linux/compat.h>
b3901d54 CM	24	#include <linux/export.h>
	25	#include <linux/sched.h>
	26	#include <linux/kernel.h>
	27	#include <linux/mm.h>
	28	#include <linux/stddef.h>
	29	#include <linux/unistd.h>
	30	#include <linux/user.h>
	31	#include <linux/delay.h>
	32	#include <linux/reboot.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/kallsyms.h>
	35	#include <linux/init.h>
	36	#include <linux/cpu.h>
	37	#include <linux/elfcore.h>
	38	#include <linux/pm.h>
	39	#include <linux/tick.h>
	40	#include <linux/utsname.h>
	41	#include <linux/uaccess.h>
	42	#include <linux/random.h>
	43	#include <linux/hw_breakpoint.h>
	44	#include <linux/personality.h>
	45	#include <linux/notifier.h>
	46
	47	#include <asm/compat.h>
	48	#include <asm/cacheflush.h>
ec45d1cf WD	49	#include <asm/fpsimd.h>
ec45d1cf WD	50	#include <asm/mmu_context.h>
b3901d54 CM	51	#include <asm/processor.h>
b3901d54 CM	52	#include <asm/stacktrace.h>
b3901d54	53
c0c264ae LA	54	#ifdef CONFIG_CC_STACKPROTECTOR
	55	#include <linux/stackprotector.h>
	56	unsigned long __stack_chk_guard __read_mostly;
	57	EXPORT_SYMBOL(__stack_chk_guard);
	58	#endif
	59
b3901d54 CM	60	void soft_restart(unsigned long addr)
b3901d54 CM	61	{
5e051531 AC	62	setup_mm_for_reboot();
5e051531 AC	63	cpu_soft_restart(virt_to_phys(cpu_reset), addr);
09024aa6 GL	64	/* Should never get here */
09024aa6 GL	65	BUG();
b3901d54 CM	66	}
	67
	68	/*
	69	* Function pointers to optional machine specific functions
	70	*/
	71	void (*pm_power_off)(void);
	72	EXPORT_SYMBOL_GPL(pm_power_off);
	73
b0946fc8	74	void (arm_pm_restart)(enum reboot_mode reboot_mode, const char cmd);
b3901d54	75
b3901d54 CM	76	/*
	77	* This is our default idle handler.
	78	*/
0087298f	79	void arch_cpu_idle(void)
b3901d54 CM	80	{
	81	/*
	82	* This should do all the clock switching and wait for interrupt
	83	* tricks
	84	*/
6990566b NP	85	cpu_do_idle();
6990566b NP	86	local_irq_enable();
b3901d54 CM	87	}
b3901d54 CM	88
9327e2c6 MR	89	#ifdef CONFIG_HOTPLUG_CPU
	90	void arch_cpu_idle_dead(void)
	91	{
	92	cpu_die();
	93	}
	94	#endif
	95
90f51a09 AK	96	/*
	97	* Called by kexec, immediately prior to machine_kexec().
	98	*
	99	* This must completely disable all secondary CPUs; simply causing those CPUs
	100	* to execute e.g. a RAM-based pin loop is not sufficient. This allows the
	101	* kexec'd kernel to use any and all RAM as it sees fit, without having to
	102	* avoid any code or data used by any SW CPU pin loop. The CPU hotplug
	103	* functionality embodied in disable_nonboot_cpus() to achieve this.
	104	*/
b3901d54 CM	105	void machine_shutdown(void)
b3901d54 CM	106	{
90f51a09	107	disable_nonboot_cpus();
b3901d54 CM	108	}
b3901d54 CM	109
90f51a09 AK	110	/*
	111	* Halting simply requires that the secondary CPUs stop performing any
	112	* activity (executing tasks, handling interrupts). smp_send_stop()
	113	* achieves this.
	114	*/
b3901d54 CM	115	void machine_halt(void)
b3901d54 CM	116	{
b9acc49e	117	local_irq_disable();
90f51a09	118	smp_send_stop();
b3901d54 CM	119	while (1);
	120	}
	121
90f51a09 AK	122	/*
	123	* Power-off simply requires that the secondary CPUs stop performing any
	124	* activity (executing tasks, handling interrupts). smp_send_stop()
	125	* achieves this. When the system power is turned off, it will take all CPUs
	126	* with it.
	127	*/
b3901d54 CM	128	void machine_power_off(void)
b3901d54 CM	129	{
b9acc49e	130	local_irq_disable();
90f51a09	131	smp_send_stop();
b3901d54 CM	132	if (pm_power_off)
	133	pm_power_off();
	134	}
	135
90f51a09 AK	136	/*
	137	* Restart requires that the secondary CPUs stop performing any activity
	138	* while the primary CPU resets the system. Systems with a single CPU can
	139	* use soft_restart() as their machine descriptor's .restart hook, since that
	140	* will cause the only available CPU to reset. Systems with multiple CPUs must
	141	* provide a HW restart implementation, to ensure that all CPUs reset at once.
	142	* This is required so that any code running after reset on the primary CPU
	143	* doesn't have to co-ordinate with other CPUs to ensure they aren't still
	144	* executing pre-reset code, and using RAM that the primary CPU's code wishes
	145	* to use. Implementing such co-ordination would be essentially impossible.
	146	*/
b3901d54 CM	147	void machine_restart(char *cmd)
b3901d54 CM	148	{
b3901d54 CM	149	/* Disable interrupts first */
b3901d54 CM	150	local_irq_disable();
b9acc49e	151	smp_send_stop();
b3901d54 CM	152
b3901d54 CM	153	/* Now call the architecture specific reboot code. */
aa1e8ec1	154	if (arm_pm_restart)
ff701306	155	arm_pm_restart(reboot_mode, cmd);
1c7ffc32 GR	156	else
1c7ffc32 GR	157	do_kernel_restart(cmd);
b3901d54 CM	158
	159	/*
	160	* Whoops - the architecture was unable to reboot.
	161	*/
	162	printk("Reboot failed -- System halted\n");
	163	while (1);
	164	}
	165
	166	void __show_regs(struct pt_regs *regs)
	167	{
6ca68e80 CM	168	int i, top_reg;
	169	u64 lr, sp;
	170
	171	if (compat_user_mode(regs)) {
	172	lr = regs->compat_lr;
	173	sp = regs->compat_sp;
	174	top_reg = 12;
	175	} else {
	176	lr = regs->regs[30];
	177	sp = regs->sp;
	178	top_reg = 29;
	179	}
b3901d54	180
a43cb95d	181	show_regs_print_info(KERN_DEFAULT);
b3901d54	182	print_symbol("PC is at %s\n", instruction_pointer(regs));
6ca68e80	183	print_symbol("LR is at %s\n", lr);
b3901d54	184	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
6ca68e80 CM	185	regs->pc, lr, regs->pstate);
	186	printk("sp : %016llx\n", sp);
	187	for (i = top_reg; i >= 0; i--) {
b3901d54 CM	188	printk("x%-2d: %016llx ", i, regs->regs[i]);
	189	if (i % 2 == 0)
	190	printk("\n");
	191	}
	192	printk("\n");
	193	}
	194
	195	void show_regs(struct pt_regs * regs)
	196	{
	197	printk("\n");
b3901d54 CM	198	__show_regs(regs);
	199	}
	200
	201	/*
	202	* Free current thread data structures etc..
	203	*/
	204	void exit_thread(void)
	205	{
	206	}
	207
eb35bdd7 WD	208	static void tls_thread_flush(void)
	209	{
	210	asm ("msr tpidr_el0, xzr");
	211
	212	if (is_compat_task()) {
	213	current->thread.tp_value = 0;
	214
	215	/*
	216	* We need to ensure ordering between the shadow state and the
	217	* hardware state, so that we don't corrupt the hardware state
	218	* with a stale shadow state during context switch.
	219	*/
	220	barrier();
	221	asm ("msr tpidrro_el0, xzr");
	222	}
	223	}
	224
b3901d54 CM	225	void flush_thread(void)
	226	{
	227	fpsimd_flush_thread();
eb35bdd7	228	tls_thread_flush();
b3901d54 CM	229	flush_ptrace_hw_breakpoint(current);
	230	}
	231
	232	void release_thread(struct task_struct *dead_task)
	233	{
	234	}
	235
	236	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
	237	{
c51f9269	238	fpsimd_preserve_current_state();
b3901d54 CM	239	dst = src;
	240	return 0;
	241	}
	242
	243	asmlinkage void ret_from_fork(void) asm("ret_from_fork");
	244
	245	int copy_thread(unsigned long clone_flags, unsigned long stack_start,
afa86fc4	246	unsigned long stk_sz, struct task_struct *p)
b3901d54 CM	247	{
	248	struct pt_regs *childregs = task_pt_regs(p);
	249	unsigned long tls = p->thread.tp_value;
	250
c34501d2	251	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
b3901d54	252
9ac08002 AV	253	if (likely(!(p->flags & PF_KTHREAD))) {
9ac08002 AV	254	childregs = current_pt_regs();
c34501d2 CM	255	childregs->regs[0] = 0;
c34501d2 CM	256	if (is_compat_thread(task_thread_info(p))) {
e0fd18ce AV	257	if (stack_start)
e0fd18ce AV	258	childregs->compat_sp = stack_start;
c34501d2 CM	259	} else {
	260	/*
	261	* Read the current TLS pointer from tpidr_el0 as it may be
	262	* out-of-sync with the saved value.
	263	*/
	264	asm("mrs %0, tpidr_el0" : "=r" (tls));
e0fd18ce AV	265	if (stack_start) {
	266	/* 16-byte aligned stack mandatory on AArch64 */
	267	if (stack_start & 15)
	268	return -EINVAL;
	269	childregs->sp = stack_start;
	270	}
c34501d2	271	}
b3901d54	272	/*
c34501d2 CM	273	* If a TLS pointer was passed to clone (4th argument), use it
c34501d2 CM	274	* for the new thread.
b3901d54	275	*/
c34501d2	276	if (clone_flags & CLONE_SETTLS)
9ac08002	277	tls = childregs->regs[3];
c34501d2 CM	278	} else {
	279	memset(childregs, 0, sizeof(struct pt_regs));
	280	childregs->pstate = PSR_MODE_EL1h;
	281	p->thread.cpu_context.x19 = stack_start;
	282	p->thread.cpu_context.x20 = stk_sz;
b3901d54	283	}
b3901d54	284	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
c34501d2	285	p->thread.cpu_context.sp = (unsigned long)childregs;
b3901d54 CM	286	p->thread.tp_value = tls;
	287
	288	ptrace_hw_copy_thread(p);
	289
	290	return 0;
	291	}
	292
	293	static void tls_thread_switch(struct task_struct *next)
	294	{
	295	unsigned long tpidr, tpidrro;
	296
	297	if (!is_compat_task()) {
	298	asm("mrs %0, tpidr_el0" : "=r" (tpidr));
	299	current->thread.tp_value = tpidr;
	300	}
	301
	302	if (is_compat_thread(task_thread_info(next))) {
	303	tpidr = 0;
	304	tpidrro = next->thread.tp_value;
	305	} else {
	306	tpidr = next->thread.tp_value;
	307	tpidrro = 0;
	308	}
	309
	310	asm(
	311	" msr tpidr_el0, %0\n"
	312	" msr tpidrro_el0, %1"
	313	: : "r" (tpidr), "r" (tpidrro));
	314	}
	315
	316	/*
	317	* Thread switching.
	318	*/
	319	struct task_struct __switch_to(struct task_struct prev,
	320	struct task_struct *next)
	321	{
	322	struct task_struct *last;
	323
	324	fpsimd_thread_switch(next);
	325	tls_thread_switch(next);
	326	hw_breakpoint_thread_switch(next);
3325732f	327	contextidr_thread_switch(next);
b3901d54	328
5108c67c CM	329	/*
	330	* Complete any pending TLB or cache maintenance on this CPU in case
	331	* the thread migrates to a different CPU.
	332	*/
98f7685e	333	dsb(ish);
b3901d54 CM	334
	335	/* the actual thread switch */
	336	last = cpu_switch_to(prev, next);
	337
	338	return last;
	339	}
	340
b3901d54 CM	341	unsigned long get_wchan(struct task_struct *p)
	342	{
	343	struct stackframe frame;
408c3658	344	unsigned long stack_page;
b3901d54 CM	345	int count = 0;
	346	if (!p \|\| p == current \|\| p->state == TASK_RUNNING)
	347	return 0;
	348
	349	frame.fp = thread_saved_fp(p);
	350	frame.sp = thread_saved_sp(p);
	351	frame.pc = thread_saved_pc(p);
408c3658	352	stack_page = (unsigned long)task_stack_page(p);
b3901d54	353	do {
408c3658 KK	354	if (frame.sp < stack_page \|\|
	355	frame.sp >= stack_page + THREAD_SIZE \|\|
	356	unwind_frame(&frame))
b3901d54 CM	357	return 0;
	358	if (!in_sched_functions(frame.pc))
	359	return frame.pc;
	360	} while (count ++ < 16);
	361	return 0;
	362	}
	363
	364	unsigned long arch_align_stack(unsigned long sp)
	365	{
	366	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
	367	sp -= get_random_int() & ~PAGE_MASK;
	368	return sp & ~0xf;
	369	}
	370
	371	static unsigned long randomize_base(unsigned long base)
	372	{
	373	unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
	374	return randomize_range(base, range_end, 0) ? : base;
	375	}
	376
	377	unsigned long arch_randomize_brk(struct mm_struct *mm)
	378	{
	379	return randomize_base(mm->brk);
	380	}