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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
08e875c1 CM |
2 | /* |
3 | * SMP initialisation and IPI support | |
4 | * Based on arch/arm/kernel/smp.c | |
5 | * | |
6 | * Copyright (C) 2012 ARM Ltd. | |
08e875c1 CM |
7 | */ |
8 | ||
0f078336 | 9 | #include <linux/acpi.h> |
f5df2696 | 10 | #include <linux/arm_sdei.h> |
08e875c1 CM |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
68e21be2 | 14 | #include <linux/sched/mm.h> |
ef8bd77f | 15 | #include <linux/sched/hotplug.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
08e875c1 CM |
17 | #include <linux/interrupt.h> |
18 | #include <linux/cache.h> | |
19 | #include <linux/profile.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/cpu.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/seq_file.h> | |
26 | #include <linux/irq.h> | |
e7932188 | 27 | #include <linux/irqchip/arm-gic-v3.h> |
08e875c1 CM |
28 | #include <linux/percpu.h> |
29 | #include <linux/clockchips.h> | |
30 | #include <linux/completion.h> | |
31 | #include <linux/of.h> | |
eb631bb5 | 32 | #include <linux/irq_work.h> |
78fd584c | 33 | #include <linux/kexec.h> |
08e875c1 | 34 | |
e039ee4e | 35 | #include <asm/alternative.h> |
08e875c1 CM |
36 | #include <asm/atomic.h> |
37 | #include <asm/cacheflush.h> | |
df857416 | 38 | #include <asm/cpu.h> |
08e875c1 | 39 | #include <asm/cputype.h> |
cd1aebf5 | 40 | #include <asm/cpu_ops.h> |
0fbeb318 | 41 | #include <asm/daifflags.h> |
08e875c1 | 42 | #include <asm/mmu_context.h> |
1a2db300 | 43 | #include <asm/numa.h> |
08e875c1 CM |
44 | #include <asm/pgtable.h> |
45 | #include <asm/pgalloc.h> | |
46 | #include <asm/processor.h> | |
4c7aa002 | 47 | #include <asm/smp_plat.h> |
08e875c1 CM |
48 | #include <asm/sections.h> |
49 | #include <asm/tlbflush.h> | |
50 | #include <asm/ptrace.h> | |
377bcff9 | 51 | #include <asm/virt.h> |
08e875c1 | 52 | |
45ed695a NP |
53 | #define CREATE_TRACE_POINTS |
54 | #include <trace/events/ipi.h> | |
55 | ||
57c82954 MR |
56 | DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number); |
57 | EXPORT_PER_CPU_SYMBOL(cpu_number); | |
58 | ||
08e875c1 CM |
59 | /* |
60 | * as from 2.5, kernels no longer have an init_tasks structure | |
61 | * so we need some other way of telling a new secondary core | |
62 | * where to place its SVC stack | |
63 | */ | |
64 | struct secondary_data secondary_data; | |
bb905274 SP |
65 | /* Number of CPUs which aren't online, but looping in kernel text. */ |
66 | int cpus_stuck_in_kernel; | |
08e875c1 CM |
67 | |
68 | enum ipi_msg_type { | |
69 | IPI_RESCHEDULE, | |
70 | IPI_CALL_FUNC, | |
08e875c1 | 71 | IPI_CPU_STOP, |
78fd584c | 72 | IPI_CPU_CRASH_STOP, |
1f85008e | 73 | IPI_TIMER, |
eb631bb5 | 74 | IPI_IRQ_WORK, |
5e89c55e | 75 | IPI_WAKEUP |
08e875c1 CM |
76 | }; |
77 | ||
bb905274 SP |
78 | #ifdef CONFIG_HOTPLUG_CPU |
79 | static int op_cpu_kill(unsigned int cpu); | |
80 | #else | |
81 | static inline int op_cpu_kill(unsigned int cpu) | |
82 | { | |
83 | return -ENOSYS; | |
84 | } | |
85 | #endif | |
86 | ||
87 | ||
08e875c1 CM |
88 | /* |
89 | * Boot a secondary CPU, and assign it the specified idle task. | |
90 | * This also gives us the initial stack to use for this CPU. | |
91 | */ | |
b8c6453a | 92 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 93 | { |
652af899 MR |
94 | if (cpu_ops[cpu]->cpu_boot) |
95 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 96 | |
652af899 | 97 | return -EOPNOTSUPP; |
08e875c1 CM |
98 | } |
99 | ||
100 | static DECLARE_COMPLETION(cpu_running); | |
101 | ||
b8c6453a | 102 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
103 | { |
104 | int ret; | |
bb905274 | 105 | long status; |
08e875c1 CM |
106 | |
107 | /* | |
108 | * We need to tell the secondary core where to find its stack and the | |
109 | * page tables. | |
110 | */ | |
c02433dd | 111 | secondary_data.task = idle; |
34be98f4 | 112 | secondary_data.stack = task_stack_page(idle) + THREAD_SIZE; |
bb905274 | 113 | update_cpu_boot_status(CPU_MMU_OFF); |
08e875c1 CM |
114 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); |
115 | ||
116 | /* | |
117 | * Now bring the CPU into our world. | |
118 | */ | |
119 | ret = boot_secondary(cpu, idle); | |
120 | if (ret == 0) { | |
121 | /* | |
122 | * CPU was successfully started, wait for it to come online or | |
123 | * time out. | |
124 | */ | |
125 | wait_for_completion_timeout(&cpu_running, | |
126 | msecs_to_jiffies(1000)); | |
127 | ||
128 | if (!cpu_online(cpu)) { | |
129 | pr_crit("CPU%u: failed to come online\n", cpu); | |
130 | ret = -EIO; | |
131 | } | |
132 | } else { | |
133 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
f357b3a7 | 134 | return ret; |
08e875c1 CM |
135 | } |
136 | ||
c02433dd | 137 | secondary_data.task = NULL; |
08e875c1 | 138 | secondary_data.stack = NULL; |
bb905274 SP |
139 | status = READ_ONCE(secondary_data.status); |
140 | if (ret && status) { | |
141 | ||
142 | if (status == CPU_MMU_OFF) | |
143 | status = READ_ONCE(__early_cpu_boot_status); | |
144 | ||
66f16a24 | 145 | switch (status & CPU_BOOT_STATUS_MASK) { |
bb905274 SP |
146 | default: |
147 | pr_err("CPU%u: failed in unknown state : 0x%lx\n", | |
148 | cpu, status); | |
149 | break; | |
150 | case CPU_KILL_ME: | |
151 | if (!op_cpu_kill(cpu)) { | |
152 | pr_crit("CPU%u: died during early boot\n", cpu); | |
153 | break; | |
154 | } | |
155 | /* Fall through */ | |
156 | pr_crit("CPU%u: may not have shut down cleanly\n", cpu); | |
157 | case CPU_STUCK_IN_KERNEL: | |
158 | pr_crit("CPU%u: is stuck in kernel\n", cpu); | |
66f16a24 WD |
159 | if (status & CPU_STUCK_REASON_52_BIT_VA) |
160 | pr_crit("CPU%u: does not support 52-bit VAs\n", cpu); | |
161 | if (status & CPU_STUCK_REASON_NO_GRAN) | |
162 | pr_crit("CPU%u: does not support %luK granule \n", cpu, PAGE_SIZE / SZ_1K); | |
bb905274 SP |
163 | cpus_stuck_in_kernel++; |
164 | break; | |
165 | case CPU_PANIC_KERNEL: | |
166 | panic("CPU%u detected unsupported configuration\n", cpu); | |
167 | } | |
168 | } | |
08e875c1 CM |
169 | |
170 | return ret; | |
171 | } | |
172 | ||
e7932188 JT |
173 | static void init_gic_priority_masking(void) |
174 | { | |
175 | u32 cpuflags; | |
176 | ||
177 | if (WARN_ON(!gic_enable_sre())) | |
178 | return; | |
179 | ||
180 | cpuflags = read_sysreg(daif); | |
181 | ||
182 | WARN_ON(!(cpuflags & PSR_I_BIT)); | |
183 | ||
184 | gic_write_pmr(GIC_PRIO_IRQOFF); | |
185 | ||
186 | /* We can only unmask PSR.I if we can take aborts */ | |
187 | if (!(cpuflags & PSR_A_BIT)) | |
188 | write_sysreg(cpuflags & ~PSR_I_BIT, daif); | |
189 | } | |
190 | ||
08e875c1 CM |
191 | /* |
192 | * This is the secondary CPU boot entry. We're using this CPUs | |
193 | * idle thread stack, but a set of temporary page tables. | |
194 | */ | |
b154886f | 195 | asmlinkage notrace void secondary_start_kernel(void) |
08e875c1 | 196 | { |
ccaac162 | 197 | u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; |
08e875c1 | 198 | struct mm_struct *mm = &init_mm; |
580efaa7 MR |
199 | unsigned int cpu; |
200 | ||
201 | cpu = task_cpu(current); | |
202 | set_my_cpu_offset(per_cpu_offset(cpu)); | |
08e875c1 | 203 | |
08e875c1 CM |
204 | /* |
205 | * All kernel threads share the same mm context; grab a | |
206 | * reference and switch to it. | |
207 | */ | |
f1f10076 | 208 | mmgrab(mm); |
08e875c1 | 209 | current->active_mm = mm; |
08e875c1 CM |
210 | |
211 | /* | |
212 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
213 | * point to zero page to avoid speculatively fetching new entries. | |
214 | */ | |
9e8e865b | 215 | cpu_uninstall_idmap(); |
08e875c1 | 216 | |
e7932188 JT |
217 | if (system_uses_irq_prio_masking()) |
218 | init_gic_priority_masking(); | |
219 | ||
08e875c1 CM |
220 | preempt_disable(); |
221 | trace_hardirqs_off(); | |
222 | ||
dbb4e152 SP |
223 | /* |
224 | * If the system has established the capabilities, make sure | |
225 | * this CPU ticks all of those. If it doesn't, the CPU will | |
226 | * fail to come online. | |
227 | */ | |
c47a1900 | 228 | check_local_cpu_capabilities(); |
dbb4e152 | 229 | |
652af899 MR |
230 | if (cpu_ops[cpu]->cpu_postboot) |
231 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 232 | |
df857416 MR |
233 | /* |
234 | * Log the CPU info before it is marked online and might get read. | |
235 | */ | |
236 | cpuinfo_store_cpu(); | |
237 | ||
7ade67b5 MZ |
238 | /* |
239 | * Enable GIC and timers. | |
240 | */ | |
241 | notify_cpu_starting(cpu); | |
242 | ||
c18df0ad | 243 | store_cpu_topology(cpu); |
97fd6016 | 244 | numa_add_cpu(cpu); |
f6e763b9 | 245 | |
08e875c1 CM |
246 | /* |
247 | * OK, now it's safe to let the boot CPU continue. Wait for | |
248 | * the CPU migration code to notice that the CPU is online | |
249 | * before we continue. | |
250 | */ | |
ccaac162 MR |
251 | pr_info("CPU%u: Booted secondary processor 0x%010lx [0x%08x]\n", |
252 | cpu, (unsigned long)mpidr, | |
253 | read_cpuid_id()); | |
bb905274 | 254 | update_cpu_boot_status(CPU_BOOT_SUCCESS); |
08e875c1 | 255 | set_cpu_online(cpu, true); |
b3770b32 | 256 | complete(&cpu_running); |
08e875c1 | 257 | |
41bd5b5d | 258 | local_daif_restore(DAIF_PROCCTX); |
53ae3acd | 259 | |
08e875c1 CM |
260 | /* |
261 | * OK, it's off to the idle thread for us | |
262 | */ | |
fc6d73d6 | 263 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
08e875c1 CM |
264 | } |
265 | ||
9327e2c6 MR |
266 | #ifdef CONFIG_HOTPLUG_CPU |
267 | static int op_cpu_disable(unsigned int cpu) | |
268 | { | |
269 | /* | |
270 | * If we don't have a cpu_die method, abort before we reach the point | |
271 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
272 | */ | |
273 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
274 | return -EOPNOTSUPP; | |
275 | ||
276 | /* | |
277 | * We may need to abort a hot unplug for some other mechanism-specific | |
278 | * reason. | |
279 | */ | |
280 | if (cpu_ops[cpu]->cpu_disable) | |
281 | return cpu_ops[cpu]->cpu_disable(cpu); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | /* | |
287 | * __cpu_disable runs on the processor to be shutdown. | |
288 | */ | |
289 | int __cpu_disable(void) | |
290 | { | |
291 | unsigned int cpu = smp_processor_id(); | |
292 | int ret; | |
293 | ||
294 | ret = op_cpu_disable(cpu); | |
295 | if (ret) | |
296 | return ret; | |
297 | ||
7f9545aa SH |
298 | remove_cpu_topology(cpu); |
299 | numa_remove_cpu(cpu); | |
300 | ||
9327e2c6 MR |
301 | /* |
302 | * Take this CPU offline. Once we clear this, we can't return, | |
303 | * and we must not schedule until we're ready to give up the cpu. | |
304 | */ | |
305 | set_cpu_online(cpu, false); | |
306 | ||
307 | /* | |
308 | * OK - migrate IRQs away from this CPU | |
309 | */ | |
217d453d YY |
310 | irq_migrate_all_off_this_cpu(); |
311 | ||
9327e2c6 MR |
312 | return 0; |
313 | } | |
314 | ||
c814ca02 AC |
315 | static int op_cpu_kill(unsigned int cpu) |
316 | { | |
317 | /* | |
318 | * If we have no means of synchronising with the dying CPU, then assume | |
319 | * that it is really dead. We can only wait for an arbitrary length of | |
320 | * time and hope that it's dead, so let's skip the wait and just hope. | |
321 | */ | |
322 | if (!cpu_ops[cpu]->cpu_kill) | |
6b99c68c | 323 | return 0; |
c814ca02 AC |
324 | |
325 | return cpu_ops[cpu]->cpu_kill(cpu); | |
326 | } | |
327 | ||
9327e2c6 MR |
328 | /* |
329 | * called on the thread which is asking for a CPU to be shutdown - | |
330 | * waits until shutdown has completed, or it is timed out. | |
331 | */ | |
332 | void __cpu_die(unsigned int cpu) | |
333 | { | |
6b99c68c MR |
334 | int err; |
335 | ||
05981277 | 336 | if (!cpu_wait_death(cpu, 5)) { |
9327e2c6 MR |
337 | pr_crit("CPU%u: cpu didn't die\n", cpu); |
338 | return; | |
339 | } | |
340 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
341 | |
342 | /* | |
343 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
344 | * in-kernel synchronisation, try to get the firwmare to help us to | |
345 | * verify that it has really left the kernel before we consider | |
346 | * clobbering anything it might still be using. | |
347 | */ | |
6b99c68c MR |
348 | err = op_cpu_kill(cpu); |
349 | if (err) | |
350 | pr_warn("CPU%d may not have shut down cleanly: %d\n", | |
351 | cpu, err); | |
9327e2c6 MR |
352 | } |
353 | ||
354 | /* | |
355 | * Called from the idle thread for the CPU which has been shutdown. | |
356 | * | |
9327e2c6 MR |
357 | */ |
358 | void cpu_die(void) | |
359 | { | |
360 | unsigned int cpu = smp_processor_id(); | |
361 | ||
362 | idle_task_exit(); | |
363 | ||
0fbeb318 | 364 | local_daif_mask(); |
9327e2c6 MR |
365 | |
366 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
05981277 | 367 | (void)cpu_report_death(); |
9327e2c6 MR |
368 | |
369 | /* | |
370 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
371 | * mechanism must perform all required cache maintenance to ensure that | |
372 | * no dirty lines are lost in the process of shutting down the CPU. | |
373 | */ | |
374 | cpu_ops[cpu]->cpu_die(cpu); | |
375 | ||
376 | BUG(); | |
377 | } | |
378 | #endif | |
379 | ||
fce6361f SP |
380 | /* |
381 | * Kill the calling secondary CPU, early in bringup before it is turned | |
382 | * online. | |
383 | */ | |
384 | void cpu_die_early(void) | |
385 | { | |
386 | int cpu = smp_processor_id(); | |
387 | ||
388 | pr_crit("CPU%d: will not boot\n", cpu); | |
389 | ||
390 | /* Mark this CPU absent */ | |
391 | set_cpu_present(cpu, 0); | |
392 | ||
393 | #ifdef CONFIG_HOTPLUG_CPU | |
bb905274 | 394 | update_cpu_boot_status(CPU_KILL_ME); |
fce6361f SP |
395 | /* Check if we can park ourselves */ |
396 | if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) | |
397 | cpu_ops[cpu]->cpu_die(cpu); | |
398 | #endif | |
bb905274 | 399 | update_cpu_boot_status(CPU_STUCK_IN_KERNEL); |
fce6361f SP |
400 | |
401 | cpu_park_loop(); | |
402 | } | |
403 | ||
377bcff9 JR |
404 | static void __init hyp_mode_check(void) |
405 | { | |
406 | if (is_hyp_mode_available()) | |
407 | pr_info("CPU: All CPU(s) started at EL2\n"); | |
408 | else if (is_hyp_mode_mismatched()) | |
409 | WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, | |
410 | "CPU: CPUs started in inconsistent modes"); | |
411 | else | |
412 | pr_info("CPU: All CPU(s) started at EL1\n"); | |
413 | } | |
414 | ||
08e875c1 CM |
415 | void __init smp_cpus_done(unsigned int max_cpus) |
416 | { | |
326b16db | 417 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
3a75578e | 418 | setup_cpu_features(); |
377bcff9 JR |
419 | hyp_mode_check(); |
420 | apply_alternatives_all(); | |
5ea5306c | 421 | mark_linear_text_alias_ro(); |
08e875c1 CM |
422 | } |
423 | ||
424 | void __init smp_prepare_boot_cpu(void) | |
425 | { | |
9113c2aa | 426 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
efd9e03f CM |
427 | /* |
428 | * Initialise the static keys early as they may be enabled by the | |
429 | * cpufeature code. | |
430 | */ | |
431 | jump_label_init(); | |
4b998ff1 | 432 | cpuinfo_store_boot_cpu(); |
0ceb0d56 DT |
433 | |
434 | /* | |
435 | * We now know enough about the boot CPU to apply the | |
436 | * alternatives that cannot wait until interrupt handling | |
437 | * and/or scheduling is enabled. | |
438 | */ | |
439 | apply_boot_alternatives(); | |
e7932188 JT |
440 | |
441 | /* Conditionally switch to GIC PMR for interrupt masking */ | |
442 | if (system_uses_irq_prio_masking()) | |
443 | init_gic_priority_masking(); | |
08e875c1 CM |
444 | } |
445 | ||
0f078336 LP |
446 | static u64 __init of_get_cpu_mpidr(struct device_node *dn) |
447 | { | |
448 | const __be32 *cell; | |
449 | u64 hwid; | |
450 | ||
451 | /* | |
452 | * A cpu node with missing "reg" property is | |
453 | * considered invalid to build a cpu_logical_map | |
454 | * entry. | |
455 | */ | |
456 | cell = of_get_property(dn, "reg", NULL); | |
457 | if (!cell) { | |
a270f327 | 458 | pr_err("%pOF: missing reg property\n", dn); |
0f078336 LP |
459 | return INVALID_HWID; |
460 | } | |
461 | ||
462 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
463 | /* | |
464 | * Non affinity bits must be set to 0 in the DT | |
465 | */ | |
466 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
a270f327 | 467 | pr_err("%pOF: invalid reg property\n", dn); |
0f078336 LP |
468 | return INVALID_HWID; |
469 | } | |
470 | return hwid; | |
471 | } | |
472 | ||
473 | /* | |
474 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
475 | * entries and check for duplicates. If any is found just ignore the | |
476 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
477 | * matching valid MPIDR values. | |
478 | */ | |
479 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
480 | { | |
481 | unsigned int i; | |
482 | ||
483 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
484 | if (cpu_logical_map(i) == hwid) | |
485 | return true; | |
486 | return false; | |
487 | } | |
488 | ||
819a8826 LP |
489 | /* |
490 | * Initialize cpu operations for a logical cpu and | |
491 | * set it in the possible mask on success | |
492 | */ | |
493 | static int __init smp_cpu_setup(int cpu) | |
494 | { | |
495 | if (cpu_read_ops(cpu)) | |
496 | return -ENODEV; | |
497 | ||
498 | if (cpu_ops[cpu]->cpu_init(cpu)) | |
499 | return -ENODEV; | |
500 | ||
501 | set_cpu_possible(cpu, true); | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
0f078336 LP |
506 | static bool bootcpu_valid __initdata; |
507 | static unsigned int cpu_count = 1; | |
508 | ||
509 | #ifdef CONFIG_ACPI | |
e0013aed MR |
510 | static struct acpi_madt_generic_interrupt cpu_madt_gicc[NR_CPUS]; |
511 | ||
512 | struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu) | |
513 | { | |
514 | return &cpu_madt_gicc[cpu]; | |
515 | } | |
516 | ||
0f078336 LP |
517 | /* |
518 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
519 | * | |
520 | * Carry out sanity checks on MADT processor entry and initialize | |
521 | * cpu_logical_map on success | |
522 | */ | |
523 | static void __init | |
524 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
525 | { | |
526 | u64 hwid = processor->arm_mpidr; | |
527 | ||
f9058929 HG |
528 | if (!(processor->flags & ACPI_MADT_ENABLED)) { |
529 | pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); | |
0f078336 LP |
530 | return; |
531 | } | |
532 | ||
f9058929 HG |
533 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { |
534 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
0f078336 LP |
535 | return; |
536 | } | |
537 | ||
538 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
539 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
540 | return; | |
541 | } | |
542 | ||
543 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
544 | if (cpu_logical_map(0) == hwid) { | |
545 | if (bootcpu_valid) { | |
546 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
547 | hwid); | |
548 | return; | |
549 | } | |
550 | bootcpu_valid = true; | |
e0013aed | 551 | cpu_madt_gicc[0] = *processor; |
0f078336 LP |
552 | return; |
553 | } | |
554 | ||
555 | if (cpu_count >= NR_CPUS) | |
556 | return; | |
557 | ||
558 | /* map the logical cpu id to cpu MPIDR */ | |
559 | cpu_logical_map(cpu_count) = hwid; | |
560 | ||
e0013aed MR |
561 | cpu_madt_gicc[cpu_count] = *processor; |
562 | ||
5e89c55e LP |
563 | /* |
564 | * Set-up the ACPI parking protocol cpu entries | |
565 | * while initializing the cpu_logical_map to | |
566 | * avoid parsing MADT entries multiple times for | |
567 | * nothing (ie a valid cpu_logical_map entry should | |
568 | * contain a valid parking protocol data set to | |
569 | * initialize the cpu if the parking protocol is | |
570 | * the only available enable method). | |
571 | */ | |
572 | acpi_set_mailbox_entry(cpu_count, processor); | |
573 | ||
0f078336 LP |
574 | cpu_count++; |
575 | } | |
576 | ||
577 | static int __init | |
60574d1e | 578 | acpi_parse_gic_cpu_interface(union acpi_subtable_headers *header, |
0f078336 LP |
579 | const unsigned long end) |
580 | { | |
581 | struct acpi_madt_generic_interrupt *processor; | |
582 | ||
583 | processor = (struct acpi_madt_generic_interrupt *)header; | |
99e3e3ae | 584 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
0f078336 LP |
585 | return -EINVAL; |
586 | ||
60574d1e | 587 | acpi_table_print_madt_entry(&header->common); |
0f078336 LP |
588 | |
589 | acpi_map_gic_cpu_interface(processor); | |
590 | ||
591 | return 0; | |
592 | } | |
e1896249 LP |
593 | |
594 | static void __init acpi_parse_and_init_cpus(void) | |
595 | { | |
596 | int i; | |
597 | ||
598 | /* | |
599 | * do a walk of MADT to determine how many CPUs | |
600 | * we have including disabled CPUs, and get information | |
601 | * we need for SMP init. | |
602 | */ | |
603 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
604 | acpi_parse_gic_cpu_interface, 0); | |
605 | ||
606 | /* | |
607 | * In ACPI, SMP and CPU NUMA information is provided in separate | |
608 | * static tables, namely the MADT and the SRAT. | |
609 | * | |
610 | * Thus, it is simpler to first create the cpu logical map through | |
611 | * an MADT walk and then map the logical cpus to their node ids | |
612 | * as separate steps. | |
613 | */ | |
614 | acpi_map_cpus_to_nodes(); | |
615 | ||
616 | for (i = 0; i < nr_cpu_ids; i++) | |
617 | early_map_cpu_to_node(i, acpi_numa_get_nid(i)); | |
618 | } | |
0f078336 | 619 | #else |
e1896249 | 620 | #define acpi_parse_and_init_cpus(...) do { } while (0) |
0f078336 LP |
621 | #endif |
622 | ||
08e875c1 | 623 | /* |
4c7aa002 JM |
624 | * Enumerate the possible CPU set from the device tree and build the |
625 | * cpu logical map array containing MPIDR values related to logical | |
626 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 627 | */ |
29b8302b | 628 | static void __init of_parse_and_init_cpus(void) |
08e875c1 | 629 | { |
3d29a9a0 | 630 | struct device_node *dn; |
08e875c1 | 631 | |
de76e70a | 632 | for_each_of_cpu_node(dn) { |
0f078336 | 633 | u64 hwid = of_get_cpu_mpidr(dn); |
4c7aa002 | 634 | |
0f078336 | 635 | if (hwid == INVALID_HWID) |
4c7aa002 | 636 | goto next; |
4c7aa002 | 637 | |
0f078336 | 638 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
a270f327 RH |
639 | pr_err("%pOF: duplicate cpu reg properties in the DT\n", |
640 | dn); | |
4c7aa002 JM |
641 | goto next; |
642 | } | |
643 | ||
4c7aa002 JM |
644 | /* |
645 | * The numbering scheme requires that the boot CPU | |
646 | * must be assigned logical id 0. Record it so that | |
647 | * the logical map built from DT is validated and can | |
648 | * be used. | |
649 | */ | |
650 | if (hwid == cpu_logical_map(0)) { | |
651 | if (bootcpu_valid) { | |
a270f327 RH |
652 | pr_err("%pOF: duplicate boot cpu reg property in DT\n", |
653 | dn); | |
4c7aa002 JM |
654 | goto next; |
655 | } | |
656 | ||
657 | bootcpu_valid = true; | |
7ba5f605 | 658 | early_map_cpu_to_node(0, of_node_to_nid(dn)); |
4c7aa002 JM |
659 | |
660 | /* | |
661 | * cpu_logical_map has already been | |
662 | * initialized and the boot cpu doesn't need | |
663 | * the enable-method so continue without | |
664 | * incrementing cpu. | |
665 | */ | |
666 | continue; | |
667 | } | |
668 | ||
0f078336 | 669 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
670 | goto next; |
671 | ||
4c7aa002 | 672 | pr_debug("cpu logical map 0x%llx\n", hwid); |
0f078336 | 673 | cpu_logical_map(cpu_count) = hwid; |
1a2db300 GK |
674 | |
675 | early_map_cpu_to_node(cpu_count, of_node_to_nid(dn)); | |
08e875c1 | 676 | next: |
0f078336 | 677 | cpu_count++; |
08e875c1 | 678 | } |
0f078336 LP |
679 | } |
680 | ||
681 | /* | |
682 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
683 | * cpu logical map array containing MPIDR values related to logical | |
684 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
685 | */ | |
686 | void __init smp_init_cpus(void) | |
687 | { | |
688 | int i; | |
689 | ||
690 | if (acpi_disabled) | |
691 | of_parse_and_init_cpus(); | |
692 | else | |
e1896249 | 693 | acpi_parse_and_init_cpus(); |
08e875c1 | 694 | |
50ee91bd | 695 | if (cpu_count > nr_cpu_ids) |
9b130ad5 | 696 | pr_warn("Number of cores (%d) exceeds configured maximum of %u - clipping\n", |
50ee91bd | 697 | cpu_count, nr_cpu_ids); |
4c7aa002 JM |
698 | |
699 | if (!bootcpu_valid) { | |
0f078336 | 700 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
701 | return; |
702 | } | |
703 | ||
704 | /* | |
819a8826 LP |
705 | * We need to set the cpu_logical_map entries before enabling |
706 | * the cpus so that cpu processor description entries (DT cpu nodes | |
707 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
708 | * with entries in cpu_logical_map while initializing the cpus. | |
709 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 710 | */ |
50ee91bd | 711 | for (i = 1; i < nr_cpu_ids; i++) { |
819a8826 LP |
712 | if (cpu_logical_map(i) != INVALID_HWID) { |
713 | if (smp_cpu_setup(i)) | |
714 | cpu_logical_map(i) = INVALID_HWID; | |
715 | } | |
716 | } | |
08e875c1 CM |
717 | } |
718 | ||
719 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
720 | { | |
cd1aebf5 | 721 | int err; |
44dbcc93 | 722 | unsigned int cpu; |
c18df0ad | 723 | unsigned int this_cpu; |
08e875c1 | 724 | |
f6e763b9 MB |
725 | init_cpu_topology(); |
726 | ||
c18df0ad DD |
727 | this_cpu = smp_processor_id(); |
728 | store_cpu_topology(this_cpu); | |
729 | numa_store_cpu_info(this_cpu); | |
97fd6016 | 730 | numa_add_cpu(this_cpu); |
f6e763b9 | 731 | |
e75118a7 SP |
732 | /* |
733 | * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set | |
734 | * secondary CPUs present. | |
735 | */ | |
736 | if (max_cpus == 0) | |
737 | return; | |
738 | ||
08e875c1 CM |
739 | /* |
740 | * Initialise the present map (which describes the set of CPUs | |
741 | * actually populated at the present time) and release the | |
742 | * secondaries from the bootloader. | |
743 | */ | |
744 | for_each_possible_cpu(cpu) { | |
08e875c1 | 745 | |
57c82954 MR |
746 | per_cpu(cpu_number, cpu) = cpu; |
747 | ||
d329de3f MZ |
748 | if (cpu == smp_processor_id()) |
749 | continue; | |
750 | ||
cd1aebf5 | 751 | if (!cpu_ops[cpu]) |
08e875c1 CM |
752 | continue; |
753 | ||
cd1aebf5 | 754 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
755 | if (err) |
756 | continue; | |
08e875c1 CM |
757 | |
758 | set_cpu_present(cpu, true); | |
c18df0ad | 759 | numa_store_cpu_info(cpu); |
08e875c1 | 760 | } |
08e875c1 CM |
761 | } |
762 | ||
36310736 | 763 | void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
08e875c1 CM |
764 | |
765 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
766 | { | |
45ed695a | 767 | __smp_cross_call = fn; |
08e875c1 CM |
768 | } |
769 | ||
45ed695a NP |
770 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
771 | #define S(x,s) [x] = s | |
08e875c1 CM |
772 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), |
773 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
08e875c1 | 774 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
78fd584c | 775 | S(IPI_CPU_CRASH_STOP, "CPU stop (for crash dump) interrupts"), |
1f85008e | 776 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 777 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5e89c55e | 778 | S(IPI_WAKEUP, "CPU wake-up interrupts"), |
08e875c1 CM |
779 | }; |
780 | ||
45ed695a NP |
781 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
782 | { | |
783 | trace_ipi_raise(target, ipi_types[ipinr]); | |
784 | __smp_cross_call(target, ipinr); | |
785 | } | |
786 | ||
08e875c1 CM |
787 | void show_ipi_list(struct seq_file *p, int prec) |
788 | { | |
789 | unsigned int cpu, i; | |
790 | ||
791 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 792 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 793 | prec >= 4 ? " " : ""); |
67317c26 | 794 | for_each_online_cpu(cpu) |
08e875c1 CM |
795 | seq_printf(p, "%10u ", |
796 | __get_irq_stat(cpu, ipi_irqs[i])); | |
797 | seq_printf(p, " %s\n", ipi_types[i]); | |
798 | } | |
799 | } | |
800 | ||
801 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
802 | { | |
803 | u64 sum = 0; | |
804 | int i; | |
805 | ||
806 | for (i = 0; i < NR_IPI; i++) | |
807 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
808 | ||
809 | return sum; | |
810 | } | |
811 | ||
45ed695a NP |
812 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
813 | { | |
814 | smp_cross_call(mask, IPI_CALL_FUNC); | |
815 | } | |
816 | ||
817 | void arch_send_call_function_single_ipi(int cpu) | |
818 | { | |
0aaf0dae | 819 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
820 | } |
821 | ||
5e89c55e LP |
822 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
823 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
824 | { | |
825 | smp_cross_call(mask, IPI_WAKEUP); | |
826 | } | |
827 | #endif | |
828 | ||
45ed695a NP |
829 | #ifdef CONFIG_IRQ_WORK |
830 | void arch_irq_work_raise(void) | |
831 | { | |
832 | if (__smp_cross_call) | |
833 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
834 | } | |
835 | #endif | |
836 | ||
08e875c1 CM |
837 | /* |
838 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
839 | */ | |
840 | static void ipi_cpu_stop(unsigned int cpu) | |
841 | { | |
08e875c1 CM |
842 | set_cpu_online(cpu, false); |
843 | ||
0fbeb318 | 844 | local_daif_mask(); |
f5df2696 | 845 | sdei_mask_local_cpu(); |
08e875c1 CM |
846 | |
847 | while (1) | |
848 | cpu_relax(); | |
849 | } | |
850 | ||
78fd584c AT |
851 | #ifdef CONFIG_KEXEC_CORE |
852 | static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0); | |
853 | #endif | |
854 | ||
855 | static void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) | |
856 | { | |
857 | #ifdef CONFIG_KEXEC_CORE | |
858 | crash_save_cpu(regs, cpu); | |
859 | ||
860 | atomic_dec(&waiting_for_crash_ipi); | |
861 | ||
862 | local_irq_disable(); | |
f5df2696 | 863 | sdei_mask_local_cpu(); |
78fd584c AT |
864 | |
865 | #ifdef CONFIG_HOTPLUG_CPU | |
866 | if (cpu_ops[cpu]->cpu_die) | |
867 | cpu_ops[cpu]->cpu_die(cpu); | |
868 | #endif | |
869 | ||
870 | /* just in case */ | |
871 | cpu_park_loop(); | |
872 | #endif | |
873 | } | |
874 | ||
08e875c1 CM |
875 | /* |
876 | * Main handler for inter-processor interrupts | |
877 | */ | |
878 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
879 | { | |
880 | unsigned int cpu = smp_processor_id(); | |
881 | struct pt_regs *old_regs = set_irq_regs(regs); | |
882 | ||
45ed695a | 883 | if ((unsigned)ipinr < NR_IPI) { |
be081d9b | 884 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
45ed695a NP |
885 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
886 | } | |
08e875c1 CM |
887 | |
888 | switch (ipinr) { | |
889 | case IPI_RESCHEDULE: | |
890 | scheduler_ipi(); | |
891 | break; | |
892 | ||
893 | case IPI_CALL_FUNC: | |
894 | irq_enter(); | |
895 | generic_smp_call_function_interrupt(); | |
896 | irq_exit(); | |
897 | break; | |
898 | ||
08e875c1 CM |
899 | case IPI_CPU_STOP: |
900 | irq_enter(); | |
901 | ipi_cpu_stop(cpu); | |
902 | irq_exit(); | |
903 | break; | |
904 | ||
78fd584c AT |
905 | case IPI_CPU_CRASH_STOP: |
906 | if (IS_ENABLED(CONFIG_KEXEC_CORE)) { | |
907 | irq_enter(); | |
908 | ipi_cpu_crash_stop(cpu, regs); | |
909 | ||
910 | unreachable(); | |
911 | } | |
912 | break; | |
913 | ||
1f85008e LP |
914 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
915 | case IPI_TIMER: | |
916 | irq_enter(); | |
917 | tick_receive_broadcast(); | |
918 | irq_exit(); | |
919 | break; | |
920 | #endif | |
921 | ||
eb631bb5 LB |
922 | #ifdef CONFIG_IRQ_WORK |
923 | case IPI_IRQ_WORK: | |
924 | irq_enter(); | |
925 | irq_work_run(); | |
926 | irq_exit(); | |
927 | break; | |
928 | #endif | |
929 | ||
5e89c55e LP |
930 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
931 | case IPI_WAKEUP: | |
932 | WARN_ONCE(!acpi_parking_protocol_valid(cpu), | |
933 | "CPU%u: Wake-up IPI outside the ACPI parking protocol\n", | |
934 | cpu); | |
935 | break; | |
936 | #endif | |
937 | ||
08e875c1 CM |
938 | default: |
939 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
940 | break; | |
941 | } | |
45ed695a NP |
942 | |
943 | if ((unsigned)ipinr < NR_IPI) | |
be081d9b | 944 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
08e875c1 CM |
945 | set_irq_regs(old_regs); |
946 | } | |
947 | ||
948 | void smp_send_reschedule(int cpu) | |
949 | { | |
950 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
951 | } | |
952 | ||
1f85008e LP |
953 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
954 | void tick_broadcast(const struct cpumask *mask) | |
955 | { | |
956 | smp_cross_call(mask, IPI_TIMER); | |
957 | } | |
958 | #endif | |
959 | ||
08e875c1 CM |
960 | void smp_send_stop(void) |
961 | { | |
962 | unsigned long timeout; | |
963 | ||
964 | if (num_online_cpus() > 1) { | |
965 | cpumask_t mask; | |
966 | ||
967 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 968 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 | 969 | |
ef284f5c | 970 | if (system_state <= SYSTEM_RUNNING) |
82611c14 | 971 | pr_crit("SMP: stopping secondary CPUs\n"); |
08e875c1 CM |
972 | smp_cross_call(&mask, IPI_CPU_STOP); |
973 | } | |
974 | ||
975 | /* Wait up to one second for other CPUs to stop */ | |
976 | timeout = USEC_PER_SEC; | |
977 | while (num_online_cpus() > 1 && timeout--) | |
978 | udelay(1); | |
979 | ||
980 | if (num_online_cpus() > 1) | |
82611c14 JG |
981 | pr_warning("SMP: failed to stop secondary CPUs %*pbl\n", |
982 | cpumask_pr_args(cpu_online_mask)); | |
f5df2696 JM |
983 | |
984 | sdei_mask_local_cpu(); | |
08e875c1 CM |
985 | } |
986 | ||
78fd584c | 987 | #ifdef CONFIG_KEXEC_CORE |
a88ce63b | 988 | void crash_smp_send_stop(void) |
78fd584c | 989 | { |
a88ce63b | 990 | static int cpus_stopped; |
78fd584c AT |
991 | cpumask_t mask; |
992 | unsigned long timeout; | |
993 | ||
a88ce63b HR |
994 | /* |
995 | * This function can be called twice in panic path, but obviously | |
996 | * we execute this only once. | |
997 | */ | |
998 | if (cpus_stopped) | |
999 | return; | |
1000 | ||
1001 | cpus_stopped = 1; | |
1002 | ||
f5df2696 JM |
1003 | if (num_online_cpus() == 1) { |
1004 | sdei_mask_local_cpu(); | |
78fd584c | 1005 | return; |
f5df2696 | 1006 | } |
78fd584c AT |
1007 | |
1008 | cpumask_copy(&mask, cpu_online_mask); | |
1009 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
1010 | ||
1011 | atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1); | |
1012 | ||
1013 | pr_crit("SMP: stopping secondary CPUs\n"); | |
1014 | smp_cross_call(&mask, IPI_CPU_CRASH_STOP); | |
1015 | ||
1016 | /* Wait up to one second for other CPUs to stop */ | |
1017 | timeout = USEC_PER_SEC; | |
1018 | while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--) | |
1019 | udelay(1); | |
1020 | ||
1021 | if (atomic_read(&waiting_for_crash_ipi) > 0) | |
1022 | pr_warning("SMP: failed to stop secondary CPUs %*pbl\n", | |
1023 | cpumask_pr_args(&mask)); | |
f5df2696 JM |
1024 | |
1025 | sdei_mask_local_cpu(); | |
78fd584c AT |
1026 | } |
1027 | ||
1028 | bool smp_crash_stop_failed(void) | |
1029 | { | |
1030 | return (atomic_read(&waiting_for_crash_ipi) > 0); | |
1031 | } | |
1032 | #endif | |
1033 | ||
08e875c1 CM |
1034 | /* |
1035 | * not supported here | |
1036 | */ | |
1037 | int setup_profiling_timer(unsigned int multiplier) | |
1038 | { | |
1039 | return -EINVAL; | |
1040 | } | |
5c492c3f JM |
1041 | |
1042 | static bool have_cpu_die(void) | |
1043 | { | |
1044 | #ifdef CONFIG_HOTPLUG_CPU | |
1045 | int any_cpu = raw_smp_processor_id(); | |
1046 | ||
335d2c2d | 1047 | if (cpu_ops[any_cpu] && cpu_ops[any_cpu]->cpu_die) |
5c492c3f JM |
1048 | return true; |
1049 | #endif | |
1050 | return false; | |
1051 | } | |
1052 | ||
1053 | bool cpus_are_stuck_in_kernel(void) | |
1054 | { | |
1055 | bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die()); | |
1056 | ||
1057 | return !!cpus_stuck_in_kernel || smp_spin_tables; | |
1058 | } |