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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7c8c5e6a MZ |
2 | /* |
3 | * Copyright (C) 2012,2013 - ARM Ltd | |
4 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
5 | * | |
6 | * Derived from arch/arm/kvm/coproc.c: | |
7 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
8 | * Authors: Rusty Russell <rusty@rustcorp.com.au> | |
9 | * Christoffer Dall <c.dall@virtualopensystems.com> | |
7c8c5e6a MZ |
10 | */ |
11 | ||
623eefa8 | 12 | #include <linux/bsearch.h> |
7c8c5e6a | 13 | #include <linux/kvm_host.h> |
c6d01a94 | 14 | #include <linux/mm.h> |
07d79fe7 | 15 | #include <linux/printk.h> |
7c8c5e6a | 16 | #include <linux/uaccess.h> |
c6d01a94 | 17 | |
7c8c5e6a MZ |
18 | #include <asm/cacheflush.h> |
19 | #include <asm/cputype.h> | |
0c557ed4 | 20 | #include <asm/debug-monitors.h> |
c6d01a94 MR |
21 | #include <asm/esr.h> |
22 | #include <asm/kvm_arm.h> | |
c6d01a94 | 23 | #include <asm/kvm_emulate.h> |
d47533da | 24 | #include <asm/kvm_hyp.h> |
c6d01a94 | 25 | #include <asm/kvm_mmu.h> |
ab946834 | 26 | #include <asm/perf_event.h> |
1f3d8699 | 27 | #include <asm/sysreg.h> |
c6d01a94 | 28 | |
7c8c5e6a MZ |
29 | #include <trace/events/kvm.h> |
30 | ||
31 | #include "sys_regs.h" | |
32 | ||
eef8c85a AB |
33 | #include "trace.h" |
34 | ||
7c8c5e6a | 35 | /* |
656012c7 | 36 | * All of this file is extremely similar to the ARM coproc.c, but the |
7c8c5e6a MZ |
37 | * types are different. My gut feeling is that it should be pretty |
38 | * easy to merge, but that would be an ABI breakage -- again. VFP | |
39 | * would also need to be abstracted. | |
62a89c44 MZ |
40 | * |
41 | * For AArch32, we only take care of what is being trapped. Anything | |
42 | * that has to do with init and userspace access has to go via the | |
43 | * 64bit interface. | |
7c8c5e6a MZ |
44 | */ |
45 | ||
7b5b4df1 | 46 | static bool read_from_write_only(struct kvm_vcpu *vcpu, |
e7f1d1ee MZ |
47 | struct sys_reg_params *params, |
48 | const struct sys_reg_desc *r) | |
7b5b4df1 MZ |
49 | { |
50 | WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); | |
51 | print_sys_reg_instr(params); | |
52 | kvm_inject_undefined(vcpu); | |
53 | return false; | |
54 | } | |
55 | ||
7b1dba1f MZ |
56 | static bool write_to_read_only(struct kvm_vcpu *vcpu, |
57 | struct sys_reg_params *params, | |
58 | const struct sys_reg_desc *r) | |
59 | { | |
60 | WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); | |
61 | print_sys_reg_instr(params); | |
62 | kvm_inject_undefined(vcpu); | |
63 | return false; | |
64 | } | |
65 | ||
7ea90bdd MZ |
66 | u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) |
67 | { | |
68 | u64 val = 0x8badf00d8badf00d; | |
69 | ||
70 | if (vcpu->arch.sysregs_loaded_on_cpu && | |
71 | __vcpu_read_sys_reg_from_cpu(reg, &val)) | |
72 | return val; | |
73 | ||
74 | return __vcpu_sys_reg(vcpu, reg); | |
75 | } | |
76 | ||
77 | void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) | |
78 | { | |
79 | if (vcpu->arch.sysregs_loaded_on_cpu && | |
80 | __vcpu_write_sys_reg_to_cpu(val, reg)) | |
81 | return; | |
82 | ||
d47533da CD |
83 | __vcpu_sys_reg(vcpu, reg) = val; |
84 | } | |
85 | ||
7c8c5e6a MZ |
86 | /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ |
87 | static u32 cache_levels; | |
88 | ||
89 | /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ | |
c73a4416 | 90 | #define CSSELR_MAX 14 |
7c8c5e6a MZ |
91 | |
92 | /* Which cache CCSIDR represents depends on CSSELR value. */ | |
93 | static u32 get_ccsidr(u32 csselr) | |
94 | { | |
95 | u32 ccsidr; | |
96 | ||
97 | /* Make sure noone else changes CSSELR during this! */ | |
98 | local_irq_disable(); | |
1f3d8699 | 99 | write_sysreg(csselr, csselr_el1); |
7c8c5e6a | 100 | isb(); |
1f3d8699 | 101 | ccsidr = read_sysreg(ccsidr_el1); |
7c8c5e6a MZ |
102 | local_irq_enable(); |
103 | ||
104 | return ccsidr; | |
105 | } | |
106 | ||
3c1e7165 MZ |
107 | /* |
108 | * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). | |
109 | */ | |
7c8c5e6a | 110 | static bool access_dcsw(struct kvm_vcpu *vcpu, |
3fec037d | 111 | struct sys_reg_params *p, |
7c8c5e6a MZ |
112 | const struct sys_reg_desc *r) |
113 | { | |
7c8c5e6a | 114 | if (!p->is_write) |
e7f1d1ee | 115 | return read_from_write_only(vcpu, p, r); |
7c8c5e6a | 116 | |
09605e94 MZ |
117 | /* |
118 | * Only track S/W ops if we don't have FWB. It still indicates | |
119 | * that the guest is a bit broken (S/W operations should only | |
120 | * be done by firmware, knowing that there is only a single | |
121 | * CPU left in the system, and certainly not from non-secure | |
122 | * software). | |
123 | */ | |
124 | if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) | |
125 | kvm_set_way_flush(vcpu); | |
126 | ||
7c8c5e6a MZ |
127 | return true; |
128 | } | |
129 | ||
b1ea1d76 MZ |
130 | static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) |
131 | { | |
132 | switch (r->aarch32_map) { | |
133 | case AA32_LO: | |
134 | *mask = GENMASK_ULL(31, 0); | |
135 | *shift = 0; | |
136 | break; | |
137 | case AA32_HI: | |
138 | *mask = GENMASK_ULL(63, 32); | |
139 | *shift = 32; | |
140 | break; | |
141 | default: | |
142 | *mask = GENMASK_ULL(63, 0); | |
143 | *shift = 0; | |
144 | break; | |
145 | } | |
146 | } | |
147 | ||
4d44923b MZ |
148 | /* |
149 | * Generic accessor for VM registers. Only called as long as HCR_TVM | |
3c1e7165 MZ |
150 | * is set. If the guest enables the MMU, we stop trapping the VM |
151 | * sys_regs and leave it in complete control of the caches. | |
4d44923b MZ |
152 | */ |
153 | static bool access_vm_reg(struct kvm_vcpu *vcpu, | |
3fec037d | 154 | struct sys_reg_params *p, |
4d44923b MZ |
155 | const struct sys_reg_desc *r) |
156 | { | |
3c1e7165 | 157 | bool was_enabled = vcpu_has_cache_enabled(vcpu); |
b1ea1d76 | 158 | u64 val, mask, shift; |
4d44923b MZ |
159 | |
160 | BUG_ON(!p->is_write); | |
161 | ||
b1ea1d76 | 162 | get_access_mask(r, &mask, &shift); |
52f6c4f0 | 163 | |
b1ea1d76 MZ |
164 | if (~mask) { |
165 | val = vcpu_read_sys_reg(vcpu, r->reg); | |
166 | val &= ~mask; | |
dedf97e8 | 167 | } else { |
b1ea1d76 | 168 | val = 0; |
dedf97e8 | 169 | } |
b1ea1d76 MZ |
170 | |
171 | val |= (p->regval & (mask >> shift)) << shift; | |
172 | vcpu_write_sys_reg(vcpu, val, r->reg); | |
f0a3eaff | 173 | |
3c1e7165 | 174 | kvm_toggle_cache(vcpu, was_enabled); |
4d44923b MZ |
175 | return true; |
176 | } | |
177 | ||
af473829 JM |
178 | static bool access_actlr(struct kvm_vcpu *vcpu, |
179 | struct sys_reg_params *p, | |
180 | const struct sys_reg_desc *r) | |
181 | { | |
b1ea1d76 MZ |
182 | u64 mask, shift; |
183 | ||
af473829 JM |
184 | if (p->is_write) |
185 | return ignore_write(vcpu, p); | |
186 | ||
b1ea1d76 MZ |
187 | get_access_mask(r, &mask, &shift); |
188 | p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; | |
af473829 JM |
189 | |
190 | return true; | |
191 | } | |
192 | ||
6d52f35a AP |
193 | /* |
194 | * Trap handler for the GICv3 SGI generation system register. | |
195 | * Forward the request to the VGIC emulation. | |
196 | * The cp15_64 code makes sure this automatically works | |
197 | * for both AArch64 and AArch32 accesses. | |
198 | */ | |
199 | static bool access_gic_sgi(struct kvm_vcpu *vcpu, | |
3fec037d | 200 | struct sys_reg_params *p, |
6d52f35a AP |
201 | const struct sys_reg_desc *r) |
202 | { | |
03bd646d MZ |
203 | bool g1; |
204 | ||
6d52f35a | 205 | if (!p->is_write) |
e7f1d1ee | 206 | return read_from_write_only(vcpu, p, r); |
6d52f35a | 207 | |
03bd646d MZ |
208 | /* |
209 | * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates | |
210 | * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, | |
211 | * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively | |
212 | * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure | |
213 | * group. | |
214 | */ | |
50f30453 | 215 | if (p->Op0 == 0) { /* AArch32 */ |
03bd646d MZ |
216 | switch (p->Op1) { |
217 | default: /* Keep GCC quiet */ | |
218 | case 0: /* ICC_SGI1R */ | |
219 | g1 = true; | |
220 | break; | |
221 | case 1: /* ICC_ASGI1R */ | |
222 | case 2: /* ICC_SGI0R */ | |
223 | g1 = false; | |
224 | break; | |
225 | } | |
50f30453 | 226 | } else { /* AArch64 */ |
03bd646d MZ |
227 | switch (p->Op2) { |
228 | default: /* Keep GCC quiet */ | |
229 | case 5: /* ICC_SGI1R_EL1 */ | |
230 | g1 = true; | |
231 | break; | |
232 | case 6: /* ICC_ASGI1R_EL1 */ | |
233 | case 7: /* ICC_SGI0R_EL1 */ | |
234 | g1 = false; | |
235 | break; | |
236 | } | |
237 | } | |
238 | ||
239 | vgic_v3_dispatch_sgi(vcpu, p->regval, g1); | |
6d52f35a AP |
240 | |
241 | return true; | |
242 | } | |
243 | ||
b34f2bcb MZ |
244 | static bool access_gic_sre(struct kvm_vcpu *vcpu, |
245 | struct sys_reg_params *p, | |
246 | const struct sys_reg_desc *r) | |
247 | { | |
248 | if (p->is_write) | |
249 | return ignore_write(vcpu, p); | |
250 | ||
251 | p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; | |
252 | return true; | |
253 | } | |
254 | ||
7609c125 | 255 | static bool trap_raz_wi(struct kvm_vcpu *vcpu, |
3fec037d | 256 | struct sys_reg_params *p, |
7609c125 | 257 | const struct sys_reg_desc *r) |
7c8c5e6a MZ |
258 | { |
259 | if (p->is_write) | |
260 | return ignore_write(vcpu, p); | |
261 | else | |
262 | return read_zero(vcpu, p); | |
263 | } | |
264 | ||
22925521 MZ |
265 | /* |
266 | * ARMv8.1 mandates at least a trivial LORegion implementation, where all the | |
267 | * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 | |
268 | * system, these registers should UNDEF. LORID_EL1 being a RO register, we | |
269 | * treat it separately. | |
270 | */ | |
271 | static bool trap_loregion(struct kvm_vcpu *vcpu, | |
272 | struct sys_reg_params *p, | |
273 | const struct sys_reg_desc *r) | |
cc33c4e2 | 274 | { |
22925521 MZ |
275 | u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); |
276 | u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, | |
277 | (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); | |
278 | ||
279 | if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { | |
280 | kvm_inject_undefined(vcpu); | |
281 | return false; | |
282 | } | |
283 | ||
284 | if (p->is_write && sr == SYS_LORID_EL1) | |
285 | return write_to_read_only(vcpu, p, r); | |
286 | ||
287 | return trap_raz_wi(vcpu, p, r); | |
cc33c4e2 MR |
288 | } |
289 | ||
0c557ed4 | 290 | static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, |
3fec037d | 291 | struct sys_reg_params *p, |
0c557ed4 MZ |
292 | const struct sys_reg_desc *r) |
293 | { | |
294 | if (p->is_write) { | |
295 | return ignore_write(vcpu, p); | |
296 | } else { | |
2ec5be3d | 297 | p->regval = (1 << 3); |
0c557ed4 MZ |
298 | return true; |
299 | } | |
300 | } | |
301 | ||
302 | static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, | |
3fec037d | 303 | struct sys_reg_params *p, |
0c557ed4 MZ |
304 | const struct sys_reg_desc *r) |
305 | { | |
306 | if (p->is_write) { | |
307 | return ignore_write(vcpu, p); | |
308 | } else { | |
1f3d8699 | 309 | p->regval = read_sysreg(dbgauthstatus_el1); |
0c557ed4 MZ |
310 | return true; |
311 | } | |
312 | } | |
313 | ||
314 | /* | |
315 | * We want to avoid world-switching all the DBG registers all the | |
316 | * time: | |
317 | * | |
318 | * - If we've touched any debug register, it is likely that we're | |
319 | * going to touch more of them. It then makes sense to disable the | |
320 | * traps and start doing the save/restore dance | |
321 | * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is | |
322 | * then mandatory to save/restore the registers, as the guest | |
323 | * depends on them. | |
324 | * | |
325 | * For this, we use a DIRTY bit, indicating the guest has modified the | |
326 | * debug registers, used as follow: | |
327 | * | |
328 | * On guest entry: | |
329 | * - If the dirty bit is set (because we're coming back from trapping), | |
330 | * disable the traps, save host registers, restore guest registers. | |
331 | * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), | |
332 | * set the dirty bit, disable the traps, save host registers, | |
333 | * restore guest registers. | |
334 | * - Otherwise, enable the traps | |
335 | * | |
336 | * On guest exit: | |
337 | * - If the dirty bit is set, save guest registers, restore host | |
338 | * registers and clear the dirty bit. This ensure that the host can | |
339 | * now use the debug registers. | |
340 | */ | |
341 | static bool trap_debug_regs(struct kvm_vcpu *vcpu, | |
3fec037d | 342 | struct sys_reg_params *p, |
0c557ed4 MZ |
343 | const struct sys_reg_desc *r) |
344 | { | |
345 | if (p->is_write) { | |
8d404c4c | 346 | vcpu_write_sys_reg(vcpu, p->regval, r->reg); |
fa89d31c | 347 | vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; |
0c557ed4 | 348 | } else { |
8d404c4c | 349 | p->regval = vcpu_read_sys_reg(vcpu, r->reg); |
0c557ed4 MZ |
350 | } |
351 | ||
2ec5be3d | 352 | trace_trap_reg(__func__, r->reg, p->is_write, p->regval); |
eef8c85a | 353 | |
0c557ed4 MZ |
354 | return true; |
355 | } | |
356 | ||
84e690bf AB |
357 | /* |
358 | * reg_to_dbg/dbg_to_reg | |
359 | * | |
360 | * A 32 bit write to a debug register leave top bits alone | |
361 | * A 32 bit read from a debug register only returns the bottom bits | |
362 | * | |
363 | * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the | |
364 | * hyp.S code switches between host and guest values in future. | |
365 | */ | |
281243cb MZ |
366 | static void reg_to_dbg(struct kvm_vcpu *vcpu, |
367 | struct sys_reg_params *p, | |
1da42c34 | 368 | const struct sys_reg_desc *rd, |
281243cb | 369 | u64 *dbg_reg) |
84e690bf | 370 | { |
1da42c34 | 371 | u64 mask, shift, val; |
84e690bf | 372 | |
1da42c34 | 373 | get_access_mask(rd, &mask, &shift); |
84e690bf | 374 | |
1da42c34 MZ |
375 | val = *dbg_reg; |
376 | val &= ~mask; | |
377 | val |= (p->regval & (mask >> shift)) << shift; | |
84e690bf | 378 | *dbg_reg = val; |
1da42c34 | 379 | |
fa89d31c | 380 | vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; |
84e690bf AB |
381 | } |
382 | ||
281243cb MZ |
383 | static void dbg_to_reg(struct kvm_vcpu *vcpu, |
384 | struct sys_reg_params *p, | |
1da42c34 | 385 | const struct sys_reg_desc *rd, |
281243cb | 386 | u64 *dbg_reg) |
84e690bf | 387 | { |
1da42c34 MZ |
388 | u64 mask, shift; |
389 | ||
390 | get_access_mask(rd, &mask, &shift); | |
391 | p->regval = (*dbg_reg & mask) >> shift; | |
84e690bf AB |
392 | } |
393 | ||
281243cb MZ |
394 | static bool trap_bvr(struct kvm_vcpu *vcpu, |
395 | struct sys_reg_params *p, | |
396 | const struct sys_reg_desc *rd) | |
84e690bf AB |
397 | { |
398 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; | |
399 | ||
400 | if (p->is_write) | |
1da42c34 | 401 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 402 | else |
1da42c34 | 403 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 404 | |
eef8c85a AB |
405 | trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); |
406 | ||
84e690bf AB |
407 | return true; |
408 | } | |
409 | ||
410 | static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
411 | const struct kvm_one_reg *reg, void __user *uaddr) | |
412 | { | |
413 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; | |
414 | ||
1713e5aa | 415 | if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) |
84e690bf AB |
416 | return -EFAULT; |
417 | return 0; | |
418 | } | |
419 | ||
420 | static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
421 | const struct kvm_one_reg *reg, void __user *uaddr) | |
422 | { | |
423 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; | |
424 | ||
425 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) | |
426 | return -EFAULT; | |
427 | return 0; | |
428 | } | |
429 | ||
281243cb MZ |
430 | static void reset_bvr(struct kvm_vcpu *vcpu, |
431 | const struct sys_reg_desc *rd) | |
84e690bf AB |
432 | { |
433 | vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; | |
434 | } | |
435 | ||
281243cb MZ |
436 | static bool trap_bcr(struct kvm_vcpu *vcpu, |
437 | struct sys_reg_params *p, | |
438 | const struct sys_reg_desc *rd) | |
84e690bf AB |
439 | { |
440 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; | |
441 | ||
442 | if (p->is_write) | |
1da42c34 | 443 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 444 | else |
1da42c34 | 445 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 446 | |
eef8c85a AB |
447 | trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); |
448 | ||
84e690bf AB |
449 | return true; |
450 | } | |
451 | ||
452 | static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
453 | const struct kvm_one_reg *reg, void __user *uaddr) | |
454 | { | |
455 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; | |
456 | ||
1713e5aa | 457 | if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) |
84e690bf AB |
458 | return -EFAULT; |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
464 | const struct kvm_one_reg *reg, void __user *uaddr) | |
465 | { | |
466 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; | |
467 | ||
468 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) | |
469 | return -EFAULT; | |
470 | return 0; | |
471 | } | |
472 | ||
281243cb MZ |
473 | static void reset_bcr(struct kvm_vcpu *vcpu, |
474 | const struct sys_reg_desc *rd) | |
84e690bf AB |
475 | { |
476 | vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; | |
477 | } | |
478 | ||
281243cb MZ |
479 | static bool trap_wvr(struct kvm_vcpu *vcpu, |
480 | struct sys_reg_params *p, | |
481 | const struct sys_reg_desc *rd) | |
84e690bf AB |
482 | { |
483 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; | |
484 | ||
485 | if (p->is_write) | |
1da42c34 | 486 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 487 | else |
1da42c34 | 488 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 489 | |
eef8c85a AB |
490 | trace_trap_reg(__func__, rd->reg, p->is_write, |
491 | vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); | |
492 | ||
84e690bf AB |
493 | return true; |
494 | } | |
495 | ||
496 | static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
497 | const struct kvm_one_reg *reg, void __user *uaddr) | |
498 | { | |
499 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; | |
500 | ||
1713e5aa | 501 | if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) |
84e690bf AB |
502 | return -EFAULT; |
503 | return 0; | |
504 | } | |
505 | ||
506 | static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
507 | const struct kvm_one_reg *reg, void __user *uaddr) | |
508 | { | |
509 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; | |
510 | ||
511 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) | |
512 | return -EFAULT; | |
513 | return 0; | |
514 | } | |
515 | ||
281243cb MZ |
516 | static void reset_wvr(struct kvm_vcpu *vcpu, |
517 | const struct sys_reg_desc *rd) | |
84e690bf AB |
518 | { |
519 | vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; | |
520 | } | |
521 | ||
281243cb MZ |
522 | static bool trap_wcr(struct kvm_vcpu *vcpu, |
523 | struct sys_reg_params *p, | |
524 | const struct sys_reg_desc *rd) | |
84e690bf AB |
525 | { |
526 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; | |
527 | ||
528 | if (p->is_write) | |
1da42c34 | 529 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 530 | else |
1da42c34 | 531 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 532 | |
eef8c85a AB |
533 | trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); |
534 | ||
84e690bf AB |
535 | return true; |
536 | } | |
537 | ||
538 | static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
539 | const struct kvm_one_reg *reg, void __user *uaddr) | |
540 | { | |
541 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; | |
542 | ||
1713e5aa | 543 | if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) |
84e690bf AB |
544 | return -EFAULT; |
545 | return 0; | |
546 | } | |
547 | ||
548 | static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
549 | const struct kvm_one_reg *reg, void __user *uaddr) | |
550 | { | |
551 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; | |
552 | ||
553 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) | |
554 | return -EFAULT; | |
555 | return 0; | |
556 | } | |
557 | ||
281243cb MZ |
558 | static void reset_wcr(struct kvm_vcpu *vcpu, |
559 | const struct sys_reg_desc *rd) | |
84e690bf AB |
560 | { |
561 | vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; | |
562 | } | |
563 | ||
7c8c5e6a MZ |
564 | static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
565 | { | |
8d404c4c CD |
566 | u64 amair = read_sysreg(amair_el1); |
567 | vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); | |
7c8c5e6a MZ |
568 | } |
569 | ||
af473829 JM |
570 | static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
571 | { | |
572 | u64 actlr = read_sysreg(actlr_el1); | |
573 | vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); | |
574 | } | |
575 | ||
7c8c5e6a MZ |
576 | static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
577 | { | |
4429fc64 AP |
578 | u64 mpidr; |
579 | ||
7c8c5e6a | 580 | /* |
4429fc64 AP |
581 | * Map the vcpu_id into the first three affinity level fields of |
582 | * the MPIDR. We limit the number of VCPUs in level 0 due to a | |
583 | * limitation to 16 CPUs in that level in the ICC_SGIxR registers | |
584 | * of the GICv3 to be able to address each CPU directly when | |
585 | * sending IPIs. | |
7c8c5e6a | 586 | */ |
4429fc64 AP |
587 | mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); |
588 | mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); | |
589 | mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); | |
8d404c4c | 590 | vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); |
7c8c5e6a MZ |
591 | } |
592 | ||
ab946834 SZ |
593 | static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
594 | { | |
595 | u64 pmcr, val; | |
596 | ||
2a5f1b67 MZ |
597 | /* No PMU available, PMCR_EL0 may UNDEF... */ |
598 | if (!kvm_arm_support_pmu_v3()) | |
599 | return; | |
600 | ||
1f3d8699 MR |
601 | pmcr = read_sysreg(pmcr_el0); |
602 | /* | |
603 | * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN | |
ab946834 SZ |
604 | * except PMCR.E resetting to zero. |
605 | */ | |
606 | val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) | |
607 | | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); | |
6f163714 MZ |
608 | if (!system_supports_32bit_el0()) |
609 | val |= ARMV8_PMU_PMCR_LC; | |
03fdfb26 | 610 | __vcpu_sys_reg(vcpu, r->reg) = val; |
ab946834 SZ |
611 | } |
612 | ||
6c007036 | 613 | static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) |
d692b8ad | 614 | { |
8d404c4c | 615 | u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); |
b0737e99 | 616 | bool enabled = kvm_vcpu_has_pmu(vcpu); |
d692b8ad | 617 | |
b0737e99 | 618 | enabled &= (reg & flags) || vcpu_mode_priv(vcpu); |
24d5950f MZ |
619 | if (!enabled) |
620 | kvm_inject_undefined(vcpu); | |
d692b8ad | 621 | |
6c007036 | 622 | return !enabled; |
d692b8ad SZ |
623 | } |
624 | ||
6c007036 | 625 | static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) |
d692b8ad | 626 | { |
6c007036 MZ |
627 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); |
628 | } | |
d692b8ad | 629 | |
6c007036 MZ |
630 | static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) |
631 | { | |
632 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); | |
d692b8ad SZ |
633 | } |
634 | ||
635 | static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) | |
636 | { | |
6c007036 | 637 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); |
d692b8ad SZ |
638 | } |
639 | ||
640 | static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) | |
641 | { | |
6c007036 | 642 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); |
d692b8ad SZ |
643 | } |
644 | ||
ab946834 SZ |
645 | static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
646 | const struct sys_reg_desc *r) | |
647 | { | |
648 | u64 val; | |
649 | ||
d692b8ad SZ |
650 | if (pmu_access_el0_disabled(vcpu)) |
651 | return false; | |
652 | ||
ab946834 SZ |
653 | if (p->is_write) { |
654 | /* Only update writeable bits of PMCR */ | |
8d404c4c | 655 | val = __vcpu_sys_reg(vcpu, PMCR_EL0); |
ab946834 SZ |
656 | val &= ~ARMV8_PMU_PMCR_MASK; |
657 | val |= p->regval & ARMV8_PMU_PMCR_MASK; | |
6f163714 MZ |
658 | if (!system_supports_32bit_el0()) |
659 | val |= ARMV8_PMU_PMCR_LC; | |
8d404c4c | 660 | __vcpu_sys_reg(vcpu, PMCR_EL0) = val; |
76993739 | 661 | kvm_pmu_handle_pmcr(vcpu, val); |
435e53fb | 662 | kvm_vcpu_pmu_restore_guest(vcpu); |
ab946834 SZ |
663 | } else { |
664 | /* PMCR.P & PMCR.C are RAZ */ | |
8d404c4c | 665 | val = __vcpu_sys_reg(vcpu, PMCR_EL0) |
ab946834 SZ |
666 | & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); |
667 | p->regval = val; | |
668 | } | |
669 | ||
670 | return true; | |
671 | } | |
672 | ||
3965c3ce SZ |
673 | static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
674 | const struct sys_reg_desc *r) | |
675 | { | |
d692b8ad SZ |
676 | if (pmu_access_event_counter_el0_disabled(vcpu)) |
677 | return false; | |
678 | ||
3965c3ce | 679 | if (p->is_write) |
8d404c4c | 680 | __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; |
3965c3ce SZ |
681 | else |
682 | /* return PMSELR.SEL field */ | |
8d404c4c | 683 | p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) |
3965c3ce SZ |
684 | & ARMV8_PMU_COUNTER_MASK; |
685 | ||
686 | return true; | |
687 | } | |
688 | ||
a86b5505 SZ |
689 | static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
690 | const struct sys_reg_desc *r) | |
691 | { | |
692 | u64 pmceid; | |
693 | ||
a86b5505 SZ |
694 | BUG_ON(p->is_write); |
695 | ||
d692b8ad SZ |
696 | if (pmu_access_el0_disabled(vcpu)) |
697 | return false; | |
698 | ||
88865bec | 699 | pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); |
a86b5505 SZ |
700 | |
701 | p->regval = pmceid; | |
702 | ||
703 | return true; | |
704 | } | |
705 | ||
051ff581 SZ |
706 | static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) |
707 | { | |
708 | u64 pmcr, val; | |
709 | ||
8d404c4c | 710 | pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); |
051ff581 | 711 | val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; |
24d5950f MZ |
712 | if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { |
713 | kvm_inject_undefined(vcpu); | |
051ff581 | 714 | return false; |
24d5950f | 715 | } |
051ff581 SZ |
716 | |
717 | return true; | |
718 | } | |
719 | ||
720 | static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, | |
721 | struct sys_reg_params *p, | |
722 | const struct sys_reg_desc *r) | |
723 | { | |
a3da9358 | 724 | u64 idx = ~0UL; |
051ff581 SZ |
725 | |
726 | if (r->CRn == 9 && r->CRm == 13) { | |
727 | if (r->Op2 == 2) { | |
728 | /* PMXEVCNTR_EL0 */ | |
d692b8ad SZ |
729 | if (pmu_access_event_counter_el0_disabled(vcpu)) |
730 | return false; | |
731 | ||
8d404c4c | 732 | idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) |
051ff581 SZ |
733 | & ARMV8_PMU_COUNTER_MASK; |
734 | } else if (r->Op2 == 0) { | |
735 | /* PMCCNTR_EL0 */ | |
d692b8ad SZ |
736 | if (pmu_access_cycle_counter_el0_disabled(vcpu)) |
737 | return false; | |
738 | ||
051ff581 | 739 | idx = ARMV8_PMU_CYCLE_IDX; |
051ff581 | 740 | } |
9e3f7a29 WH |
741 | } else if (r->CRn == 0 && r->CRm == 9) { |
742 | /* PMCCNTR */ | |
743 | if (pmu_access_event_counter_el0_disabled(vcpu)) | |
744 | return false; | |
745 | ||
746 | idx = ARMV8_PMU_CYCLE_IDX; | |
051ff581 SZ |
747 | } else if (r->CRn == 14 && (r->CRm & 12) == 8) { |
748 | /* PMEVCNTRn_EL0 */ | |
d692b8ad SZ |
749 | if (pmu_access_event_counter_el0_disabled(vcpu)) |
750 | return false; | |
751 | ||
051ff581 | 752 | idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); |
051ff581 SZ |
753 | } |
754 | ||
a3da9358 MZ |
755 | /* Catch any decoding mistake */ |
756 | WARN_ON(idx == ~0UL); | |
757 | ||
051ff581 SZ |
758 | if (!pmu_counter_idx_valid(vcpu, idx)) |
759 | return false; | |
760 | ||
d692b8ad SZ |
761 | if (p->is_write) { |
762 | if (pmu_access_el0_disabled(vcpu)) | |
763 | return false; | |
764 | ||
051ff581 | 765 | kvm_pmu_set_counter_value(vcpu, idx, p->regval); |
d692b8ad | 766 | } else { |
051ff581 | 767 | p->regval = kvm_pmu_get_counter_value(vcpu, idx); |
d692b8ad | 768 | } |
051ff581 SZ |
769 | |
770 | return true; | |
771 | } | |
772 | ||
9feb21ac SZ |
773 | static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
774 | const struct sys_reg_desc *r) | |
775 | { | |
776 | u64 idx, reg; | |
777 | ||
d692b8ad SZ |
778 | if (pmu_access_el0_disabled(vcpu)) |
779 | return false; | |
780 | ||
9feb21ac SZ |
781 | if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { |
782 | /* PMXEVTYPER_EL0 */ | |
8d404c4c | 783 | idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; |
9feb21ac SZ |
784 | reg = PMEVTYPER0_EL0 + idx; |
785 | } else if (r->CRn == 14 && (r->CRm & 12) == 12) { | |
786 | idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); | |
787 | if (idx == ARMV8_PMU_CYCLE_IDX) | |
788 | reg = PMCCFILTR_EL0; | |
789 | else | |
790 | /* PMEVTYPERn_EL0 */ | |
791 | reg = PMEVTYPER0_EL0 + idx; | |
792 | } else { | |
793 | BUG(); | |
794 | } | |
795 | ||
796 | if (!pmu_counter_idx_valid(vcpu, idx)) | |
797 | return false; | |
798 | ||
799 | if (p->is_write) { | |
800 | kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); | |
8d404c4c | 801 | __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; |
435e53fb | 802 | kvm_vcpu_pmu_restore_guest(vcpu); |
9feb21ac | 803 | } else { |
8d404c4c | 804 | p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; |
9feb21ac SZ |
805 | } |
806 | ||
807 | return true; | |
808 | } | |
809 | ||
96b0eebc SZ |
810 | static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
811 | const struct sys_reg_desc *r) | |
812 | { | |
813 | u64 val, mask; | |
814 | ||
d692b8ad SZ |
815 | if (pmu_access_el0_disabled(vcpu)) |
816 | return false; | |
817 | ||
96b0eebc SZ |
818 | mask = kvm_pmu_valid_counter_mask(vcpu); |
819 | if (p->is_write) { | |
820 | val = p->regval & mask; | |
821 | if (r->Op2 & 0x1) { | |
822 | /* accessing PMCNTENSET_EL0 */ | |
8d404c4c | 823 | __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; |
418e5ca8 | 824 | kvm_pmu_enable_counter_mask(vcpu, val); |
435e53fb | 825 | kvm_vcpu_pmu_restore_guest(vcpu); |
96b0eebc SZ |
826 | } else { |
827 | /* accessing PMCNTENCLR_EL0 */ | |
8d404c4c | 828 | __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; |
418e5ca8 | 829 | kvm_pmu_disable_counter_mask(vcpu, val); |
96b0eebc SZ |
830 | } |
831 | } else { | |
8d404c4c | 832 | p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; |
96b0eebc SZ |
833 | } |
834 | ||
835 | return true; | |
836 | } | |
837 | ||
9db52c78 SZ |
838 | static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
839 | const struct sys_reg_desc *r) | |
840 | { | |
841 | u64 mask = kvm_pmu_valid_counter_mask(vcpu); | |
842 | ||
b0737e99 | 843 | if (check_pmu_access_disabled(vcpu, 0)) |
d692b8ad SZ |
844 | return false; |
845 | ||
9db52c78 SZ |
846 | if (p->is_write) { |
847 | u64 val = p->regval & mask; | |
848 | ||
849 | if (r->Op2 & 0x1) | |
850 | /* accessing PMINTENSET_EL1 */ | |
8d404c4c | 851 | __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; |
9db52c78 SZ |
852 | else |
853 | /* accessing PMINTENCLR_EL1 */ | |
8d404c4c | 854 | __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; |
9db52c78 | 855 | } else { |
8d404c4c | 856 | p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; |
9db52c78 SZ |
857 | } |
858 | ||
859 | return true; | |
860 | } | |
861 | ||
76d883c4 SZ |
862 | static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
863 | const struct sys_reg_desc *r) | |
864 | { | |
865 | u64 mask = kvm_pmu_valid_counter_mask(vcpu); | |
866 | ||
d692b8ad SZ |
867 | if (pmu_access_el0_disabled(vcpu)) |
868 | return false; | |
869 | ||
76d883c4 SZ |
870 | if (p->is_write) { |
871 | if (r->CRm & 0x2) | |
872 | /* accessing PMOVSSET_EL0 */ | |
8d404c4c | 873 | __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); |
76d883c4 SZ |
874 | else |
875 | /* accessing PMOVSCLR_EL0 */ | |
8d404c4c | 876 | __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); |
76d883c4 | 877 | } else { |
8d404c4c | 878 | p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; |
76d883c4 SZ |
879 | } |
880 | ||
881 | return true; | |
882 | } | |
883 | ||
7a0adc70 SZ |
884 | static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
885 | const struct sys_reg_desc *r) | |
886 | { | |
887 | u64 mask; | |
888 | ||
e0443230 | 889 | if (!p->is_write) |
e7f1d1ee | 890 | return read_from_write_only(vcpu, p, r); |
e0443230 | 891 | |
d692b8ad SZ |
892 | if (pmu_write_swinc_el0_disabled(vcpu)) |
893 | return false; | |
894 | ||
e0443230 MZ |
895 | mask = kvm_pmu_valid_counter_mask(vcpu); |
896 | kvm_pmu_software_increment(vcpu, p->regval & mask); | |
897 | return true; | |
7a0adc70 SZ |
898 | } |
899 | ||
d692b8ad SZ |
900 | static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
901 | const struct sys_reg_desc *r) | |
902 | { | |
b0737e99 MZ |
903 | if (!kvm_vcpu_has_pmu(vcpu)) { |
904 | kvm_inject_undefined(vcpu); | |
905 | return false; | |
906 | } | |
d692b8ad SZ |
907 | |
908 | if (p->is_write) { | |
9008c235 MZ |
909 | if (!vcpu_mode_priv(vcpu)) { |
910 | kvm_inject_undefined(vcpu); | |
d692b8ad | 911 | return false; |
9008c235 | 912 | } |
d692b8ad | 913 | |
8d404c4c CD |
914 | __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = |
915 | p->regval & ARMV8_PMU_USERENR_MASK; | |
d692b8ad | 916 | } else { |
8d404c4c | 917 | p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) |
d692b8ad SZ |
918 | & ARMV8_PMU_USERENR_MASK; |
919 | } | |
920 | ||
921 | return true; | |
922 | } | |
923 | ||
09838de9 MZ |
924 | #define reg_to_encoding(x) \ |
925 | sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ | |
926 | (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2); | |
927 | ||
0c557ed4 MZ |
928 | /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ |
929 | #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ | |
ee1b64e6 | 930 | { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ |
03fdfb26 | 931 | trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ |
ee1b64e6 | 932 | { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ |
03fdfb26 | 933 | trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ |
ee1b64e6 | 934 | { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ |
03fdfb26 | 935 | trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ |
ee1b64e6 | 936 | { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ |
03fdfb26 | 937 | trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } |
0c557ed4 | 938 | |
051ff581 SZ |
939 | /* Macro to expand the PMEVCNTRn_EL0 register */ |
940 | #define PMU_PMEVCNTR_EL0(n) \ | |
174ed3e4 | 941 | { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \ |
051ff581 SZ |
942 | access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), } |
943 | ||
9feb21ac SZ |
944 | /* Macro to expand the PMEVTYPERn_EL0 register */ |
945 | #define PMU_PMEVTYPER_EL0(n) \ | |
174ed3e4 | 946 | { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \ |
9feb21ac SZ |
947 | access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), } |
948 | ||
338b1793 MZ |
949 | static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
950 | const struct sys_reg_desc *r) | |
4fcdf106 IV |
951 | { |
952 | kvm_inject_undefined(vcpu); | |
953 | ||
954 | return false; | |
955 | } | |
956 | ||
957 | /* Macro to expand the AMU counter and type registers*/ | |
338b1793 MZ |
958 | #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } |
959 | #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } | |
960 | #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } | |
961 | #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } | |
384b40ca MR |
962 | |
963 | static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, | |
964 | const struct sys_reg_desc *rd) | |
965 | { | |
01fe5ace | 966 | return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; |
384b40ca MR |
967 | } |
968 | ||
338b1793 MZ |
969 | /* |
970 | * If we land here on a PtrAuth access, that is because we didn't | |
971 | * fixup the access on exit by allowing the PtrAuth sysregs. The only | |
972 | * way this happens is when the guest does not have PtrAuth support | |
973 | * enabled. | |
974 | */ | |
384b40ca | 975 | #define __PTRAUTH_KEY(k) \ |
338b1793 | 976 | { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ |
384b40ca MR |
977 | .visibility = ptrauth_visibility} |
978 | ||
979 | #define PTRAUTH_KEY(k) \ | |
980 | __PTRAUTH_KEY(k ## KEYLO_EL1), \ | |
981 | __PTRAUTH_KEY(k ## KEYHI_EL1) | |
982 | ||
84135d3d AP |
983 | static bool access_arch_timer(struct kvm_vcpu *vcpu, |
984 | struct sys_reg_params *p, | |
985 | const struct sys_reg_desc *r) | |
c9a3c58f | 986 | { |
84135d3d AP |
987 | enum kvm_arch_timers tmr; |
988 | enum kvm_arch_timer_regs treg; | |
989 | u64 reg = reg_to_encoding(r); | |
7b6b4631 | 990 | |
84135d3d AP |
991 | switch (reg) { |
992 | case SYS_CNTP_TVAL_EL0: | |
993 | case SYS_AARCH32_CNTP_TVAL: | |
994 | tmr = TIMER_PTIMER; | |
995 | treg = TIMER_REG_TVAL; | |
996 | break; | |
997 | case SYS_CNTP_CTL_EL0: | |
998 | case SYS_AARCH32_CNTP_CTL: | |
999 | tmr = TIMER_PTIMER; | |
1000 | treg = TIMER_REG_CTL; | |
1001 | break; | |
1002 | case SYS_CNTP_CVAL_EL0: | |
1003 | case SYS_AARCH32_CNTP_CVAL: | |
1004 | tmr = TIMER_PTIMER; | |
1005 | treg = TIMER_REG_CVAL; | |
1006 | break; | |
1007 | default: | |
1008 | BUG(); | |
c1b135af | 1009 | } |
7b6b4631 | 1010 | |
7b6b4631 | 1011 | if (p->is_write) |
84135d3d | 1012 | kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); |
7b6b4631 | 1013 | else |
84135d3d | 1014 | p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); |
7b6b4631 | 1015 | |
c9a3c58f JL |
1016 | return true; |
1017 | } | |
1018 | ||
93390c0a | 1019 | /* Read a sanitised cpufeature ID register by sys_reg_desc */ |
1c199913 DM |
1020 | static u64 read_id_reg(const struct kvm_vcpu *vcpu, |
1021 | struct sys_reg_desc const *r, bool raz) | |
93390c0a DM |
1022 | { |
1023 | u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, | |
1024 | (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); | |
07d79fe7 | 1025 | u64 val = raz ? 0 : read_sanitised_ftr_reg(id); |
93390c0a | 1026 | |
4fcdf106 IV |
1027 | if (id == SYS_ID_AA64PFR0_EL1) { |
1028 | if (!vcpu_has_sve(vcpu)) | |
1029 | val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); | |
1030 | val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); | |
23711a5e MZ |
1031 | val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT); |
1032 | val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT); | |
4f1df628 MZ |
1033 | val &= ~(0xfUL << ID_AA64PFR0_CSV3_SHIFT); |
1034 | val |= ((u64)vcpu->kvm->arch.pfr0_csv3 << ID_AA64PFR0_CSV3_SHIFT); | |
2ac638fc CM |
1035 | } else if (id == SYS_ID_AA64PFR1_EL1) { |
1036 | val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT); | |
384b40ca | 1037 | } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { |
9eecfc22 KM |
1038 | val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | |
1039 | (0xfUL << ID_AA64ISAR1_API_SHIFT) | | |
1040 | (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | | |
1041 | (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); | |
c854188e | 1042 | } else if (id == SYS_ID_AA64DFR0_EL1) { |
04355e41 MZ |
1043 | u64 cap = 0; |
1044 | ||
c854188e | 1045 | /* Limit guests to PMUv3 for ARMv8.1 */ |
04355e41 MZ |
1046 | if (kvm_vcpu_has_pmu(vcpu)) |
1047 | cap = ID_AA64DFR0_PMUVER_8_1; | |
1048 | ||
c854188e AM |
1049 | val = cpuid_feature_cap_perfmon_field(val, |
1050 | ID_AA64DFR0_PMUVER_SHIFT, | |
04355e41 | 1051 | cap); |
c854188e AM |
1052 | } else if (id == SYS_ID_DFR0_EL1) { |
1053 | /* Limit guests to PMUv3 for ARMv8.1 */ | |
1054 | val = cpuid_feature_cap_perfmon_field(val, | |
1055 | ID_DFR0_PERFMON_SHIFT, | |
1056 | ID_DFR0_PERFMON_8_1); | |
07d79fe7 DM |
1057 | } |
1058 | ||
1059 | return val; | |
93390c0a DM |
1060 | } |
1061 | ||
912dee57 AJ |
1062 | static unsigned int id_visibility(const struct kvm_vcpu *vcpu, |
1063 | const struct sys_reg_desc *r) | |
1064 | { | |
c512298e AJ |
1065 | u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, |
1066 | (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); | |
1067 | ||
1068 | switch (id) { | |
1069 | case SYS_ID_AA64ZFR0_EL1: | |
1070 | if (!vcpu_has_sve(vcpu)) | |
1071 | return REG_RAZ; | |
1072 | break; | |
1073 | } | |
1074 | ||
912dee57 AJ |
1075 | return 0; |
1076 | } | |
1077 | ||
93390c0a DM |
1078 | /* cpufeature ID register access trap handlers */ |
1079 | ||
1080 | static bool __access_id_reg(struct kvm_vcpu *vcpu, | |
1081 | struct sys_reg_params *p, | |
1082 | const struct sys_reg_desc *r, | |
1083 | bool raz) | |
1084 | { | |
1085 | if (p->is_write) | |
1086 | return write_to_read_only(vcpu, p, r); | |
1087 | ||
1c199913 | 1088 | p->regval = read_id_reg(vcpu, r, raz); |
93390c0a DM |
1089 | return true; |
1090 | } | |
1091 | ||
1092 | static bool access_id_reg(struct kvm_vcpu *vcpu, | |
1093 | struct sys_reg_params *p, | |
1094 | const struct sys_reg_desc *r) | |
1095 | { | |
912dee57 AJ |
1096 | bool raz = sysreg_visible_as_raz(vcpu, r); |
1097 | ||
1098 | return __access_id_reg(vcpu, p, r, raz); | |
93390c0a DM |
1099 | } |
1100 | ||
1101 | static bool access_raz_id_reg(struct kvm_vcpu *vcpu, | |
1102 | struct sys_reg_params *p, | |
1103 | const struct sys_reg_desc *r) | |
1104 | { | |
1105 | return __access_id_reg(vcpu, p, r, true); | |
1106 | } | |
1107 | ||
1108 | static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); | |
1109 | static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); | |
1110 | static u64 sys_reg_to_index(const struct sys_reg_desc *reg); | |
1111 | ||
73433762 DM |
1112 | /* Visibility overrides for SVE-specific control registers */ |
1113 | static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, | |
1114 | const struct sys_reg_desc *rd) | |
1115 | { | |
1116 | if (vcpu_has_sve(vcpu)) | |
1117 | return 0; | |
1118 | ||
01fe5ace | 1119 | return REG_HIDDEN; |
73433762 DM |
1120 | } |
1121 | ||
23711a5e MZ |
1122 | static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, |
1123 | const struct sys_reg_desc *rd, | |
1124 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1125 | { | |
1126 | const u64 id = sys_reg_to_index(rd); | |
4f1df628 | 1127 | u8 csv2, csv3; |
23711a5e MZ |
1128 | int err; |
1129 | u64 val; | |
23711a5e MZ |
1130 | |
1131 | err = reg_from_user(&val, uaddr, id); | |
1132 | if (err) | |
1133 | return err; | |
1134 | ||
1135 | /* | |
1136 | * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as | |
1137 | * it doesn't promise more than what is actually provided (the | |
1138 | * guest could otherwise be covered in ectoplasmic residue). | |
1139 | */ | |
1140 | csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT); | |
1141 | if (csv2 > 1 || | |
1142 | (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) | |
1143 | return -EINVAL; | |
1144 | ||
4f1df628 MZ |
1145 | /* Same thing for CSV3 */ |
1146 | csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT); | |
1147 | if (csv3 > 1 || | |
1148 | (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) | |
1149 | return -EINVAL; | |
1150 | ||
1151 | /* We can only differ with CSV[23], and anything else is an error */ | |
23711a5e | 1152 | val ^= read_id_reg(vcpu, rd, false); |
4f1df628 MZ |
1153 | val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) | |
1154 | (0xFUL << ID_AA64PFR0_CSV3_SHIFT)); | |
23711a5e MZ |
1155 | if (val) |
1156 | return -EINVAL; | |
1157 | ||
1158 | vcpu->kvm->arch.pfr0_csv2 = csv2; | |
4f1df628 | 1159 | vcpu->kvm->arch.pfr0_csv3 = csv3 ; |
23711a5e MZ |
1160 | |
1161 | return 0; | |
1162 | } | |
1163 | ||
93390c0a DM |
1164 | /* |
1165 | * cpufeature ID register user accessors | |
1166 | * | |
1167 | * For now, these registers are immutable for userspace, so no values | |
1168 | * are stored, and for set_id_reg() we don't allow the effective value | |
1169 | * to be changed. | |
1170 | */ | |
1c199913 DM |
1171 | static int __get_id_reg(const struct kvm_vcpu *vcpu, |
1172 | const struct sys_reg_desc *rd, void __user *uaddr, | |
93390c0a DM |
1173 | bool raz) |
1174 | { | |
1175 | const u64 id = sys_reg_to_index(rd); | |
1c199913 | 1176 | const u64 val = read_id_reg(vcpu, rd, raz); |
93390c0a DM |
1177 | |
1178 | return reg_to_user(uaddr, &val, id); | |
1179 | } | |
1180 | ||
1c199913 DM |
1181 | static int __set_id_reg(const struct kvm_vcpu *vcpu, |
1182 | const struct sys_reg_desc *rd, void __user *uaddr, | |
93390c0a DM |
1183 | bool raz) |
1184 | { | |
1185 | const u64 id = sys_reg_to_index(rd); | |
1186 | int err; | |
1187 | u64 val; | |
1188 | ||
1189 | err = reg_from_user(&val, uaddr, id); | |
1190 | if (err) | |
1191 | return err; | |
1192 | ||
1193 | /* This is what we mean by invariant: you can't change it. */ | |
1c199913 | 1194 | if (val != read_id_reg(vcpu, rd, raz)) |
93390c0a DM |
1195 | return -EINVAL; |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
1201 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1202 | { | |
912dee57 AJ |
1203 | bool raz = sysreg_visible_as_raz(vcpu, rd); |
1204 | ||
1205 | return __get_id_reg(vcpu, rd, uaddr, raz); | |
93390c0a DM |
1206 | } |
1207 | ||
1208 | static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
1209 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1210 | { | |
912dee57 AJ |
1211 | bool raz = sysreg_visible_as_raz(vcpu, rd); |
1212 | ||
1213 | return __set_id_reg(vcpu, rd, uaddr, raz); | |
93390c0a DM |
1214 | } |
1215 | ||
1216 | static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
1217 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1218 | { | |
1c199913 | 1219 | return __get_id_reg(vcpu, rd, uaddr, true); |
93390c0a DM |
1220 | } |
1221 | ||
1222 | static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
1223 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1224 | { | |
1c199913 | 1225 | return __set_id_reg(vcpu, rd, uaddr, true); |
93390c0a DM |
1226 | } |
1227 | ||
f7f2b15c AB |
1228 | static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1229 | const struct sys_reg_desc *r) | |
1230 | { | |
1231 | if (p->is_write) | |
1232 | return write_to_read_only(vcpu, p, r); | |
1233 | ||
1234 | p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); | |
1235 | return true; | |
1236 | } | |
1237 | ||
1238 | static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, | |
1239 | const struct sys_reg_desc *r) | |
1240 | { | |
1241 | if (p->is_write) | |
1242 | return write_to_read_only(vcpu, p, r); | |
1243 | ||
1244 | p->regval = read_sysreg(clidr_el1); | |
1245 | return true; | |
1246 | } | |
1247 | ||
1248 | static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, | |
1249 | const struct sys_reg_desc *r) | |
1250 | { | |
7c582bf4 JM |
1251 | int reg = r->reg; |
1252 | ||
f7f2b15c | 1253 | if (p->is_write) |
7c582bf4 | 1254 | vcpu_write_sys_reg(vcpu, p->regval, reg); |
f7f2b15c | 1255 | else |
7c582bf4 | 1256 | p->regval = vcpu_read_sys_reg(vcpu, reg); |
f7f2b15c AB |
1257 | return true; |
1258 | } | |
1259 | ||
1260 | static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, | |
1261 | const struct sys_reg_desc *r) | |
1262 | { | |
1263 | u32 csselr; | |
1264 | ||
1265 | if (p->is_write) | |
1266 | return write_to_read_only(vcpu, p, r); | |
1267 | ||
1268 | csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); | |
1269 | p->regval = get_ccsidr(csselr); | |
793acf87 AB |
1270 | |
1271 | /* | |
1272 | * Guests should not be doing cache operations by set/way at all, and | |
1273 | * for this reason, we trap them and attempt to infer the intent, so | |
1274 | * that we can flush the entire guest's address space at the appropriate | |
1275 | * time. | |
1276 | * To prevent this trapping from causing performance problems, let's | |
1277 | * expose the geometry of all data and unified caches (which are | |
1278 | * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. | |
1279 | * [If guests should attempt to infer aliasing properties from the | |
1280 | * geometry (which is not permitted by the architecture), they would | |
1281 | * only do so for virtually indexed caches.] | |
1282 | */ | |
1283 | if (!(csselr & 1)) // data or unified cache | |
1284 | p->regval &= ~GENMASK(27, 3); | |
f7f2b15c AB |
1285 | return true; |
1286 | } | |
1287 | ||
93390c0a DM |
1288 | /* sys_reg_desc initialiser for known cpufeature ID registers */ |
1289 | #define ID_SANITISED(name) { \ | |
1290 | SYS_DESC(SYS_##name), \ | |
1291 | .access = access_id_reg, \ | |
1292 | .get_user = get_id_reg, \ | |
1293 | .set_user = set_id_reg, \ | |
912dee57 | 1294 | .visibility = id_visibility, \ |
93390c0a DM |
1295 | } |
1296 | ||
1297 | /* | |
1298 | * sys_reg_desc initialiser for architecturally unallocated cpufeature ID | |
1299 | * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 | |
1300 | * (1 <= crm < 8, 0 <= Op2 < 8). | |
1301 | */ | |
1302 | #define ID_UNALLOCATED(crm, op2) { \ | |
1303 | Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ | |
1304 | .access = access_raz_id_reg, \ | |
1305 | .get_user = get_raz_id_reg, \ | |
1306 | .set_user = set_raz_id_reg, \ | |
1307 | } | |
1308 | ||
1309 | /* | |
1310 | * sys_reg_desc initialiser for known ID registers that we hide from guests. | |
1311 | * For now, these are exposed just like unallocated ID regs: they appear | |
1312 | * RAZ for the guest. | |
1313 | */ | |
1314 | #define ID_HIDDEN(name) { \ | |
1315 | SYS_DESC(SYS_##name), \ | |
1316 | .access = access_raz_id_reg, \ | |
1317 | .get_user = get_raz_id_reg, \ | |
1318 | .set_user = set_raz_id_reg, \ | |
1319 | } | |
1320 | ||
7c8c5e6a MZ |
1321 | /* |
1322 | * Architected system registers. | |
1323 | * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 | |
7609c125 | 1324 | * |
0c557ed4 MZ |
1325 | * Debug handling: We do trap most, if not all debug related system |
1326 | * registers. The implementation is good enough to ensure that a guest | |
1327 | * can use these with minimal performance degradation. The drawback is | |
1328 | * that we don't implement any of the external debug, none of the | |
1329 | * OSlock protocol. This should be revisited if we ever encounter a | |
1330 | * more demanding guest... | |
7c8c5e6a MZ |
1331 | */ |
1332 | static const struct sys_reg_desc sys_reg_descs[] = { | |
7606e078 MR |
1333 | { SYS_DESC(SYS_DC_ISW), access_dcsw }, |
1334 | { SYS_DESC(SYS_DC_CSW), access_dcsw }, | |
1335 | { SYS_DESC(SYS_DC_CISW), access_dcsw }, | |
7c8c5e6a | 1336 | |
0c557ed4 MZ |
1337 | DBG_BCR_BVR_WCR_WVR_EL1(0), |
1338 | DBG_BCR_BVR_WCR_WVR_EL1(1), | |
ee1b64e6 MR |
1339 | { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, |
1340 | { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, | |
0c557ed4 MZ |
1341 | DBG_BCR_BVR_WCR_WVR_EL1(2), |
1342 | DBG_BCR_BVR_WCR_WVR_EL1(3), | |
1343 | DBG_BCR_BVR_WCR_WVR_EL1(4), | |
1344 | DBG_BCR_BVR_WCR_WVR_EL1(5), | |
1345 | DBG_BCR_BVR_WCR_WVR_EL1(6), | |
1346 | DBG_BCR_BVR_WCR_WVR_EL1(7), | |
1347 | DBG_BCR_BVR_WCR_WVR_EL1(8), | |
1348 | DBG_BCR_BVR_WCR_WVR_EL1(9), | |
1349 | DBG_BCR_BVR_WCR_WVR_EL1(10), | |
1350 | DBG_BCR_BVR_WCR_WVR_EL1(11), | |
1351 | DBG_BCR_BVR_WCR_WVR_EL1(12), | |
1352 | DBG_BCR_BVR_WCR_WVR_EL1(13), | |
1353 | DBG_BCR_BVR_WCR_WVR_EL1(14), | |
1354 | DBG_BCR_BVR_WCR_WVR_EL1(15), | |
1355 | ||
ee1b64e6 MR |
1356 | { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, |
1357 | { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, | |
1358 | { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, | |
1359 | { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, | |
1360 | { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, | |
1361 | { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, | |
1362 | { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, | |
1363 | { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, | |
1364 | ||
1365 | { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, | |
1366 | { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, | |
1367 | // DBGDTR[TR]X_EL0 share the same encoding | |
1368 | { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, | |
1369 | ||
1370 | { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, | |
62a89c44 | 1371 | |
851050a5 | 1372 | { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, |
93390c0a DM |
1373 | |
1374 | /* | |
1375 | * ID regs: all ID_SANITISED() entries here must have corresponding | |
1376 | * entries in arm64_ftr_regs[]. | |
1377 | */ | |
1378 | ||
1379 | /* AArch64 mappings of the AArch32 ID registers */ | |
1380 | /* CRm=1 */ | |
1381 | ID_SANITISED(ID_PFR0_EL1), | |
1382 | ID_SANITISED(ID_PFR1_EL1), | |
1383 | ID_SANITISED(ID_DFR0_EL1), | |
1384 | ID_HIDDEN(ID_AFR0_EL1), | |
1385 | ID_SANITISED(ID_MMFR0_EL1), | |
1386 | ID_SANITISED(ID_MMFR1_EL1), | |
1387 | ID_SANITISED(ID_MMFR2_EL1), | |
1388 | ID_SANITISED(ID_MMFR3_EL1), | |
1389 | ||
1390 | /* CRm=2 */ | |
1391 | ID_SANITISED(ID_ISAR0_EL1), | |
1392 | ID_SANITISED(ID_ISAR1_EL1), | |
1393 | ID_SANITISED(ID_ISAR2_EL1), | |
1394 | ID_SANITISED(ID_ISAR3_EL1), | |
1395 | ID_SANITISED(ID_ISAR4_EL1), | |
1396 | ID_SANITISED(ID_ISAR5_EL1), | |
1397 | ID_SANITISED(ID_MMFR4_EL1), | |
8e3747be | 1398 | ID_SANITISED(ID_ISAR6_EL1), |
93390c0a DM |
1399 | |
1400 | /* CRm=3 */ | |
1401 | ID_SANITISED(MVFR0_EL1), | |
1402 | ID_SANITISED(MVFR1_EL1), | |
1403 | ID_SANITISED(MVFR2_EL1), | |
1404 | ID_UNALLOCATED(3,3), | |
16824085 | 1405 | ID_SANITISED(ID_PFR2_EL1), |
dd35ec07 | 1406 | ID_HIDDEN(ID_DFR1_EL1), |
152accf8 | 1407 | ID_SANITISED(ID_MMFR5_EL1), |
93390c0a DM |
1408 | ID_UNALLOCATED(3,7), |
1409 | ||
1410 | /* AArch64 ID registers */ | |
1411 | /* CRm=4 */ | |
23711a5e MZ |
1412 | { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, |
1413 | .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, | |
93390c0a DM |
1414 | ID_SANITISED(ID_AA64PFR1_EL1), |
1415 | ID_UNALLOCATED(4,2), | |
1416 | ID_UNALLOCATED(4,3), | |
c512298e | 1417 | ID_SANITISED(ID_AA64ZFR0_EL1), |
93390c0a DM |
1418 | ID_UNALLOCATED(4,5), |
1419 | ID_UNALLOCATED(4,6), | |
1420 | ID_UNALLOCATED(4,7), | |
1421 | ||
1422 | /* CRm=5 */ | |
1423 | ID_SANITISED(ID_AA64DFR0_EL1), | |
1424 | ID_SANITISED(ID_AA64DFR1_EL1), | |
1425 | ID_UNALLOCATED(5,2), | |
1426 | ID_UNALLOCATED(5,3), | |
1427 | ID_HIDDEN(ID_AA64AFR0_EL1), | |
1428 | ID_HIDDEN(ID_AA64AFR1_EL1), | |
1429 | ID_UNALLOCATED(5,6), | |
1430 | ID_UNALLOCATED(5,7), | |
1431 | ||
1432 | /* CRm=6 */ | |
1433 | ID_SANITISED(ID_AA64ISAR0_EL1), | |
1434 | ID_SANITISED(ID_AA64ISAR1_EL1), | |
1435 | ID_UNALLOCATED(6,2), | |
1436 | ID_UNALLOCATED(6,3), | |
1437 | ID_UNALLOCATED(6,4), | |
1438 | ID_UNALLOCATED(6,5), | |
1439 | ID_UNALLOCATED(6,6), | |
1440 | ID_UNALLOCATED(6,7), | |
1441 | ||
1442 | /* CRm=7 */ | |
1443 | ID_SANITISED(ID_AA64MMFR0_EL1), | |
1444 | ID_SANITISED(ID_AA64MMFR1_EL1), | |
1445 | ID_SANITISED(ID_AA64MMFR2_EL1), | |
1446 | ID_UNALLOCATED(7,3), | |
1447 | ID_UNALLOCATED(7,4), | |
1448 | ID_UNALLOCATED(7,5), | |
1449 | ID_UNALLOCATED(7,6), | |
1450 | ID_UNALLOCATED(7,7), | |
1451 | ||
851050a5 | 1452 | { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, |
af473829 | 1453 | { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, |
851050a5 | 1454 | { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, |
2ac638fc | 1455 | |
338b1793 MZ |
1456 | { SYS_DESC(SYS_RGSR_EL1), undef_access }, |
1457 | { SYS_DESC(SYS_GCR_EL1), undef_access }, | |
2ac638fc | 1458 | |
73433762 | 1459 | { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, |
851050a5 MR |
1460 | { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, |
1461 | { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, | |
1462 | { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, | |
1463 | ||
384b40ca MR |
1464 | PTRAUTH_KEY(APIA), |
1465 | PTRAUTH_KEY(APIB), | |
1466 | PTRAUTH_KEY(APDA), | |
1467 | PTRAUTH_KEY(APDB), | |
1468 | PTRAUTH_KEY(APGA), | |
1469 | ||
851050a5 MR |
1470 | { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, |
1471 | { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, | |
1472 | { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, | |
558daf69 DG |
1473 | |
1474 | { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, | |
1475 | { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, | |
1476 | { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, | |
1477 | { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, | |
1478 | { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, | |
1479 | { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, | |
1480 | { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, | |
1481 | { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, | |
1482 | ||
338b1793 MZ |
1483 | { SYS_DESC(SYS_TFSR_EL1), undef_access }, |
1484 | { SYS_DESC(SYS_TFSRE0_EL1), undef_access }, | |
2ac638fc | 1485 | |
851050a5 MR |
1486 | { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, |
1487 | { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, | |
7c8c5e6a | 1488 | |
174ed3e4 | 1489 | { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, |
7ccadf23 | 1490 | { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, |
7c8c5e6a | 1491 | |
851050a5 MR |
1492 | { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, |
1493 | { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, | |
7c8c5e6a | 1494 | |
22925521 MZ |
1495 | { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, |
1496 | { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, | |
1497 | { SYS_DESC(SYS_LORN_EL1), trap_loregion }, | |
1498 | { SYS_DESC(SYS_LORC_EL1), trap_loregion }, | |
1499 | { SYS_DESC(SYS_LORID_EL1), trap_loregion }, | |
cc33c4e2 | 1500 | |
851050a5 | 1501 | { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, |
c773ae2b | 1502 | { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, |
db7dedd0 | 1503 | |
7b1dba1f | 1504 | { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, |
e7f1d1ee | 1505 | { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, |
7b1dba1f | 1506 | { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, |
e7f1d1ee | 1507 | { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, |
7b1dba1f | 1508 | { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, |
e804d208 | 1509 | { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, |
03bd646d MZ |
1510 | { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, |
1511 | { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, | |
7b1dba1f | 1512 | { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, |
e7f1d1ee | 1513 | { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, |
7b1dba1f | 1514 | { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, |
e804d208 | 1515 | { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, |
db7dedd0 | 1516 | |
851050a5 MR |
1517 | { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, |
1518 | { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, | |
7c8c5e6a | 1519 | |
ed4ffaf4 MZ |
1520 | { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, |
1521 | ||
851050a5 | 1522 | { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, |
7c8c5e6a | 1523 | |
f7f2b15c AB |
1524 | { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, |
1525 | { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, | |
1526 | { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, | |
1527 | { SYS_DESC(SYS_CTR_EL0), access_ctr }, | |
7c8c5e6a | 1528 | |
03fdfb26 | 1529 | { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 }, |
174ed3e4 | 1530 | { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, |
7ccadf23 MZ |
1531 | { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, |
1532 | { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, | |
174ed3e4 MR |
1533 | { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 }, |
1534 | { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 }, | |
1535 | { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid }, | |
1536 | { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid }, | |
1537 | { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 }, | |
1538 | { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper }, | |
1539 | { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr }, | |
1540 | /* | |
1541 | * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero | |
d692b8ad SZ |
1542 | * in 32bit mode. Here we choose to reset it as zero for consistency. |
1543 | */ | |
174ed3e4 MR |
1544 | { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 }, |
1545 | { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, | |
7c8c5e6a | 1546 | |
851050a5 MR |
1547 | { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, |
1548 | { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, | |
4fcdf106 | 1549 | |
ed4ffaf4 MZ |
1550 | { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, |
1551 | ||
338b1793 MZ |
1552 | { SYS_DESC(SYS_AMCR_EL0), undef_access }, |
1553 | { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, | |
1554 | { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, | |
1555 | { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, | |
1556 | { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, | |
1557 | { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, | |
1558 | { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, | |
1559 | { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, | |
4fcdf106 IV |
1560 | AMU_AMEVCNTR0_EL0(0), |
1561 | AMU_AMEVCNTR0_EL0(1), | |
1562 | AMU_AMEVCNTR0_EL0(2), | |
1563 | AMU_AMEVCNTR0_EL0(3), | |
1564 | AMU_AMEVCNTR0_EL0(4), | |
1565 | AMU_AMEVCNTR0_EL0(5), | |
1566 | AMU_AMEVCNTR0_EL0(6), | |
1567 | AMU_AMEVCNTR0_EL0(7), | |
1568 | AMU_AMEVCNTR0_EL0(8), | |
1569 | AMU_AMEVCNTR0_EL0(9), | |
1570 | AMU_AMEVCNTR0_EL0(10), | |
1571 | AMU_AMEVCNTR0_EL0(11), | |
1572 | AMU_AMEVCNTR0_EL0(12), | |
1573 | AMU_AMEVCNTR0_EL0(13), | |
1574 | AMU_AMEVCNTR0_EL0(14), | |
1575 | AMU_AMEVCNTR0_EL0(15), | |
493cf9b7 VM |
1576 | AMU_AMEVTYPER0_EL0(0), |
1577 | AMU_AMEVTYPER0_EL0(1), | |
1578 | AMU_AMEVTYPER0_EL0(2), | |
1579 | AMU_AMEVTYPER0_EL0(3), | |
1580 | AMU_AMEVTYPER0_EL0(4), | |
1581 | AMU_AMEVTYPER0_EL0(5), | |
1582 | AMU_AMEVTYPER0_EL0(6), | |
1583 | AMU_AMEVTYPER0_EL0(7), | |
1584 | AMU_AMEVTYPER0_EL0(8), | |
1585 | AMU_AMEVTYPER0_EL0(9), | |
1586 | AMU_AMEVTYPER0_EL0(10), | |
1587 | AMU_AMEVTYPER0_EL0(11), | |
1588 | AMU_AMEVTYPER0_EL0(12), | |
1589 | AMU_AMEVTYPER0_EL0(13), | |
1590 | AMU_AMEVTYPER0_EL0(14), | |
1591 | AMU_AMEVTYPER0_EL0(15), | |
4fcdf106 IV |
1592 | AMU_AMEVCNTR1_EL0(0), |
1593 | AMU_AMEVCNTR1_EL0(1), | |
1594 | AMU_AMEVCNTR1_EL0(2), | |
1595 | AMU_AMEVCNTR1_EL0(3), | |
1596 | AMU_AMEVCNTR1_EL0(4), | |
1597 | AMU_AMEVCNTR1_EL0(5), | |
1598 | AMU_AMEVCNTR1_EL0(6), | |
1599 | AMU_AMEVCNTR1_EL0(7), | |
1600 | AMU_AMEVCNTR1_EL0(8), | |
1601 | AMU_AMEVCNTR1_EL0(9), | |
1602 | AMU_AMEVCNTR1_EL0(10), | |
1603 | AMU_AMEVCNTR1_EL0(11), | |
1604 | AMU_AMEVCNTR1_EL0(12), | |
1605 | AMU_AMEVCNTR1_EL0(13), | |
1606 | AMU_AMEVCNTR1_EL0(14), | |
1607 | AMU_AMEVCNTR1_EL0(15), | |
493cf9b7 VM |
1608 | AMU_AMEVTYPER1_EL0(0), |
1609 | AMU_AMEVTYPER1_EL0(1), | |
1610 | AMU_AMEVTYPER1_EL0(2), | |
1611 | AMU_AMEVTYPER1_EL0(3), | |
1612 | AMU_AMEVTYPER1_EL0(4), | |
1613 | AMU_AMEVTYPER1_EL0(5), | |
1614 | AMU_AMEVTYPER1_EL0(6), | |
1615 | AMU_AMEVTYPER1_EL0(7), | |
1616 | AMU_AMEVTYPER1_EL0(8), | |
1617 | AMU_AMEVTYPER1_EL0(9), | |
1618 | AMU_AMEVTYPER1_EL0(10), | |
1619 | AMU_AMEVTYPER1_EL0(11), | |
1620 | AMU_AMEVTYPER1_EL0(12), | |
1621 | AMU_AMEVTYPER1_EL0(13), | |
1622 | AMU_AMEVTYPER1_EL0(14), | |
1623 | AMU_AMEVTYPER1_EL0(15), | |
62a89c44 | 1624 | |
84135d3d AP |
1625 | { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, |
1626 | { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, | |
1627 | { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, | |
c9a3c58f | 1628 | |
051ff581 SZ |
1629 | /* PMEVCNTRn_EL0 */ |
1630 | PMU_PMEVCNTR_EL0(0), | |
1631 | PMU_PMEVCNTR_EL0(1), | |
1632 | PMU_PMEVCNTR_EL0(2), | |
1633 | PMU_PMEVCNTR_EL0(3), | |
1634 | PMU_PMEVCNTR_EL0(4), | |
1635 | PMU_PMEVCNTR_EL0(5), | |
1636 | PMU_PMEVCNTR_EL0(6), | |
1637 | PMU_PMEVCNTR_EL0(7), | |
1638 | PMU_PMEVCNTR_EL0(8), | |
1639 | PMU_PMEVCNTR_EL0(9), | |
1640 | PMU_PMEVCNTR_EL0(10), | |
1641 | PMU_PMEVCNTR_EL0(11), | |
1642 | PMU_PMEVCNTR_EL0(12), | |
1643 | PMU_PMEVCNTR_EL0(13), | |
1644 | PMU_PMEVCNTR_EL0(14), | |
1645 | PMU_PMEVCNTR_EL0(15), | |
1646 | PMU_PMEVCNTR_EL0(16), | |
1647 | PMU_PMEVCNTR_EL0(17), | |
1648 | PMU_PMEVCNTR_EL0(18), | |
1649 | PMU_PMEVCNTR_EL0(19), | |
1650 | PMU_PMEVCNTR_EL0(20), | |
1651 | PMU_PMEVCNTR_EL0(21), | |
1652 | PMU_PMEVCNTR_EL0(22), | |
1653 | PMU_PMEVCNTR_EL0(23), | |
1654 | PMU_PMEVCNTR_EL0(24), | |
1655 | PMU_PMEVCNTR_EL0(25), | |
1656 | PMU_PMEVCNTR_EL0(26), | |
1657 | PMU_PMEVCNTR_EL0(27), | |
1658 | PMU_PMEVCNTR_EL0(28), | |
1659 | PMU_PMEVCNTR_EL0(29), | |
1660 | PMU_PMEVCNTR_EL0(30), | |
9feb21ac SZ |
1661 | /* PMEVTYPERn_EL0 */ |
1662 | PMU_PMEVTYPER_EL0(0), | |
1663 | PMU_PMEVTYPER_EL0(1), | |
1664 | PMU_PMEVTYPER_EL0(2), | |
1665 | PMU_PMEVTYPER_EL0(3), | |
1666 | PMU_PMEVTYPER_EL0(4), | |
1667 | PMU_PMEVTYPER_EL0(5), | |
1668 | PMU_PMEVTYPER_EL0(6), | |
1669 | PMU_PMEVTYPER_EL0(7), | |
1670 | PMU_PMEVTYPER_EL0(8), | |
1671 | PMU_PMEVTYPER_EL0(9), | |
1672 | PMU_PMEVTYPER_EL0(10), | |
1673 | PMU_PMEVTYPER_EL0(11), | |
1674 | PMU_PMEVTYPER_EL0(12), | |
1675 | PMU_PMEVTYPER_EL0(13), | |
1676 | PMU_PMEVTYPER_EL0(14), | |
1677 | PMU_PMEVTYPER_EL0(15), | |
1678 | PMU_PMEVTYPER_EL0(16), | |
1679 | PMU_PMEVTYPER_EL0(17), | |
1680 | PMU_PMEVTYPER_EL0(18), | |
1681 | PMU_PMEVTYPER_EL0(19), | |
1682 | PMU_PMEVTYPER_EL0(20), | |
1683 | PMU_PMEVTYPER_EL0(21), | |
1684 | PMU_PMEVTYPER_EL0(22), | |
1685 | PMU_PMEVTYPER_EL0(23), | |
1686 | PMU_PMEVTYPER_EL0(24), | |
1687 | PMU_PMEVTYPER_EL0(25), | |
1688 | PMU_PMEVTYPER_EL0(26), | |
1689 | PMU_PMEVTYPER_EL0(27), | |
1690 | PMU_PMEVTYPER_EL0(28), | |
1691 | PMU_PMEVTYPER_EL0(29), | |
1692 | PMU_PMEVTYPER_EL0(30), | |
174ed3e4 MR |
1693 | /* |
1694 | * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero | |
9feb21ac SZ |
1695 | * in 32bit mode. Here we choose to reset it as zero for consistency. |
1696 | */ | |
174ed3e4 | 1697 | { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 }, |
051ff581 | 1698 | |
851050a5 MR |
1699 | { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, |
1700 | { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, | |
c88b0936 | 1701 | { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, |
62a89c44 MZ |
1702 | }; |
1703 | ||
bdfb4b38 | 1704 | static bool trap_dbgidr(struct kvm_vcpu *vcpu, |
3fec037d | 1705 | struct sys_reg_params *p, |
bdfb4b38 MZ |
1706 | const struct sys_reg_desc *r) |
1707 | { | |
1708 | if (p->is_write) { | |
1709 | return ignore_write(vcpu, p); | |
1710 | } else { | |
46823dd1 DM |
1711 | u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); |
1712 | u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); | |
28c5dcb2 | 1713 | u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); |
bdfb4b38 | 1714 | |
2ec5be3d PF |
1715 | p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | |
1716 | (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | | |
1717 | (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) | |
1718 | | (6 << 16) | (el3 << 14) | (el3 << 12)); | |
bdfb4b38 MZ |
1719 | return true; |
1720 | } | |
1721 | } | |
1722 | ||
1da42c34 MZ |
1723 | /* |
1724 | * AArch32 debug register mappings | |
84e690bf AB |
1725 | * |
1726 | * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] | |
1727 | * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] | |
1728 | * | |
1da42c34 MZ |
1729 | * None of the other registers share their location, so treat them as |
1730 | * if they were 64bit. | |
84e690bf | 1731 | */ |
1da42c34 MZ |
1732 | #define DBG_BCR_BVR_WCR_WVR(n) \ |
1733 | /* DBGBVRn */ \ | |
1734 | { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ | |
1735 | /* DBGBCRn */ \ | |
1736 | { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ | |
1737 | /* DBGWVRn */ \ | |
1738 | { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ | |
1739 | /* DBGWCRn */ \ | |
84e690bf AB |
1740 | { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } |
1741 | ||
1da42c34 MZ |
1742 | #define DBGBXVR(n) \ |
1743 | { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } | |
bdfb4b38 MZ |
1744 | |
1745 | /* | |
1746 | * Trapped cp14 registers. We generally ignore most of the external | |
1747 | * debug, on the principle that they don't really make sense to a | |
84e690bf | 1748 | * guest. Revisit this one day, would this principle change. |
bdfb4b38 | 1749 | */ |
72564016 | 1750 | static const struct sys_reg_desc cp14_regs[] = { |
bdfb4b38 MZ |
1751 | /* DBGIDR */ |
1752 | { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, | |
1753 | /* DBGDTRRXext */ | |
1754 | { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, | |
1755 | ||
1756 | DBG_BCR_BVR_WCR_WVR(0), | |
1757 | /* DBGDSCRint */ | |
1758 | { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, | |
1759 | DBG_BCR_BVR_WCR_WVR(1), | |
1760 | /* DBGDCCINT */ | |
1da42c34 | 1761 | { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, |
bdfb4b38 | 1762 | /* DBGDSCRext */ |
1da42c34 | 1763 | { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, |
bdfb4b38 MZ |
1764 | DBG_BCR_BVR_WCR_WVR(2), |
1765 | /* DBGDTR[RT]Xint */ | |
1766 | { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, | |
1767 | /* DBGDTR[RT]Xext */ | |
1768 | { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, | |
1769 | DBG_BCR_BVR_WCR_WVR(3), | |
1770 | DBG_BCR_BVR_WCR_WVR(4), | |
1771 | DBG_BCR_BVR_WCR_WVR(5), | |
1772 | /* DBGWFAR */ | |
1773 | { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, | |
1774 | /* DBGOSECCR */ | |
1775 | { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, | |
1776 | DBG_BCR_BVR_WCR_WVR(6), | |
1777 | /* DBGVCR */ | |
1da42c34 | 1778 | { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, |
bdfb4b38 MZ |
1779 | DBG_BCR_BVR_WCR_WVR(7), |
1780 | DBG_BCR_BVR_WCR_WVR(8), | |
1781 | DBG_BCR_BVR_WCR_WVR(9), | |
1782 | DBG_BCR_BVR_WCR_WVR(10), | |
1783 | DBG_BCR_BVR_WCR_WVR(11), | |
1784 | DBG_BCR_BVR_WCR_WVR(12), | |
1785 | DBG_BCR_BVR_WCR_WVR(13), | |
1786 | DBG_BCR_BVR_WCR_WVR(14), | |
1787 | DBG_BCR_BVR_WCR_WVR(15), | |
1788 | ||
1789 | /* DBGDRAR (32bit) */ | |
1790 | { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, | |
1791 | ||
1792 | DBGBXVR(0), | |
1793 | /* DBGOSLAR */ | |
1794 | { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, | |
1795 | DBGBXVR(1), | |
1796 | /* DBGOSLSR */ | |
1797 | { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, | |
1798 | DBGBXVR(2), | |
1799 | DBGBXVR(3), | |
1800 | /* DBGOSDLR */ | |
1801 | { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, | |
1802 | DBGBXVR(4), | |
1803 | /* DBGPRCR */ | |
1804 | { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, | |
1805 | DBGBXVR(5), | |
1806 | DBGBXVR(6), | |
1807 | DBGBXVR(7), | |
1808 | DBGBXVR(8), | |
1809 | DBGBXVR(9), | |
1810 | DBGBXVR(10), | |
1811 | DBGBXVR(11), | |
1812 | DBGBXVR(12), | |
1813 | DBGBXVR(13), | |
1814 | DBGBXVR(14), | |
1815 | DBGBXVR(15), | |
1816 | ||
1817 | /* DBGDSAR (32bit) */ | |
1818 | { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, | |
1819 | ||
1820 | /* DBGDEVID2 */ | |
1821 | { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, | |
1822 | /* DBGDEVID1 */ | |
1823 | { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, | |
1824 | /* DBGDEVID */ | |
1825 | { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, | |
1826 | /* DBGCLAIMSET */ | |
1827 | { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, | |
1828 | /* DBGCLAIMCLR */ | |
1829 | { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, | |
1830 | /* DBGAUTHSTATUS */ | |
1831 | { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, | |
72564016 MZ |
1832 | }; |
1833 | ||
a9866ba0 MZ |
1834 | /* Trapped cp14 64bit registers */ |
1835 | static const struct sys_reg_desc cp14_64_regs[] = { | |
bdfb4b38 MZ |
1836 | /* DBGDRAR (64bit) */ |
1837 | { Op1( 0), CRm( 1), .access = trap_raz_wi }, | |
1838 | ||
1839 | /* DBGDSAR (64bit) */ | |
1840 | { Op1( 0), CRm( 2), .access = trap_raz_wi }, | |
a9866ba0 MZ |
1841 | }; |
1842 | ||
051ff581 SZ |
1843 | /* Macro to expand the PMEVCNTRn register */ |
1844 | #define PMU_PMEVCNTR(n) \ | |
1845 | /* PMEVCNTRn */ \ | |
1846 | { Op1(0), CRn(0b1110), \ | |
1847 | CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ | |
1848 | access_pmu_evcntr } | |
1849 | ||
9feb21ac SZ |
1850 | /* Macro to expand the PMEVTYPERn register */ |
1851 | #define PMU_PMEVTYPER(n) \ | |
1852 | /* PMEVTYPERn */ \ | |
1853 | { Op1(0), CRn(0b1110), \ | |
1854 | CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ | |
1855 | access_pmu_evtyper } | |
1856 | ||
4d44923b MZ |
1857 | /* |
1858 | * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, | |
1859 | * depending on the way they are accessed (as a 32bit or a 64bit | |
1860 | * register). | |
1861 | */ | |
62a89c44 | 1862 | static const struct sys_reg_desc cp15_regs[] = { |
f7f2b15c | 1863 | { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, |
b1ea1d76 MZ |
1864 | { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, |
1865 | /* ACTLR */ | |
1866 | { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, | |
1867 | /* ACTLR2 */ | |
1868 | { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, | |
1869 | { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, | |
1870 | { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, | |
1871 | /* TTBCR */ | |
1872 | { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, | |
1873 | /* TTBCR2 */ | |
1874 | { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, | |
1875 | { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, | |
1876 | /* DFSR */ | |
1877 | { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, | |
1878 | { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, | |
1879 | /* ADFSR */ | |
1880 | { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, | |
1881 | /* AIFSR */ | |
1882 | { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, | |
1883 | /* DFAR */ | |
1884 | { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, | |
1885 | /* IFAR */ | |
1886 | { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, | |
4d44923b | 1887 | |
62a89c44 MZ |
1888 | /* |
1889 | * DC{C,I,CI}SW operations: | |
1890 | */ | |
1891 | { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, | |
1892 | { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, | |
1893 | { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, | |
4d44923b | 1894 | |
7609c125 | 1895 | /* PMU */ |
ab946834 | 1896 | { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, |
96b0eebc SZ |
1897 | { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, |
1898 | { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, | |
76d883c4 | 1899 | { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, |
7a0adc70 | 1900 | { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, |
3965c3ce | 1901 | { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, |
a86b5505 SZ |
1902 | { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, |
1903 | { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, | |
051ff581 | 1904 | { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, |
9feb21ac | 1905 | { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, |
051ff581 | 1906 | { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, |
d692b8ad | 1907 | { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, |
9db52c78 SZ |
1908 | { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, |
1909 | { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, | |
76d883c4 | 1910 | { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, |
4d44923b | 1911 | |
b1ea1d76 MZ |
1912 | /* PRRR/MAIR0 */ |
1913 | { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, | |
1914 | /* NMRR/MAIR1 */ | |
1915 | { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, | |
1916 | /* AMAIR0 */ | |
1917 | { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, | |
1918 | /* AMAIR1 */ | |
1919 | { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, | |
db7dedd0 CD |
1920 | |
1921 | /* ICC_SRE */ | |
f7f6f2d9 | 1922 | { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, |
db7dedd0 | 1923 | |
b1ea1d76 | 1924 | { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, |
051ff581 | 1925 | |
84135d3d AP |
1926 | /* Arch Tmers */ |
1927 | { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, | |
1928 | { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, | |
eac137b4 | 1929 | |
051ff581 SZ |
1930 | /* PMEVCNTRn */ |
1931 | PMU_PMEVCNTR(0), | |
1932 | PMU_PMEVCNTR(1), | |
1933 | PMU_PMEVCNTR(2), | |
1934 | PMU_PMEVCNTR(3), | |
1935 | PMU_PMEVCNTR(4), | |
1936 | PMU_PMEVCNTR(5), | |
1937 | PMU_PMEVCNTR(6), | |
1938 | PMU_PMEVCNTR(7), | |
1939 | PMU_PMEVCNTR(8), | |
1940 | PMU_PMEVCNTR(9), | |
1941 | PMU_PMEVCNTR(10), | |
1942 | PMU_PMEVCNTR(11), | |
1943 | PMU_PMEVCNTR(12), | |
1944 | PMU_PMEVCNTR(13), | |
1945 | PMU_PMEVCNTR(14), | |
1946 | PMU_PMEVCNTR(15), | |
1947 | PMU_PMEVCNTR(16), | |
1948 | PMU_PMEVCNTR(17), | |
1949 | PMU_PMEVCNTR(18), | |
1950 | PMU_PMEVCNTR(19), | |
1951 | PMU_PMEVCNTR(20), | |
1952 | PMU_PMEVCNTR(21), | |
1953 | PMU_PMEVCNTR(22), | |
1954 | PMU_PMEVCNTR(23), | |
1955 | PMU_PMEVCNTR(24), | |
1956 | PMU_PMEVCNTR(25), | |
1957 | PMU_PMEVCNTR(26), | |
1958 | PMU_PMEVCNTR(27), | |
1959 | PMU_PMEVCNTR(28), | |
1960 | PMU_PMEVCNTR(29), | |
1961 | PMU_PMEVCNTR(30), | |
9feb21ac SZ |
1962 | /* PMEVTYPERn */ |
1963 | PMU_PMEVTYPER(0), | |
1964 | PMU_PMEVTYPER(1), | |
1965 | PMU_PMEVTYPER(2), | |
1966 | PMU_PMEVTYPER(3), | |
1967 | PMU_PMEVTYPER(4), | |
1968 | PMU_PMEVTYPER(5), | |
1969 | PMU_PMEVTYPER(6), | |
1970 | PMU_PMEVTYPER(7), | |
1971 | PMU_PMEVTYPER(8), | |
1972 | PMU_PMEVTYPER(9), | |
1973 | PMU_PMEVTYPER(10), | |
1974 | PMU_PMEVTYPER(11), | |
1975 | PMU_PMEVTYPER(12), | |
1976 | PMU_PMEVTYPER(13), | |
1977 | PMU_PMEVTYPER(14), | |
1978 | PMU_PMEVTYPER(15), | |
1979 | PMU_PMEVTYPER(16), | |
1980 | PMU_PMEVTYPER(17), | |
1981 | PMU_PMEVTYPER(18), | |
1982 | PMU_PMEVTYPER(19), | |
1983 | PMU_PMEVTYPER(20), | |
1984 | PMU_PMEVTYPER(21), | |
1985 | PMU_PMEVTYPER(22), | |
1986 | PMU_PMEVTYPER(23), | |
1987 | PMU_PMEVTYPER(24), | |
1988 | PMU_PMEVTYPER(25), | |
1989 | PMU_PMEVTYPER(26), | |
1990 | PMU_PMEVTYPER(27), | |
1991 | PMU_PMEVTYPER(28), | |
1992 | PMU_PMEVTYPER(29), | |
1993 | PMU_PMEVTYPER(30), | |
1994 | /* PMCCFILTR */ | |
1995 | { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, | |
f7f2b15c AB |
1996 | |
1997 | { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, | |
1998 | { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, | |
b1ea1d76 | 1999 | { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, |
a9866ba0 MZ |
2000 | }; |
2001 | ||
2002 | static const struct sys_reg_desc cp15_64_regs[] = { | |
b1ea1d76 | 2003 | { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, |
051ff581 | 2004 | { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, |
03bd646d | 2005 | { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ |
b1ea1d76 | 2006 | { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, |
03bd646d MZ |
2007 | { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ |
2008 | { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ | |
84135d3d | 2009 | { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, |
7c8c5e6a MZ |
2010 | }; |
2011 | ||
bb44a8db MZ |
2012 | static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, |
2013 | bool is_32) | |
2014 | { | |
2015 | unsigned int i; | |
2016 | ||
2017 | for (i = 0; i < n; i++) { | |
2018 | if (!is_32 && table[i].reg && !table[i].reset) { | |
2019 | kvm_err("sys_reg table %p entry %d has lacks reset\n", | |
2020 | table, i); | |
2021 | return 1; | |
2022 | } | |
2023 | ||
2024 | if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { | |
2025 | kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); | |
2026 | return 1; | |
2027 | } | |
2028 | } | |
2029 | ||
2030 | return 0; | |
2031 | } | |
2032 | ||
623eefa8 MZ |
2033 | static int match_sys_reg(const void *key, const void *elt) |
2034 | { | |
2035 | const unsigned long pval = (unsigned long)key; | |
2036 | const struct sys_reg_desc *r = elt; | |
2037 | ||
09838de9 | 2038 | return pval - reg_to_encoding(r); |
623eefa8 MZ |
2039 | } |
2040 | ||
7c8c5e6a MZ |
2041 | static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, |
2042 | const struct sys_reg_desc table[], | |
2043 | unsigned int num) | |
2044 | { | |
09838de9 | 2045 | unsigned long pval = reg_to_encoding(params); |
623eefa8 MZ |
2046 | |
2047 | return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg); | |
7c8c5e6a MZ |
2048 | } |
2049 | ||
74cc7e0c | 2050 | int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) |
62a89c44 MZ |
2051 | { |
2052 | kvm_inject_undefined(vcpu); | |
2053 | return 1; | |
2054 | } | |
2055 | ||
e70b9522 MZ |
2056 | static void perform_access(struct kvm_vcpu *vcpu, |
2057 | struct sys_reg_params *params, | |
2058 | const struct sys_reg_desc *r) | |
2059 | { | |
599d79dc MZ |
2060 | trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); |
2061 | ||
7f34e409 | 2062 | /* Check for regs disabled by runtime config */ |
01fe5ace | 2063 | if (sysreg_hidden(vcpu, r)) { |
7f34e409 DM |
2064 | kvm_inject_undefined(vcpu); |
2065 | return; | |
2066 | } | |
2067 | ||
e70b9522 MZ |
2068 | /* |
2069 | * Not having an accessor means that we have configured a trap | |
2070 | * that we don't know how to handle. This certainly qualifies | |
2071 | * as a gross bug that should be fixed right away. | |
2072 | */ | |
2073 | BUG_ON(!r->access); | |
2074 | ||
2075 | /* Skip instruction if instructed so */ | |
2076 | if (likely(r->access(vcpu, params, r))) | |
cdb5e02e | 2077 | kvm_incr_pc(vcpu); |
e70b9522 MZ |
2078 | } |
2079 | ||
72564016 MZ |
2080 | /* |
2081 | * emulate_cp -- tries to match a sys_reg access in a handling table, and | |
2082 | * call the corresponding trap handler. | |
2083 | * | |
2084 | * @params: pointer to the descriptor of the access | |
2085 | * @table: array of trap descriptors | |
2086 | * @num: size of the trap descriptor array | |
2087 | * | |
2088 | * Return 0 if the access has been handled, and -1 if not. | |
2089 | */ | |
2090 | static int emulate_cp(struct kvm_vcpu *vcpu, | |
3fec037d | 2091 | struct sys_reg_params *params, |
72564016 MZ |
2092 | const struct sys_reg_desc *table, |
2093 | size_t num) | |
62a89c44 | 2094 | { |
72564016 | 2095 | const struct sys_reg_desc *r; |
62a89c44 | 2096 | |
72564016 MZ |
2097 | if (!table) |
2098 | return -1; /* Not handled */ | |
62a89c44 | 2099 | |
62a89c44 | 2100 | r = find_reg(params, table, num); |
62a89c44 | 2101 | |
72564016 | 2102 | if (r) { |
e70b9522 MZ |
2103 | perform_access(vcpu, params, r); |
2104 | return 0; | |
72564016 MZ |
2105 | } |
2106 | ||
2107 | /* Not handled */ | |
2108 | return -1; | |
2109 | } | |
2110 | ||
2111 | static void unhandled_cp_access(struct kvm_vcpu *vcpu, | |
2112 | struct sys_reg_params *params) | |
2113 | { | |
3a949f4c | 2114 | u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); |
40c4f8d2 | 2115 | int cp = -1; |
72564016 | 2116 | |
3a949f4c | 2117 | switch (esr_ec) { |
c6d01a94 MR |
2118 | case ESR_ELx_EC_CP15_32: |
2119 | case ESR_ELx_EC_CP15_64: | |
72564016 MZ |
2120 | cp = 15; |
2121 | break; | |
c6d01a94 MR |
2122 | case ESR_ELx_EC_CP14_MR: |
2123 | case ESR_ELx_EC_CP14_64: | |
72564016 MZ |
2124 | cp = 14; |
2125 | break; | |
2126 | default: | |
40c4f8d2 | 2127 | WARN_ON(1); |
62a89c44 MZ |
2128 | } |
2129 | ||
bf4b96bb MR |
2130 | print_sys_reg_msg(params, |
2131 | "Unsupported guest CP%d access at: %08lx [%08lx]\n", | |
2132 | cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); | |
62a89c44 MZ |
2133 | kvm_inject_undefined(vcpu); |
2134 | } | |
2135 | ||
2136 | /** | |
7769db90 | 2137 | * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access |
62a89c44 MZ |
2138 | * @vcpu: The VCPU pointer |
2139 | * @run: The kvm_run struct | |
2140 | */ | |
72564016 MZ |
2141 | static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, |
2142 | const struct sys_reg_desc *global, | |
dcaffa7b | 2143 | size_t nr_global) |
62a89c44 MZ |
2144 | { |
2145 | struct sys_reg_params params; | |
3a949f4c | 2146 | u32 esr = kvm_vcpu_get_esr(vcpu); |
c667186f | 2147 | int Rt = kvm_vcpu_sys_get_rt(vcpu); |
3a949f4c | 2148 | int Rt2 = (esr >> 10) & 0x1f; |
62a89c44 | 2149 | |
3a949f4c GS |
2150 | params.CRm = (esr >> 1) & 0xf; |
2151 | params.is_write = ((esr & 1) == 0); | |
62a89c44 MZ |
2152 | |
2153 | params.Op0 = 0; | |
3a949f4c | 2154 | params.Op1 = (esr >> 16) & 0xf; |
62a89c44 MZ |
2155 | params.Op2 = 0; |
2156 | params.CRn = 0; | |
2157 | ||
2158 | /* | |
2ec5be3d | 2159 | * Make a 64-bit value out of Rt and Rt2. As we use the same trap |
62a89c44 MZ |
2160 | * backends between AArch32 and AArch64, we get away with it. |
2161 | */ | |
2162 | if (params.is_write) { | |
2ec5be3d PF |
2163 | params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; |
2164 | params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; | |
62a89c44 MZ |
2165 | } |
2166 | ||
b6b7a806 | 2167 | /* |
dcaffa7b | 2168 | * If the table contains a handler, handle the |
b6b7a806 MZ |
2169 | * potential register operation in the case of a read and return |
2170 | * with success. | |
2171 | */ | |
dcaffa7b | 2172 | if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { |
b6b7a806 MZ |
2173 | /* Split up the value between registers for the read side */ |
2174 | if (!params.is_write) { | |
2175 | vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); | |
2176 | vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); | |
2177 | } | |
62a89c44 | 2178 | |
b6b7a806 | 2179 | return 1; |
62a89c44 MZ |
2180 | } |
2181 | ||
b6b7a806 | 2182 | unhandled_cp_access(vcpu, ¶ms); |
62a89c44 MZ |
2183 | return 1; |
2184 | } | |
2185 | ||
2186 | /** | |
7769db90 | 2187 | * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access |
62a89c44 MZ |
2188 | * @vcpu: The VCPU pointer |
2189 | * @run: The kvm_run struct | |
2190 | */ | |
72564016 MZ |
2191 | static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, |
2192 | const struct sys_reg_desc *global, | |
dcaffa7b | 2193 | size_t nr_global) |
62a89c44 MZ |
2194 | { |
2195 | struct sys_reg_params params; | |
3a949f4c | 2196 | u32 esr = kvm_vcpu_get_esr(vcpu); |
c667186f | 2197 | int Rt = kvm_vcpu_sys_get_rt(vcpu); |
62a89c44 | 2198 | |
3a949f4c | 2199 | params.CRm = (esr >> 1) & 0xf; |
2ec5be3d | 2200 | params.regval = vcpu_get_reg(vcpu, Rt); |
3a949f4c GS |
2201 | params.is_write = ((esr & 1) == 0); |
2202 | params.CRn = (esr >> 10) & 0xf; | |
62a89c44 | 2203 | params.Op0 = 0; |
3a949f4c GS |
2204 | params.Op1 = (esr >> 14) & 0x7; |
2205 | params.Op2 = (esr >> 17) & 0x7; | |
62a89c44 | 2206 | |
dcaffa7b | 2207 | if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { |
2ec5be3d PF |
2208 | if (!params.is_write) |
2209 | vcpu_set_reg(vcpu, Rt, params.regval); | |
72564016 | 2210 | return 1; |
2ec5be3d | 2211 | } |
72564016 MZ |
2212 | |
2213 | unhandled_cp_access(vcpu, ¶ms); | |
62a89c44 MZ |
2214 | return 1; |
2215 | } | |
2216 | ||
74cc7e0c | 2217 | int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) |
72564016 | 2218 | { |
dcaffa7b | 2219 | return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); |
72564016 MZ |
2220 | } |
2221 | ||
74cc7e0c | 2222 | int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) |
72564016 | 2223 | { |
dcaffa7b | 2224 | return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); |
72564016 MZ |
2225 | } |
2226 | ||
74cc7e0c | 2227 | int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) |
72564016 | 2228 | { |
dcaffa7b | 2229 | return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); |
72564016 MZ |
2230 | } |
2231 | ||
74cc7e0c | 2232 | int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) |
72564016 | 2233 | { |
dcaffa7b | 2234 | return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); |
72564016 MZ |
2235 | } |
2236 | ||
54ad68b7 MR |
2237 | static bool is_imp_def_sys_reg(struct sys_reg_params *params) |
2238 | { | |
2239 | // See ARM DDI 0487E.a, section D12.3.2 | |
2240 | return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; | |
2241 | } | |
2242 | ||
7c8c5e6a | 2243 | static int emulate_sys_reg(struct kvm_vcpu *vcpu, |
3fec037d | 2244 | struct sys_reg_params *params) |
7c8c5e6a | 2245 | { |
dcaffa7b | 2246 | const struct sys_reg_desc *r; |
7c8c5e6a | 2247 | |
dcaffa7b | 2248 | r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); |
7c8c5e6a MZ |
2249 | |
2250 | if (likely(r)) { | |
e70b9522 | 2251 | perform_access(vcpu, params, r); |
54ad68b7 MR |
2252 | } else if (is_imp_def_sys_reg(params)) { |
2253 | kvm_inject_undefined(vcpu); | |
7c8c5e6a | 2254 | } else { |
bf4b96bb MR |
2255 | print_sys_reg_msg(params, |
2256 | "Unsupported guest sys_reg access at: %lx [%08lx]\n", | |
2257 | *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); | |
e70b9522 | 2258 | kvm_inject_undefined(vcpu); |
7c8c5e6a | 2259 | } |
7c8c5e6a MZ |
2260 | return 1; |
2261 | } | |
2262 | ||
750ed566 JM |
2263 | /** |
2264 | * kvm_reset_sys_regs - sets system registers to reset value | |
2265 | * @vcpu: The VCPU pointer | |
2266 | * | |
2267 | * This function finds the right table above and sets the registers on the | |
2268 | * virtual CPU struct to their architecturally defined reset values. | |
2269 | */ | |
2270 | void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) | |
7c8c5e6a MZ |
2271 | { |
2272 | unsigned long i; | |
2273 | ||
750ed566 JM |
2274 | for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) |
2275 | if (sys_reg_descs[i].reset) | |
2276 | sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); | |
7c8c5e6a MZ |
2277 | } |
2278 | ||
2279 | /** | |
2280 | * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access | |
2281 | * @vcpu: The VCPU pointer | |
7c8c5e6a | 2282 | */ |
74cc7e0c | 2283 | int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) |
7c8c5e6a MZ |
2284 | { |
2285 | struct sys_reg_params params; | |
3a949f4c | 2286 | unsigned long esr = kvm_vcpu_get_esr(vcpu); |
c667186f | 2287 | int Rt = kvm_vcpu_sys_get_rt(vcpu); |
2ec5be3d | 2288 | int ret; |
7c8c5e6a | 2289 | |
eef8c85a AB |
2290 | trace_kvm_handle_sys_reg(esr); |
2291 | ||
7c8c5e6a MZ |
2292 | params.Op0 = (esr >> 20) & 3; |
2293 | params.Op1 = (esr >> 14) & 0x7; | |
2294 | params.CRn = (esr >> 10) & 0xf; | |
2295 | params.CRm = (esr >> 1) & 0xf; | |
2296 | params.Op2 = (esr >> 17) & 0x7; | |
2ec5be3d | 2297 | params.regval = vcpu_get_reg(vcpu, Rt); |
7c8c5e6a MZ |
2298 | params.is_write = !(esr & 1); |
2299 | ||
2ec5be3d PF |
2300 | ret = emulate_sys_reg(vcpu, ¶ms); |
2301 | ||
2302 | if (!params.is_write) | |
2303 | vcpu_set_reg(vcpu, Rt, params.regval); | |
2304 | return ret; | |
7c8c5e6a MZ |
2305 | } |
2306 | ||
2307 | /****************************************************************************** | |
2308 | * Userspace API | |
2309 | *****************************************************************************/ | |
2310 | ||
2311 | static bool index_to_params(u64 id, struct sys_reg_params *params) | |
2312 | { | |
2313 | switch (id & KVM_REG_SIZE_MASK) { | |
2314 | case KVM_REG_SIZE_U64: | |
2315 | /* Any unused index bits means it's not valid. */ | |
2316 | if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | |
2317 | | KVM_REG_ARM_COPROC_MASK | |
2318 | | KVM_REG_ARM64_SYSREG_OP0_MASK | |
2319 | | KVM_REG_ARM64_SYSREG_OP1_MASK | |
2320 | | KVM_REG_ARM64_SYSREG_CRN_MASK | |
2321 | | KVM_REG_ARM64_SYSREG_CRM_MASK | |
2322 | | KVM_REG_ARM64_SYSREG_OP2_MASK)) | |
2323 | return false; | |
2324 | params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) | |
2325 | >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); | |
2326 | params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) | |
2327 | >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); | |
2328 | params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) | |
2329 | >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); | |
2330 | params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) | |
2331 | >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); | |
2332 | params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) | |
2333 | >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); | |
2334 | return true; | |
2335 | default: | |
2336 | return false; | |
2337 | } | |
2338 | } | |
2339 | ||
4b927b94 VK |
2340 | const struct sys_reg_desc *find_reg_by_id(u64 id, |
2341 | struct sys_reg_params *params, | |
2342 | const struct sys_reg_desc table[], | |
2343 | unsigned int num) | |
2344 | { | |
2345 | if (!index_to_params(id, params)) | |
2346 | return NULL; | |
2347 | ||
2348 | return find_reg(params, table, num); | |
2349 | } | |
2350 | ||
7c8c5e6a MZ |
2351 | /* Decode an index value, and find the sys_reg_desc entry. */ |
2352 | static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, | |
2353 | u64 id) | |
2354 | { | |
dcaffa7b | 2355 | const struct sys_reg_desc *r; |
7c8c5e6a MZ |
2356 | struct sys_reg_params params; |
2357 | ||
2358 | /* We only do sys_reg for now. */ | |
2359 | if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) | |
2360 | return NULL; | |
2361 | ||
1ce74e96 WD |
2362 | if (!index_to_params(id, ¶ms)) |
2363 | return NULL; | |
2364 | ||
dcaffa7b | 2365 | r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); |
7c8c5e6a | 2366 | |
93390c0a DM |
2367 | /* Not saved in the sys_reg array and not otherwise accessible? */ |
2368 | if (r && !(r->reg || r->get_user)) | |
7c8c5e6a MZ |
2369 | r = NULL; |
2370 | ||
2371 | return r; | |
2372 | } | |
2373 | ||
2374 | /* | |
2375 | * These are the invariant sys_reg registers: we let the guest see the | |
2376 | * host versions of these, so they're part of the guest state. | |
2377 | * | |
2378 | * A future CPU may provide a mechanism to present different values to | |
2379 | * the guest, or a future kvm may trap them. | |
2380 | */ | |
2381 | ||
2382 | #define FUNCTION_INVARIANT(reg) \ | |
2383 | static void get_##reg(struct kvm_vcpu *v, \ | |
2384 | const struct sys_reg_desc *r) \ | |
2385 | { \ | |
1f3d8699 | 2386 | ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ |
7c8c5e6a MZ |
2387 | } |
2388 | ||
2389 | FUNCTION_INVARIANT(midr_el1) | |
7c8c5e6a | 2390 | FUNCTION_INVARIANT(revidr_el1) |
7c8c5e6a MZ |
2391 | FUNCTION_INVARIANT(clidr_el1) |
2392 | FUNCTION_INVARIANT(aidr_el1) | |
2393 | ||
f7f2b15c AB |
2394 | static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) |
2395 | { | |
2396 | ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); | |
2397 | } | |
2398 | ||
7c8c5e6a MZ |
2399 | /* ->val is filled in by kvm_sys_reg_table_init() */ |
2400 | static struct sys_reg_desc invariant_sys_regs[] = { | |
0d449541 MR |
2401 | { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, |
2402 | { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, | |
0d449541 MR |
2403 | { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, |
2404 | { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, | |
2405 | { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, | |
7c8c5e6a MZ |
2406 | }; |
2407 | ||
26c99af1 | 2408 | static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) |
7c8c5e6a | 2409 | { |
7c8c5e6a MZ |
2410 | if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) |
2411 | return -EFAULT; | |
2412 | return 0; | |
2413 | } | |
2414 | ||
26c99af1 | 2415 | static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) |
7c8c5e6a | 2416 | { |
7c8c5e6a MZ |
2417 | if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) |
2418 | return -EFAULT; | |
2419 | return 0; | |
2420 | } | |
2421 | ||
2422 | static int get_invariant_sys_reg(u64 id, void __user *uaddr) | |
2423 | { | |
2424 | struct sys_reg_params params; | |
2425 | const struct sys_reg_desc *r; | |
2426 | ||
4b927b94 VK |
2427 | r = find_reg_by_id(id, ¶ms, invariant_sys_regs, |
2428 | ARRAY_SIZE(invariant_sys_regs)); | |
7c8c5e6a MZ |
2429 | if (!r) |
2430 | return -ENOENT; | |
2431 | ||
2432 | return reg_to_user(uaddr, &r->val, id); | |
2433 | } | |
2434 | ||
2435 | static int set_invariant_sys_reg(u64 id, void __user *uaddr) | |
2436 | { | |
2437 | struct sys_reg_params params; | |
2438 | const struct sys_reg_desc *r; | |
2439 | int err; | |
2440 | u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ | |
2441 | ||
4b927b94 VK |
2442 | r = find_reg_by_id(id, ¶ms, invariant_sys_regs, |
2443 | ARRAY_SIZE(invariant_sys_regs)); | |
7c8c5e6a MZ |
2444 | if (!r) |
2445 | return -ENOENT; | |
2446 | ||
2447 | err = reg_from_user(&val, uaddr, id); | |
2448 | if (err) | |
2449 | return err; | |
2450 | ||
2451 | /* This is what we mean by invariant: you can't change it. */ | |
2452 | if (r->val != val) | |
2453 | return -EINVAL; | |
2454 | ||
2455 | return 0; | |
2456 | } | |
2457 | ||
2458 | static bool is_valid_cache(u32 val) | |
2459 | { | |
2460 | u32 level, ctype; | |
2461 | ||
2462 | if (val >= CSSELR_MAX) | |
18d45766 | 2463 | return false; |
7c8c5e6a MZ |
2464 | |
2465 | /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ | |
2466 | level = (val >> 1); | |
2467 | ctype = (cache_levels >> (level * 3)) & 7; | |
2468 | ||
2469 | switch (ctype) { | |
2470 | case 0: /* No cache */ | |
2471 | return false; | |
2472 | case 1: /* Instruction cache only */ | |
2473 | return (val & 1); | |
2474 | case 2: /* Data cache only */ | |
2475 | case 4: /* Unified cache */ | |
2476 | return !(val & 1); | |
2477 | case 3: /* Separate instruction and data caches */ | |
2478 | return true; | |
2479 | default: /* Reserved: we can't know instruction or data. */ | |
2480 | return false; | |
2481 | } | |
2482 | } | |
2483 | ||
2484 | static int demux_c15_get(u64 id, void __user *uaddr) | |
2485 | { | |
2486 | u32 val; | |
2487 | u32 __user *uval = uaddr; | |
2488 | ||
2489 | /* Fail if we have unknown bits set. */ | |
2490 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
2491 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
2492 | return -ENOENT; | |
2493 | ||
2494 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
2495 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
2496 | if (KVM_REG_SIZE(id) != 4) | |
2497 | return -ENOENT; | |
2498 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
2499 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
2500 | if (!is_valid_cache(val)) | |
2501 | return -ENOENT; | |
2502 | ||
2503 | return put_user(get_ccsidr(val), uval); | |
2504 | default: | |
2505 | return -ENOENT; | |
2506 | } | |
2507 | } | |
2508 | ||
2509 | static int demux_c15_set(u64 id, void __user *uaddr) | |
2510 | { | |
2511 | u32 val, newval; | |
2512 | u32 __user *uval = uaddr; | |
2513 | ||
2514 | /* Fail if we have unknown bits set. */ | |
2515 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
2516 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
2517 | return -ENOENT; | |
2518 | ||
2519 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
2520 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
2521 | if (KVM_REG_SIZE(id) != 4) | |
2522 | return -ENOENT; | |
2523 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
2524 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
2525 | if (!is_valid_cache(val)) | |
2526 | return -ENOENT; | |
2527 | ||
2528 | if (get_user(newval, uval)) | |
2529 | return -EFAULT; | |
2530 | ||
2531 | /* This is also invariant: you can't change it. */ | |
2532 | if (newval != get_ccsidr(val)) | |
2533 | return -EINVAL; | |
2534 | return 0; | |
2535 | default: | |
2536 | return -ENOENT; | |
2537 | } | |
2538 | } | |
2539 | ||
2540 | int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) | |
2541 | { | |
2542 | const struct sys_reg_desc *r; | |
2543 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; | |
2544 | ||
2545 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) | |
2546 | return demux_c15_get(reg->id, uaddr); | |
2547 | ||
2548 | if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) | |
2549 | return -ENOENT; | |
2550 | ||
2551 | r = index_to_sys_reg_desc(vcpu, reg->id); | |
2552 | if (!r) | |
2553 | return get_invariant_sys_reg(reg->id, uaddr); | |
2554 | ||
7f34e409 | 2555 | /* Check for regs disabled by runtime config */ |
01fe5ace | 2556 | if (sysreg_hidden(vcpu, r)) |
7f34e409 DM |
2557 | return -ENOENT; |
2558 | ||
84e690bf AB |
2559 | if (r->get_user) |
2560 | return (r->get_user)(vcpu, r, reg, uaddr); | |
2561 | ||
8d404c4c | 2562 | return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); |
7c8c5e6a MZ |
2563 | } |
2564 | ||
2565 | int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) | |
2566 | { | |
2567 | const struct sys_reg_desc *r; | |
2568 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; | |
2569 | ||
2570 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) | |
2571 | return demux_c15_set(reg->id, uaddr); | |
2572 | ||
2573 | if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) | |
2574 | return -ENOENT; | |
2575 | ||
2576 | r = index_to_sys_reg_desc(vcpu, reg->id); | |
2577 | if (!r) | |
2578 | return set_invariant_sys_reg(reg->id, uaddr); | |
2579 | ||
7f34e409 | 2580 | /* Check for regs disabled by runtime config */ |
01fe5ace | 2581 | if (sysreg_hidden(vcpu, r)) |
7f34e409 DM |
2582 | return -ENOENT; |
2583 | ||
84e690bf AB |
2584 | if (r->set_user) |
2585 | return (r->set_user)(vcpu, r, reg, uaddr); | |
2586 | ||
8d404c4c | 2587 | return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); |
7c8c5e6a MZ |
2588 | } |
2589 | ||
2590 | static unsigned int num_demux_regs(void) | |
2591 | { | |
2592 | unsigned int i, count = 0; | |
2593 | ||
2594 | for (i = 0; i < CSSELR_MAX; i++) | |
2595 | if (is_valid_cache(i)) | |
2596 | count++; | |
2597 | ||
2598 | return count; | |
2599 | } | |
2600 | ||
2601 | static int write_demux_regids(u64 __user *uindices) | |
2602 | { | |
efd48cea | 2603 | u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; |
7c8c5e6a MZ |
2604 | unsigned int i; |
2605 | ||
2606 | val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; | |
2607 | for (i = 0; i < CSSELR_MAX; i++) { | |
2608 | if (!is_valid_cache(i)) | |
2609 | continue; | |
2610 | if (put_user(val | i, uindices)) | |
2611 | return -EFAULT; | |
2612 | uindices++; | |
2613 | } | |
2614 | return 0; | |
2615 | } | |
2616 | ||
2617 | static u64 sys_reg_to_index(const struct sys_reg_desc *reg) | |
2618 | { | |
2619 | return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | | |
2620 | KVM_REG_ARM64_SYSREG | | |
2621 | (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | | |
2622 | (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | | |
2623 | (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | | |
2624 | (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | | |
2625 | (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); | |
2626 | } | |
2627 | ||
2628 | static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) | |
2629 | { | |
2630 | if (!*uind) | |
2631 | return true; | |
2632 | ||
2633 | if (put_user(sys_reg_to_index(reg), *uind)) | |
2634 | return false; | |
2635 | ||
2636 | (*uind)++; | |
2637 | return true; | |
2638 | } | |
2639 | ||
7f34e409 DM |
2640 | static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, |
2641 | const struct sys_reg_desc *rd, | |
93390c0a DM |
2642 | u64 __user **uind, |
2643 | unsigned int *total) | |
2644 | { | |
2645 | /* | |
2646 | * Ignore registers we trap but don't save, | |
2647 | * and for which no custom user accessor is provided. | |
2648 | */ | |
2649 | if (!(rd->reg || rd->get_user)) | |
2650 | return 0; | |
2651 | ||
01fe5ace | 2652 | if (sysreg_hidden(vcpu, rd)) |
7f34e409 DM |
2653 | return 0; |
2654 | ||
93390c0a DM |
2655 | if (!copy_reg_to_user(rd, uind)) |
2656 | return -EFAULT; | |
2657 | ||
2658 | (*total)++; | |
2659 | return 0; | |
2660 | } | |
2661 | ||
7c8c5e6a MZ |
2662 | /* Assumed ordered tables, see kvm_sys_reg_table_init. */ |
2663 | static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) | |
2664 | { | |
dcaffa7b | 2665 | const struct sys_reg_desc *i2, *end2; |
7c8c5e6a | 2666 | unsigned int total = 0; |
93390c0a | 2667 | int err; |
7c8c5e6a | 2668 | |
7c8c5e6a MZ |
2669 | i2 = sys_reg_descs; |
2670 | end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); | |
2671 | ||
dcaffa7b JM |
2672 | while (i2 != end2) { |
2673 | err = walk_one_sys_reg(vcpu, i2++, &uind, &total); | |
93390c0a DM |
2674 | if (err) |
2675 | return err; | |
7c8c5e6a MZ |
2676 | } |
2677 | return total; | |
2678 | } | |
2679 | ||
2680 | unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) | |
2681 | { | |
2682 | return ARRAY_SIZE(invariant_sys_regs) | |
2683 | + num_demux_regs() | |
2684 | + walk_sys_regs(vcpu, (u64 __user *)NULL); | |
2685 | } | |
2686 | ||
2687 | int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) | |
2688 | { | |
2689 | unsigned int i; | |
2690 | int err; | |
2691 | ||
2692 | /* Then give them all the invariant registers' indices. */ | |
2693 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { | |
2694 | if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) | |
2695 | return -EFAULT; | |
2696 | uindices++; | |
2697 | } | |
2698 | ||
2699 | err = walk_sys_regs(vcpu, uindices); | |
2700 | if (err < 0) | |
2701 | return err; | |
2702 | uindices += err; | |
2703 | ||
2704 | return write_demux_regids(uindices); | |
2705 | } | |
2706 | ||
2707 | void kvm_sys_reg_table_init(void) | |
2708 | { | |
2709 | unsigned int i; | |
2710 | struct sys_reg_desc clidr; | |
2711 | ||
2712 | /* Make sure tables are unique and in order. */ | |
bb44a8db MZ |
2713 | BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false)); |
2714 | BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true)); | |
2715 | BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true)); | |
2716 | BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true)); | |
2717 | BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true)); | |
2718 | BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false)); | |
7c8c5e6a MZ |
2719 | |
2720 | /* We abuse the reset function to overwrite the table itself. */ | |
2721 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) | |
2722 | invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); | |
2723 | ||
2724 | /* | |
2725 | * CLIDR format is awkward, so clean it up. See ARM B4.1.20: | |
2726 | * | |
2727 | * If software reads the Cache Type fields from Ctype1 | |
2728 | * upwards, once it has seen a value of 0b000, no caches | |
2729 | * exist at further-out levels of the hierarchy. So, for | |
2730 | * example, if Ctype3 is the first Cache Type field with a | |
2731 | * value of 0b000, the values of Ctype4 to Ctype7 must be | |
2732 | * ignored. | |
2733 | */ | |
2734 | get_clidr_el1(NULL, &clidr); /* Ugly... */ | |
2735 | cache_levels = clidr.val; | |
2736 | for (i = 0; i < 7; i++) | |
2737 | if (((cache_levels >> (i*3)) & 7) == 0) | |
2738 | break; | |
2739 | /* Clear all higher bits. */ | |
2740 | cache_levels &= (1 << (i*3))-1; | |
2741 | } |