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9cce7a43 CM |
1 | /* |
2 | * Based on arch/arm/mm/proc.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | #include <asm/assembler.h> | |
24 | #include <asm/asm-offsets.h> | |
25 | #include <asm/hwcap.h> | |
9cce7a43 | 26 | #include <asm/pgtable.h> |
cabe1c81 | 27 | #include <asm/pgtable-hwdef.h> |
104a0c02 AP |
28 | #include <asm/cpufeature.h> |
29 | #include <asm/alternative.h> | |
9cce7a43 | 30 | |
35a86976 CM |
31 | #ifdef CONFIG_ARM64_64K_PAGES |
32 | #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K | |
44eaacf1 SP |
33 | #elif defined(CONFIG_ARM64_16K_PAGES) |
34 | #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K | |
35 | #else /* CONFIG_ARM64_4K_PAGES */ | |
35a86976 CM |
36 | #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K |
37 | #endif | |
38 | ||
35a86976 | 39 | #define TCR_SMP_FLAGS TCR_SHARED |
9cce7a43 | 40 | |
35a86976 CM |
41 | /* PTWs cacheable, inner/outer WBWA */ |
42 | #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | |
43 | ||
9cce7a43 CM |
44 | #define MAIR(attr, mt) ((attr) << ((mt) * 8)) |
45 | ||
9cce7a43 CM |
46 | /* |
47 | * cpu_do_idle() | |
48 | * | |
49 | * Idle the processor (wait for interrupt). | |
50 | */ | |
51 | ENTRY(cpu_do_idle) | |
52 | dsb sy // WFI may enter a low-power mode | |
53 | wfi | |
54 | ret | |
55 | ENDPROC(cpu_do_idle) | |
56 | ||
af3cfdbf | 57 | #ifdef CONFIG_CPU_PM |
6732bc65 LP |
58 | /** |
59 | * cpu_do_suspend - save CPU registers context | |
60 | * | |
61 | * x0: virtual address of context pointer | |
62 | */ | |
63 | ENTRY(cpu_do_suspend) | |
64 | mrs x2, tpidr_el0 | |
65 | mrs x3, tpidrro_el0 | |
66 | mrs x4, contextidr_el1 | |
cabe1c81 JM |
67 | mrs x5, cpacr_el1 |
68 | mrs x6, tcr_el1 | |
69 | mrs x7, vbar_el1 | |
70 | mrs x8, mdscr_el1 | |
71 | mrs x9, oslsr_el1 | |
72 | mrs x10, sctlr_el1 | |
623b476f MR |
73 | mrs x11, tpidr_el1 |
74 | mrs x12, sp_el0 | |
6732bc65 | 75 | stp x2, x3, [x0] |
cabe1c81 JM |
76 | stp x4, xzr, [x0, #16] |
77 | stp x5, x6, [x0, #32] | |
78 | stp x7, x8, [x0, #48] | |
79 | stp x9, x10, [x0, #64] | |
623b476f | 80 | stp x11, x12, [x0, #80] |
6732bc65 LP |
81 | ret |
82 | ENDPROC(cpu_do_suspend) | |
83 | ||
84 | /** | |
85 | * cpu_do_resume - restore CPU register context | |
86 | * | |
cabe1c81 | 87 | * x0: Address of context pointer |
6732bc65 | 88 | */ |
b6113038 | 89 | .pushsection ".idmap.text", "ax" |
6732bc65 | 90 | ENTRY(cpu_do_resume) |
6732bc65 LP |
91 | ldp x2, x3, [x0] |
92 | ldp x4, x5, [x0, #16] | |
cabe1c81 JM |
93 | ldp x6, x8, [x0, #32] |
94 | ldp x9, x10, [x0, #48] | |
95 | ldp x11, x12, [x0, #64] | |
623b476f | 96 | ldp x13, x14, [x0, #80] |
6732bc65 LP |
97 | msr tpidr_el0, x2 |
98 | msr tpidrro_el0, x3 | |
99 | msr contextidr_el1, x4 | |
6732bc65 | 100 | msr cpacr_el1, x6 |
cabe1c81 JM |
101 | |
102 | /* Don't change t0sz here, mask those bits when restoring */ | |
103 | mrs x5, tcr_el1 | |
104 | bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH | |
105 | ||
6732bc65 LP |
106 | msr tcr_el1, x8 |
107 | msr vbar_el1, x9 | |
744c6c37 JM |
108 | |
109 | /* | |
110 | * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking | |
111 | * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug | |
0fbeb318 | 112 | * exception. Mask them until local_daif_restore() in cpu_suspend() |
744c6c37 JM |
113 | * resets them. |
114 | */ | |
0fbeb318 | 115 | disable_daif |
6732bc65 | 116 | msr mdscr_el1, x10 |
744c6c37 | 117 | |
cabe1c81 | 118 | msr sctlr_el1, x12 |
623b476f MR |
119 | msr tpidr_el1, x13 |
120 | msr sp_el0, x14 | |
6732bc65 LP |
121 | /* |
122 | * Restore oslsr_el1 by writing oslar_el1 | |
123 | */ | |
124 | ubfx x11, x11, #1, #1 | |
125 | msr oslar_el1, x11 | |
f436b2ac | 126 | reset_pmuserenr_el0 x0 // Disable PMU access from EL0 |
6732bc65 LP |
127 | isb |
128 | ret | |
129 | ENDPROC(cpu_do_resume) | |
b6113038 | 130 | .popsection |
6732bc65 LP |
131 | #endif |
132 | ||
9cce7a43 | 133 | /* |
812944e9 | 134 | * cpu_do_switch_mm(pgd_phys, tsk) |
9cce7a43 CM |
135 | * |
136 | * Set the translation table base pointer to be pgd_phys. | |
137 | * | |
138 | * - pgd_phys - physical address of new TTB | |
139 | */ | |
140 | ENTRY(cpu_do_switch_mm) | |
ea6eac90 | 141 | pre_ttbr0_update_workaround x0, x2, x3 |
5aec715d | 142 | mmid x1, x1 // get mm->context.id |
9cce7a43 CM |
143 | bfi x0, x1, #48, #16 // set the ASID |
144 | msr ttbr0_el1, x0 // set TTBR0 | |
145 | isb | |
f33bcf03 | 146 | post_ttbr0_update_workaround |
104a0c02 | 147 | ret |
9cce7a43 CM |
148 | ENDPROC(cpu_do_switch_mm) |
149 | ||
50e1881d MR |
150 | .pushsection ".idmap.text", "ax" |
151 | /* | |
152 | * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd) | |
153 | * | |
154 | * This is the low-level counterpart to cpu_replace_ttbr1, and should not be | |
155 | * called by anything else. It can only be executed from a TTBR0 mapping. | |
156 | */ | |
157 | ENTRY(idmap_cpu_replace_ttbr1) | |
0fbeb318 | 158 | save_and_disable_daif flags=x2 |
50e1881d MR |
159 | |
160 | adrp x1, empty_zero_page | |
161 | msr ttbr1_el1, x1 | |
162 | isb | |
163 | ||
164 | tlbi vmalle1 | |
165 | dsb nsh | |
166 | isb | |
167 | ||
168 | msr ttbr1_el1, x0 | |
169 | isb | |
170 | ||
0fbeb318 | 171 | restore_daif x2 |
50e1881d MR |
172 | |
173 | ret | |
174 | ENDPROC(idmap_cpu_replace_ttbr1) | |
175 | .popsection | |
176 | ||
9cce7a43 CM |
177 | /* |
178 | * __cpu_setup | |
179 | * | |
180 | * Initialise the processor for turning the MMU on. Return in x0 the | |
181 | * value of the SCTLR_EL1 register. | |
182 | */ | |
b6113038 | 183 | .pushsection ".idmap.text", "ax" |
9cce7a43 | 184 | ENTRY(__cpu_setup) |
fa7aae8a WD |
185 | tlbi vmalle1 // Invalidate local TLB |
186 | dsb nsh | |
9cce7a43 CM |
187 | |
188 | mov x0, #3 << 20 | |
189 | msr cpacr_el1, x0 // Enable FP/ASIMD | |
d8d23fa0 WD |
190 | mov x0, #1 << 12 // Reset mdscr_el1 and disable |
191 | msr mdscr_el1, x0 // access to the DCC from EL0 | |
2ce39ad1 WD |
192 | isb // Unmask debug exceptions now, |
193 | enable_dbg // since this is per-cpu | |
f436b2ac | 194 | reset_pmuserenr_el0 x0 // Disable PMU access from EL0 |
9cce7a43 CM |
195 | /* |
196 | * Memory region attributes for LPAE: | |
197 | * | |
198 | * n = AttrIndx[2:0] | |
199 | * n MAIR | |
200 | * DEVICE_nGnRnE 000 00000000 | |
201 | * DEVICE_nGnRE 001 00000100 | |
202 | * DEVICE_GRE 010 00001100 | |
203 | * NORMAL_NC 011 01000100 | |
204 | * NORMAL 100 11111111 | |
8d446c86 | 205 | * NORMAL_WT 101 10111011 |
9cce7a43 CM |
206 | */ |
207 | ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ | |
208 | MAIR(0x04, MT_DEVICE_nGnRE) | \ | |
209 | MAIR(0x0c, MT_DEVICE_GRE) | \ | |
210 | MAIR(0x44, MT_NORMAL_NC) | \ | |
8d446c86 JZZ |
211 | MAIR(0xff, MT_NORMAL) | \ |
212 | MAIR(0xbb, MT_NORMAL_WT) | |
9cce7a43 CM |
213 | msr mair_el1, x5 |
214 | /* | |
215 | * Prepare SCTLR | |
216 | */ | |
217 | adr x5, crval | |
218 | ldp w5, w6, [x5] | |
219 | mrs x0, sctlr_el1 | |
220 | bic x0, x0, x5 // clear bits | |
221 | orr x0, x0, x6 // set bits | |
222 | /* | |
223 | * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for | |
224 | * both user and kernel. | |
225 | */ | |
35a86976 CM |
226 | ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ |
227 | TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | |
dd006da2 AB |
228 | tcr_set_idmap_t0sz x10, x9 |
229 | ||
87366d8c RMC |
230 | /* |
231 | * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in | |
232 | * TCR_EL1. | |
233 | */ | |
234 | mrs x9, ID_AA64MMFR0_EL1 | |
235 | bfi x10, x9, #32, #3 | |
2f4b829c CM |
236 | #ifdef CONFIG_ARM64_HW_AFDBM |
237 | /* | |
238 | * Hardware update of the Access and Dirty bits. | |
239 | */ | |
240 | mrs x9, ID_AA64MMFR1_EL1 | |
241 | and x9, x9, #0xf | |
242 | cbz x9, 2f | |
243 | cmp x9, #2 | |
244 | b.lt 1f | |
245 | orr x10, x10, #TCR_HD // hardware Dirty flag update | |
246 | 1: orr x10, x10, #TCR_HA // hardware Access flag update | |
247 | 2: | |
248 | #endif /* CONFIG_ARM64_HW_AFDBM */ | |
9cce7a43 CM |
249 | msr tcr_el1, x10 |
250 | ret // return to head.S | |
251 | ENDPROC(__cpu_setup) | |
252 | ||
253 | /* | |
9f71ac96 SP |
254 | * We set the desired value explicitly, including those of the |
255 | * reserved bits. The values of bits EE & E0E were set early in | |
256 | * el2_setup, which are left untouched below. | |
257 | * | |
9cce7a43 CM |
258 | * n n T |
259 | * U E WT T UD US IHBS | |
260 | * CE0 XWHW CZ ME TEEA S | |
261 | * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM | |
9f71ac96 SP |
262 | * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved |
263 | * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings | |
9cce7a43 CM |
264 | */ |
265 | .type crval, #object | |
266 | crval: | |
9f71ac96 SP |
267 | .word 0xfcffffff // clear |
268 | .word 0x34d5d91d // set | |
b6113038 | 269 | .popsection |