]>
Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
ec7748b5 | 27 | select HAVE_IDE |
42d4b839 | 28 | select HAVE_OPROFILE |
1394f032 | 29 | |
e3defffe AL |
30 | config ZONE_DMA |
31 | bool | |
32 | default y | |
33 | ||
1394f032 BW |
34 | config GENERIC_FIND_NEXT_BIT |
35 | bool | |
36 | default y | |
37 | ||
38 | config GENERIC_HWEIGHT | |
39 | bool | |
40 | default y | |
41 | ||
42 | config GENERIC_HARDIRQS | |
43 | bool | |
44 | default y | |
45 | ||
46 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 47 | bool |
1394f032 BW |
48 | default y |
49 | ||
b2d1583f | 50 | config GENERIC_GPIO |
1394f032 BW |
51 | bool |
52 | default y | |
53 | ||
54 | config FORCE_MAX_ZONEORDER | |
55 | int | |
56 | default "14" | |
57 | ||
58 | config GENERIC_CALIBRATE_DELAY | |
59 | bool | |
60 | default y | |
61 | ||
7d2284b0 MD |
62 | config HARDWARE_PM |
63 | def_bool y | |
64 | depends on OPROFILE | |
65 | ||
1394f032 | 66 | source "init/Kconfig" |
dc52ddc0 | 67 | |
1394f032 BW |
68 | source "kernel/Kconfig.preempt" |
69 | ||
dc52ddc0 MH |
70 | source "kernel/Kconfig.freezer" |
71 | ||
1394f032 BW |
72 | menu "Blackfin Processor Options" |
73 | ||
74 | comment "Processor and Board Settings" | |
75 | ||
76 | choice | |
77 | prompt "CPU" | |
78 | default BF533 | |
79 | ||
2f6f4bcd BW |
80 | config BF512 |
81 | bool "BF512" | |
82 | help | |
83 | BF512 Processor Support. | |
84 | ||
85 | config BF514 | |
86 | bool "BF514" | |
87 | help | |
88 | BF514 Processor Support. | |
89 | ||
90 | config BF516 | |
91 | bool "BF516" | |
92 | help | |
93 | BF516 Processor Support. | |
94 | ||
95 | config BF518 | |
96 | bool "BF518" | |
97 | help | |
98 | BF518 Processor Support. | |
99 | ||
59003145 MH |
100 | config BF522 |
101 | bool "BF522" | |
102 | help | |
103 | BF522 Processor Support. | |
104 | ||
1545a111 MF |
105 | config BF523 |
106 | bool "BF523" | |
107 | help | |
108 | BF523 Processor Support. | |
109 | ||
110 | config BF524 | |
111 | bool "BF524" | |
112 | help | |
113 | BF524 Processor Support. | |
114 | ||
59003145 MH |
115 | config BF525 |
116 | bool "BF525" | |
117 | help | |
118 | BF525 Processor Support. | |
119 | ||
1545a111 MF |
120 | config BF526 |
121 | bool "BF526" | |
122 | help | |
123 | BF526 Processor Support. | |
124 | ||
59003145 MH |
125 | config BF527 |
126 | bool "BF527" | |
127 | help | |
128 | BF527 Processor Support. | |
129 | ||
1394f032 BW |
130 | config BF531 |
131 | bool "BF531" | |
132 | help | |
133 | BF531 Processor Support. | |
134 | ||
135 | config BF532 | |
136 | bool "BF532" | |
137 | help | |
138 | BF532 Processor Support. | |
139 | ||
140 | config BF533 | |
141 | bool "BF533" | |
142 | help | |
143 | BF533 Processor Support. | |
144 | ||
145 | config BF534 | |
146 | bool "BF534" | |
147 | help | |
148 | BF534 Processor Support. | |
149 | ||
150 | config BF536 | |
151 | bool "BF536" | |
152 | help | |
153 | BF536 Processor Support. | |
154 | ||
155 | config BF537 | |
156 | bool "BF537" | |
157 | help | |
158 | BF537 Processor Support. | |
159 | ||
dc26aec2 MH |
160 | config BF538 |
161 | bool "BF538" | |
162 | help | |
163 | BF538 Processor Support. | |
164 | ||
165 | config BF539 | |
166 | bool "BF539" | |
167 | help | |
168 | BF539 Processor Support. | |
169 | ||
24a07a12 RH |
170 | config BF542 |
171 | bool "BF542" | |
172 | help | |
173 | BF542 Processor Support. | |
174 | ||
175 | config BF544 | |
176 | bool "BF544" | |
177 | help | |
178 | BF544 Processor Support. | |
179 | ||
7c7fd170 MF |
180 | config BF547 |
181 | bool "BF547" | |
182 | help | |
183 | BF547 Processor Support. | |
184 | ||
24a07a12 RH |
185 | config BF548 |
186 | bool "BF548" | |
187 | help | |
188 | BF548 Processor Support. | |
189 | ||
190 | config BF549 | |
191 | bool "BF549" | |
192 | help | |
193 | BF549 Processor Support. | |
194 | ||
1394f032 BW |
195 | config BF561 |
196 | bool "BF561" | |
197 | help | |
cd88b4dc | 198 | BF561 Processor Support. |
1394f032 BW |
199 | |
200 | endchoice | |
201 | ||
0c0497c2 MF |
202 | config BF_REV_MIN |
203 | int | |
2f6f4bcd | 204 | default 0 if (BF51x || BF52x || BF54x) |
0c0497c2 MF |
205 | default 2 if (BF537 || BF536 || BF534) |
206 | default 3 if (BF561 ||BF533 || BF532 || BF531) | |
2f6f4bcd | 207 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
208 | |
209 | config BF_REV_MAX | |
210 | int | |
2f6f4bcd | 211 | default 2 if (BF51x || BF52x || BF54x) |
0c0497c2 | 212 | default 3 if (BF537 || BF536 || BF534) |
2f6f4bcd | 213 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
214 | default 6 if (BF533 || BF532 || BF531) |
215 | ||
1394f032 BW |
216 | choice |
217 | prompt "Silicon Rev" | |
2f6f4bcd | 218 | default BF_REV_0_1 if (BF51x || BF52x || BF54x) |
46ce0d9a MF |
219 | default BF_REV_0_2 if (BF534 || BF536 || BF537) |
220 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) | |
24a07a12 RH |
221 | |
222 | config BF_REV_0_0 | |
223 | bool "0.0" | |
2f6f4bcd | 224 | depends on (BF51x || BF52x || BF54x) |
59003145 MH |
225 | |
226 | config BF_REV_0_1 | |
d07f4380 MF |
227 | bool "0.1" |
228 | depends on (BF52x || BF54x) | |
1394f032 BW |
229 | |
230 | config BF_REV_0_2 | |
231 | bool "0.2" | |
49f7253c | 232 | depends on (BF52x || BF537 || BF536 || BF534 || BF54x) |
1394f032 BW |
233 | |
234 | config BF_REV_0_3 | |
235 | bool "0.3" | |
236 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
237 | ||
238 | config BF_REV_0_4 | |
239 | bool "0.4" | |
dc26aec2 | 240 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
241 | |
242 | config BF_REV_0_5 | |
243 | bool "0.5" | |
dc26aec2 | 244 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 245 | |
49f7253c MF |
246 | config BF_REV_0_6 |
247 | bool "0.6" | |
248 | depends on (BF533 || BF532 || BF531) | |
249 | ||
de3025f4 JZ |
250 | config BF_REV_ANY |
251 | bool "any" | |
252 | ||
253 | config BF_REV_NONE | |
254 | bool "none" | |
255 | ||
1394f032 BW |
256 | endchoice |
257 | ||
2f6f4bcd BW |
258 | config BF51x |
259 | bool | |
260 | depends on (BF512 || BF514 || BF516 || BF518) | |
261 | default y | |
262 | ||
59003145 MH |
263 | config BF52x |
264 | bool | |
1545a111 | 265 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
266 | default y |
267 | ||
24a07a12 RH |
268 | config BF53x |
269 | bool | |
270 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
271 | default y | |
272 | ||
273 | config BF54x | |
274 | bool | |
7c7fd170 | 275 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
276 | default y |
277 | ||
1394f032 BW |
278 | config MEM_GENERIC_BOARD |
279 | bool | |
280 | depends on GENERIC_BOARD | |
281 | default y | |
282 | ||
283 | config MEM_MT48LC64M4A2FB_7E | |
284 | bool | |
285 | depends on (BFIN533_STAMP) | |
286 | default y | |
287 | ||
288 | config MEM_MT48LC16M16A2TG_75 | |
289 | bool | |
290 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 | 291 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
9db144fe | 292 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
1394f032 BW |
293 | default y |
294 | ||
295 | config MEM_MT48LC32M8A2_75 | |
296 | bool | |
dc26aec2 | 297 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
298 | default y |
299 | ||
300 | config MEM_MT48LC8M32B2B5_7 | |
301 | bool | |
302 | depends on (BFIN561_BLUETECHNIX_CM) | |
303 | default y | |
304 | ||
59003145 MH |
305 | config MEM_MT48LC32M16A2TG_75 |
306 | bool | |
8cc7117e | 307 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
59003145 MH |
308 | default y |
309 | ||
2f6f4bcd | 310 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 311 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
312 | source "arch/blackfin/mach-bf533/Kconfig" |
313 | source "arch/blackfin/mach-bf561/Kconfig" | |
314 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 315 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 316 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
317 | |
318 | menu "Board customizations" | |
319 | ||
320 | config CMDLINE_BOOL | |
321 | bool "Default bootloader kernel arguments" | |
322 | ||
323 | config CMDLINE | |
324 | string "Initial kernel command string" | |
325 | depends on CMDLINE_BOOL | |
326 | default "console=ttyBF0,57600" | |
327 | help | |
328 | If you don't have a boot loader capable of passing a command line string | |
329 | to the kernel, you may specify one here. As a minimum, you should specify | |
330 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
331 | ||
5f004c20 MF |
332 | config BOOT_LOAD |
333 | hex "Kernel load address for booting" | |
334 | default "0x1000" | |
335 | range 0x1000 0x20000000 | |
336 | help | |
337 | This option allows you to set the load address of the kernel. | |
338 | This can be useful if you are on a board which has a small amount | |
339 | of memory or you wish to reserve some memory at the beginning of | |
340 | the address space. | |
341 | ||
342 | Note that you need to keep this value above 4k (0x1000) as this | |
343 | memory region is used to capture NULL pointer references as well | |
344 | as some core kernel functions. | |
345 | ||
8cc7117e MH |
346 | config ROM_BASE |
347 | hex "Kernel ROM Base" | |
348 | default "0x20040000" | |
349 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
350 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
351 | help | |
352 | ||
f16295e7 | 353 | comment "Clock/PLL Setup" |
1394f032 BW |
354 | |
355 | config CLKIN_HZ | |
2fb6cb41 | 356 | int "Frequency of the crystal on the board in Hz" |
1394f032 BW |
357 | default "11059200" if BFIN533_STAMP |
358 | default "27000000" if BFIN533_EZKIT | |
2f6f4bcd | 359 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD) |
1394f032 BW |
360 | default "30000000" if BFIN561_EZKIT |
361 | default "24576000" if PNAV10 | |
5d1617b2 | 362 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
363 | help |
364 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
365 | Warning: This value should match the crystal on the board. Otherwise, |
366 | peripherals won't work properly. | |
1394f032 | 367 | |
f16295e7 RG |
368 | config BFIN_KERNEL_CLOCK |
369 | bool "Re-program Clocks while Kernel boots?" | |
370 | default n | |
371 | help | |
372 | This option decides if kernel clocks are re-programed from the | |
373 | bootloader settings. If the clocks are not set, the SDRAM settings | |
374 | are also not changed, and the Bootloader does 100% of the hardware | |
375 | configuration. | |
376 | ||
377 | config PLL_BYPASS | |
e4e9a7ad MF |
378 | bool "Bypass PLL" |
379 | depends on BFIN_KERNEL_CLOCK | |
380 | default n | |
f16295e7 RG |
381 | |
382 | config CLKIN_HALF | |
383 | bool "Half Clock In" | |
384 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
385 | default n | |
386 | help | |
387 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
388 | ||
389 | config VCO_MULT | |
390 | int "VCO Multiplier" | |
391 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
392 | range 1 64 | |
393 | default "22" if BFIN533_EZKIT | |
394 | default "45" if BFIN533_STAMP | |
dc26aec2 | 395 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 396 | default "22" if BFIN533_BLUETECHNIX_CM |
9db144fe | 397 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 398 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 399 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
400 | help |
401 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
402 | PLL Frequency = (Crystal Frequency) * (this setting) | |
403 | ||
404 | choice | |
405 | prompt "Core Clock Divider" | |
406 | depends on BFIN_KERNEL_CLOCK | |
407 | default CCLK_DIV_1 | |
408 | help | |
409 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
410 | Core Frequency = (PLL frequency) / (this setting) | |
411 | ||
412 | config CCLK_DIV_1 | |
413 | bool "1" | |
414 | ||
415 | config CCLK_DIV_2 | |
416 | bool "2" | |
417 | ||
418 | config CCLK_DIV_4 | |
419 | bool "4" | |
420 | ||
421 | config CCLK_DIV_8 | |
422 | bool "8" | |
423 | endchoice | |
424 | ||
425 | config SCLK_DIV | |
426 | int "System Clock Divider" | |
427 | depends on BFIN_KERNEL_CLOCK | |
428 | range 1 15 | |
5f004c20 | 429 | default 5 |
f16295e7 RG |
430 | help |
431 | This sets the frequency of the system clock (including SDRAM or DDR). | |
432 | This can be between 1 and 15 | |
433 | System Clock = (PLL frequency) / (this setting) | |
434 | ||
5f004c20 MF |
435 | choice |
436 | prompt "DDR SDRAM Chip Type" | |
437 | depends on BFIN_KERNEL_CLOCK | |
438 | depends on BF54x | |
439 | default MEM_MT46V32M16_5B | |
440 | ||
441 | config MEM_MT46V32M16_6T | |
442 | bool "MT46V32M16_6T" | |
443 | ||
444 | config MEM_MT46V32M16_5B | |
445 | bool "MT46V32M16_5B" | |
446 | endchoice | |
447 | ||
7eb2c23f MF |
448 | config MAX_MEM_SIZE |
449 | int "Max SDRAM Memory Size in MBytes" | |
450 | depends on !MPU | |
451 | default 512 | |
452 | help | |
453 | This is the max memory size that the kernel will create CPLB | |
454 | tables for. Your system will not be able to handle any more. | |
455 | ||
f16295e7 RG |
456 | # |
457 | # Max & Min Speeds for various Chips | |
458 | # | |
459 | config MAX_VCO_HZ | |
460 | int | |
2f6f4bcd BW |
461 | default 400000000 if BF512 |
462 | default 400000000 if BF514 | |
463 | default 400000000 if BF516 | |
464 | default 400000000 if BF518 | |
f16295e7 | 465 | default 600000000 if BF522 |
1545a111 MF |
466 | default 400000000 if BF523 |
467 | default 400000000 if BF524 | |
f16295e7 | 468 | default 600000000 if BF525 |
1545a111 | 469 | default 400000000 if BF526 |
f16295e7 RG |
470 | default 600000000 if BF527 |
471 | default 400000000 if BF531 | |
472 | default 400000000 if BF532 | |
473 | default 750000000 if BF533 | |
474 | default 500000000 if BF534 | |
475 | default 400000000 if BF536 | |
476 | default 600000000 if BF537 | |
f72eecb9 RG |
477 | default 533333333 if BF538 |
478 | default 533333333 if BF539 | |
f16295e7 | 479 | default 600000000 if BF542 |
f72eecb9 | 480 | default 533333333 if BF544 |
1545a111 MF |
481 | default 600000000 if BF547 |
482 | default 600000000 if BF548 | |
f72eecb9 | 483 | default 533333333 if BF549 |
f16295e7 RG |
484 | default 600000000 if BF561 |
485 | ||
486 | config MIN_VCO_HZ | |
487 | int | |
488 | default 50000000 | |
489 | ||
490 | config MAX_SCLK_HZ | |
491 | int | |
f72eecb9 | 492 | default 133333333 |
f16295e7 RG |
493 | |
494 | config MIN_SCLK_HZ | |
495 | int | |
496 | default 27000000 | |
497 | ||
498 | comment "Kernel Timer/Scheduler" | |
499 | ||
500 | source kernel/Kconfig.hz | |
501 | ||
8b5f79f9 VM |
502 | config GENERIC_TIME |
503 | bool "Generic time" | |
504 | default y | |
505 | ||
506 | config GENERIC_CLOCKEVENTS | |
507 | bool "Generic clock events" | |
508 | depends on GENERIC_TIME | |
509 | default y | |
510 | ||
511 | config CYCLES_CLOCKSOURCE | |
512 | bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" | |
513 | depends on EXPERIMENTAL | |
514 | depends on GENERIC_CLOCKEVENTS | |
515 | depends on !BFIN_SCRATCH_REG_CYCLES | |
516 | default n | |
517 | help | |
518 | If you say Y here, you will enable support for using the 'cycles' | |
519 | registers as a clock source. Doing so means you will be unable to | |
520 | safely write to the 'cycles' register during runtime. You will | |
521 | still be able to read it (such as for performance monitoring), but | |
522 | writing the registers will most likely crash the kernel. | |
523 | ||
524 | source kernel/time/Kconfig | |
525 | ||
5f004c20 | 526 | comment "Misc" |
971d5bc4 | 527 | |
f0b5d12f MF |
528 | choice |
529 | prompt "Blackfin Exception Scratch Register" | |
530 | default BFIN_SCRATCH_REG_RETN | |
531 | help | |
532 | Select the resource to reserve for the Exception handler: | |
533 | - RETN: Non-Maskable Interrupt (NMI) | |
534 | - RETE: Exception Return (JTAG/ICE) | |
535 | - CYCLES: Performance counter | |
536 | ||
537 | If you are unsure, please select "RETN". | |
538 | ||
539 | config BFIN_SCRATCH_REG_RETN | |
540 | bool "RETN" | |
541 | help | |
542 | Use the RETN register in the Blackfin exception handler | |
543 | as a stack scratch register. This means you cannot | |
544 | safely use NMI on the Blackfin while running Linux, but | |
545 | you can debug the system with a JTAG ICE and use the | |
546 | CYCLES performance registers. | |
547 | ||
548 | If you are unsure, please select "RETN". | |
549 | ||
550 | config BFIN_SCRATCH_REG_RETE | |
551 | bool "RETE" | |
552 | help | |
553 | Use the RETE register in the Blackfin exception handler | |
554 | as a stack scratch register. This means you cannot | |
555 | safely use a JTAG ICE while debugging a Blackfin board, | |
556 | but you can safely use the CYCLES performance registers | |
557 | and the NMI. | |
558 | ||
559 | If you are unsure, please select "RETN". | |
560 | ||
561 | config BFIN_SCRATCH_REG_CYCLES | |
562 | bool "CYCLES" | |
563 | help | |
564 | Use the CYCLES register in the Blackfin exception handler | |
565 | as a stack scratch register. This means you cannot | |
566 | safely use the CYCLES performance registers on a Blackfin | |
567 | board at anytime, but you can debug the system with a JTAG | |
568 | ICE and use the NMI. | |
569 | ||
570 | If you are unsure, please select "RETN". | |
571 | ||
572 | endchoice | |
573 | ||
1394f032 BW |
574 | endmenu |
575 | ||
576 | ||
577 | menu "Blackfin Kernel Optimizations" | |
578 | ||
1394f032 BW |
579 | comment "Memory Optimizations" |
580 | ||
581 | config I_ENTRY_L1 | |
582 | bool "Locate interrupt entry code in L1 Memory" | |
583 | default y | |
584 | help | |
01dd2fbf ML |
585 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
586 | into L1 instruction memory. (less latency) | |
1394f032 BW |
587 | |
588 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 589 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
590 | default y |
591 | help | |
01dd2fbf | 592 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 593 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 594 | (less latency) |
1394f032 BW |
595 | |
596 | config DO_IRQ_L1 | |
597 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
598 | default y | |
599 | help | |
01dd2fbf ML |
600 | If enabled, the frequently called do_irq dispatcher function is linked |
601 | into L1 instruction memory. (less latency) | |
1394f032 BW |
602 | |
603 | config CORE_TIMER_IRQ_L1 | |
604 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
605 | default y | |
606 | help | |
01dd2fbf ML |
607 | If enabled, the frequently called timer_interrupt() function is linked |
608 | into L1 instruction memory. (less latency) | |
1394f032 BW |
609 | |
610 | config IDLE_L1 | |
611 | bool "Locate frequently idle function in L1 Memory" | |
612 | default y | |
613 | help | |
01dd2fbf ML |
614 | If enabled, the frequently called idle function is linked |
615 | into L1 instruction memory. (less latency) | |
1394f032 BW |
616 | |
617 | config SCHEDULE_L1 | |
618 | bool "Locate kernel schedule function in L1 Memory" | |
619 | default y | |
620 | help | |
01dd2fbf ML |
621 | If enabled, the frequently called kernel schedule is linked |
622 | into L1 instruction memory. (less latency) | |
1394f032 BW |
623 | |
624 | config ARITHMETIC_OPS_L1 | |
625 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
626 | default y | |
627 | help | |
01dd2fbf ML |
628 | If enabled, arithmetic functions are linked |
629 | into L1 instruction memory. (less latency) | |
1394f032 BW |
630 | |
631 | config ACCESS_OK_L1 | |
632 | bool "Locate access_ok function in L1 Memory" | |
633 | default y | |
634 | help | |
01dd2fbf ML |
635 | If enabled, the access_ok function is linked |
636 | into L1 instruction memory. (less latency) | |
1394f032 BW |
637 | |
638 | config MEMSET_L1 | |
639 | bool "Locate memset function in L1 Memory" | |
640 | default y | |
641 | help | |
01dd2fbf ML |
642 | If enabled, the memset function is linked |
643 | into L1 instruction memory. (less latency) | |
1394f032 BW |
644 | |
645 | config MEMCPY_L1 | |
646 | bool "Locate memcpy function in L1 Memory" | |
647 | default y | |
648 | help | |
01dd2fbf ML |
649 | If enabled, the memcpy function is linked |
650 | into L1 instruction memory. (less latency) | |
1394f032 BW |
651 | |
652 | config SYS_BFIN_SPINLOCK_L1 | |
653 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
654 | default y | |
655 | help | |
01dd2fbf ML |
656 | If enabled, sys_bfin_spinlock function is linked |
657 | into L1 instruction memory. (less latency) | |
1394f032 BW |
658 | |
659 | config IP_CHECKSUM_L1 | |
660 | bool "Locate IP Checksum function in L1 Memory" | |
661 | default n | |
662 | help | |
01dd2fbf ML |
663 | If enabled, the IP Checksum function is linked |
664 | into L1 instruction memory. (less latency) | |
1394f032 BW |
665 | |
666 | config CACHELINE_ALIGNED_L1 | |
667 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
668 | default y if !BF54x |
669 | default n if BF54x | |
1394f032 BW |
670 | depends on !BF531 |
671 | help | |
01dd2fbf ML |
672 | If enabled, cacheline_anligned data is linked |
673 | into L1 data memory. (less latency) | |
1394f032 BW |
674 | |
675 | config SYSCALL_TAB_L1 | |
676 | bool "Locate Syscall Table L1 Data Memory" | |
677 | default n | |
678 | depends on !BF531 | |
679 | help | |
01dd2fbf ML |
680 | If enabled, the Syscall LUT is linked |
681 | into L1 data memory. (less latency) | |
1394f032 BW |
682 | |
683 | config CPLB_SWITCH_TAB_L1 | |
684 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
685 | default n | |
686 | depends on !BF531 | |
687 | help | |
01dd2fbf ML |
688 | If enabled, the CPLB Switch Tables are linked |
689 | into L1 data memory. (less latency) | |
1394f032 | 690 | |
ca87b7ad GY |
691 | config APP_STACK_L1 |
692 | bool "Support locating application stack in L1 Scratch Memory" | |
693 | default y | |
694 | help | |
695 | If enabled the application stack can be located in L1 | |
696 | scratch memory (less latency). | |
697 | ||
698 | Currently only works with FLAT binaries. | |
699 | ||
6ad2b84c MF |
700 | config EXCEPTION_L1_SCRATCH |
701 | bool "Locate exception stack in L1 Scratch Memory" | |
702 | default n | |
703 | depends on !APP_STACK_L1 && !SYSCALL_TAB_L1 | |
704 | help | |
705 | Whenever an exception occurs, use the L1 Scratch memory for | |
706 | stack storage. You cannot place the stacks of FLAT binaries | |
707 | in L1 when using this option. | |
708 | ||
709 | If you don't use L1 Scratch, then you should say Y here. | |
710 | ||
251383c7 RG |
711 | comment "Speed Optimizations" |
712 | config BFIN_INS_LOWOVERHEAD | |
713 | bool "ins[bwl] low overhead, higher interrupt latency" | |
714 | default y | |
715 | help | |
716 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
717 | they can be interrupted at any time (even after they have been issued | |
718 | on to the external bus), and re-issued after the interrupt occurs. | |
719 | For memory - this is not a big deal, since memory does not change if | |
720 | it sees a read. | |
721 | ||
722 | If a FIFO is sitting on the end of the read, it will see two reads, | |
723 | when the core only sees one since the FIFO receives both the read | |
724 | which is cancelled (and not delivered to the core) and the one which | |
725 | is re-issued (which is delivered to the core). | |
726 | ||
727 | To solve this, interrupts are turned off before reads occur to | |
728 | I/O space. This option controls which the overhead/latency of | |
729 | controlling interrupts during this time | |
730 | "n" turns interrupts off every read | |
731 | (higher overhead, but lower interrupt latency) | |
732 | "y" turns interrupts off every loop | |
733 | (low overhead, but longer interrupt latency) | |
734 | ||
735 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
736 | interrupt latency issues, it is safe and OK to turn this off. | |
737 | ||
1394f032 BW |
738 | endmenu |
739 | ||
740 | ||
741 | choice | |
742 | prompt "Kernel executes from" | |
743 | help | |
744 | Choose the memory type that the kernel will be running in. | |
745 | ||
746 | config RAMKERNEL | |
747 | bool "RAM" | |
748 | help | |
749 | The kernel will be resident in RAM when running. | |
750 | ||
751 | config ROMKERNEL | |
752 | bool "ROM" | |
753 | help | |
754 | The kernel will be resident in FLASH/ROM when running. | |
755 | ||
756 | endchoice | |
757 | ||
758 | source "mm/Kconfig" | |
759 | ||
780431e3 MF |
760 | config BFIN_GPTIMERS |
761 | tristate "Enable Blackfin General Purpose Timers API" | |
762 | default n | |
763 | help | |
764 | Enable support for the General Purpose Timers API. If you | |
765 | are unsure, say N. | |
766 | ||
767 | To compile this driver as a module, choose M here: the module | |
768 | will be called gptimers.ko. | |
769 | ||
1394f032 BW |
770 | config BFIN_DMA_5XX |
771 | bool "Enable DMA Support" | |
1394f032 BW |
772 | default y |
773 | help | |
d292b000 | 774 | DMA driver for Blackfin parts. |
1394f032 BW |
775 | |
776 | choice | |
d292b000 | 777 | prompt "Uncached DMA region" |
1394f032 | 778 | default DMA_UNCACHED_1M |
247537b9 | 779 | depends on BFIN_DMA_5XX |
86ad7932 CC |
780 | config DMA_UNCACHED_4M |
781 | bool "Enable 4M DMA region" | |
1394f032 BW |
782 | config DMA_UNCACHED_2M |
783 | bool "Enable 2M DMA region" | |
784 | config DMA_UNCACHED_1M | |
785 | bool "Enable 1M DMA region" | |
786 | config DMA_UNCACHED_NONE | |
787 | bool "Disable DMA region" | |
788 | endchoice | |
789 | ||
790 | ||
791 | comment "Cache Support" | |
3bebca2d | 792 | config BFIN_ICACHE |
1394f032 | 793 | bool "Enable ICACHE" |
3bebca2d | 794 | config BFIN_DCACHE |
1394f032 | 795 | bool "Enable DCACHE" |
3bebca2d | 796 | config BFIN_DCACHE_BANKA |
1394f032 | 797 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 798 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 799 | default n |
3bebca2d RG |
800 | config BFIN_ICACHE_LOCK |
801 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
802 | |
803 | choice | |
804 | prompt "Policy" | |
3bebca2d RG |
805 | depends on BFIN_DCACHE |
806 | default BFIN_WB | |
807 | config BFIN_WB | |
1394f032 BW |
808 | bool "Write back" |
809 | help | |
810 | Write Back Policy: | |
811 | Cached data will be written back to SDRAM only when needed. | |
812 | This can give a nice increase in performance, but beware of | |
813 | broken drivers that do not properly invalidate/flush their | |
814 | cache. | |
815 | ||
816 | Write Through Policy: | |
817 | Cached data will always be written back to SDRAM when the | |
818 | cache is updated. This is a completely safe setting, but | |
819 | performance is worse than Write Back. | |
820 | ||
821 | If you are unsure of the options and you want to be safe, | |
822 | then go with Write Through. | |
823 | ||
3bebca2d | 824 | config BFIN_WT |
1394f032 BW |
825 | bool "Write through" |
826 | help | |
827 | Write Back Policy: | |
828 | Cached data will be written back to SDRAM only when needed. | |
829 | This can give a nice increase in performance, but beware of | |
830 | broken drivers that do not properly invalidate/flush their | |
831 | cache. | |
832 | ||
833 | Write Through Policy: | |
834 | Cached data will always be written back to SDRAM when the | |
835 | cache is updated. This is a completely safe setting, but | |
836 | performance is worse than Write Back. | |
837 | ||
838 | If you are unsure of the options and you want to be safe, | |
839 | then go with Write Through. | |
840 | ||
841 | endchoice | |
842 | ||
f099f39a SZ |
843 | config BFIN_L2_CACHEABLE |
844 | bool "Cache L2 SRAM" | |
845 | depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561) | |
846 | default n | |
847 | help | |
848 | Select to make L2 SRAM cacheable in L1 data and instruction cache. | |
849 | ||
b97b8a99 BS |
850 | config MPU |
851 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
852 | default n | |
853 | help | |
854 | Use the processor's MPU to protect applications from accessing | |
855 | memory they do not own. This comes at a performance penalty | |
856 | and is recommended only for debugging. | |
857 | ||
1394f032 BW |
858 | comment "Asynchonous Memory Configuration" |
859 | ||
ddf416b2 | 860 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
861 | config C_AMCKEN |
862 | bool "Enable CLKOUT" | |
863 | default y | |
864 | ||
865 | config C_CDPRIO | |
866 | bool "DMA has priority over core for ext. accesses" | |
867 | default n | |
868 | ||
869 | config C_B0PEN | |
870 | depends on BF561 | |
871 | bool "Bank 0 16 bit packing enable" | |
872 | default y | |
873 | ||
874 | config C_B1PEN | |
875 | depends on BF561 | |
876 | bool "Bank 1 16 bit packing enable" | |
877 | default y | |
878 | ||
879 | config C_B2PEN | |
880 | depends on BF561 | |
881 | bool "Bank 2 16 bit packing enable" | |
882 | default y | |
883 | ||
884 | config C_B3PEN | |
885 | depends on BF561 | |
886 | bool "Bank 3 16 bit packing enable" | |
887 | default n | |
888 | ||
889 | choice | |
890 | prompt"Enable Asynchonous Memory Banks" | |
891 | default C_AMBEN_ALL | |
892 | ||
893 | config C_AMBEN | |
894 | bool "Disable All Banks" | |
895 | ||
896 | config C_AMBEN_B0 | |
897 | bool "Enable Bank 0" | |
898 | ||
899 | config C_AMBEN_B0_B1 | |
900 | bool "Enable Bank 0 & 1" | |
901 | ||
902 | config C_AMBEN_B0_B1_B2 | |
903 | bool "Enable Bank 0 & 1 & 2" | |
904 | ||
905 | config C_AMBEN_ALL | |
906 | bool "Enable All Banks" | |
907 | endchoice | |
908 | endmenu | |
909 | ||
910 | menu "EBIU_AMBCTL Control" | |
911 | config BANK_0 | |
912 | hex "Bank 0" | |
913 | default 0x7BB0 | |
914 | ||
915 | config BANK_1 | |
916 | hex "Bank 1" | |
917 | default 0x7BB0 | |
197fba56 | 918 | default 0x5558 if BF54x |
1394f032 BW |
919 | |
920 | config BANK_2 | |
921 | hex "Bank 2" | |
922 | default 0x7BB0 | |
923 | ||
924 | config BANK_3 | |
925 | hex "Bank 3" | |
926 | default 0x99B3 | |
927 | endmenu | |
928 | ||
e40540b3 SZ |
929 | config EBIU_MBSCTLVAL |
930 | hex "EBIU Bank Select Control Register" | |
931 | depends on BF54x | |
932 | default 0 | |
933 | ||
934 | config EBIU_MODEVAL | |
935 | hex "Flash Memory Mode Control Register" | |
936 | depends on BF54x | |
937 | default 1 | |
938 | ||
939 | config EBIU_FCTLVAL | |
940 | hex "Flash Memory Bank Control Register" | |
941 | depends on BF54x | |
942 | default 6 | |
1394f032 BW |
943 | endmenu |
944 | ||
945 | ############################################################################# | |
946 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
947 | ||
948 | config PCI | |
949 | bool "PCI support" | |
a95ca3b2 | 950 | depends on BROKEN |
1394f032 BW |
951 | help |
952 | Support for PCI bus. | |
953 | ||
954 | source "drivers/pci/Kconfig" | |
955 | ||
956 | config HOTPLUG | |
957 | bool "Support for hot-pluggable device" | |
958 | help | |
959 | Say Y here if you want to plug devices into your computer while | |
960 | the system is running, and be able to use them quickly. In many | |
961 | cases, the devices can likewise be unplugged at any time too. | |
962 | ||
963 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
964 | size devices such as network cards, modems or hard drives which are | |
965 | plugged into slots found on all modern laptop computers. Another | |
966 | example, used on modern desktops as well as laptops, is USB. | |
967 | ||
a81792f6 JB |
968 | Enable HOTPLUG and build a modular kernel. Get agent software |
969 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
970 | Then your kernel will automatically call out to a user mode "policy |
971 | agent" (/sbin/hotplug) to load modules and set up software needed | |
972 | to use devices as you hotplug them. | |
973 | ||
974 | source "drivers/pcmcia/Kconfig" | |
975 | ||
976 | source "drivers/pci/hotplug/Kconfig" | |
977 | ||
978 | endmenu | |
979 | ||
980 | menu "Executable file formats" | |
981 | ||
982 | source "fs/Kconfig.binfmt" | |
983 | ||
984 | endmenu | |
985 | ||
986 | menu "Power management options" | |
987 | source "kernel/power/Kconfig" | |
988 | ||
f4cb5700 JB |
989 | config ARCH_SUSPEND_POSSIBLE |
990 | def_bool y | |
991 | depends on !SMP | |
992 | ||
1394f032 | 993 | choice |
1efc80b5 | 994 | prompt "Standby Power Saving Mode" |
1394f032 | 995 | depends on PM |
cfefe3c6 MH |
996 | default PM_BFIN_SLEEP_DEEPER |
997 | config PM_BFIN_SLEEP_DEEPER | |
998 | bool "Sleep Deeper" | |
999 | help | |
1000 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1001 | power dissipation by disabling the clock to the processor core (CCLK). | |
1002 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1003 | to 0.85 V to provide the greatest power savings, while preserving the | |
1004 | processor state. | |
1005 | The PLL and system clock (SCLK) continue to operate at a very low | |
1006 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1007 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1008 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1009 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1010 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1011 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1012 | ||
1efc80b5 MH |
1013 | If unsure, select "Sleep Deeper". |
1014 | ||
cfefe3c6 MH |
1015 | config PM_BFIN_SLEEP |
1016 | bool "Sleep" | |
1017 | help | |
1018 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1019 | dissipation by disabling the clock to the processor core (CCLK). | |
1020 | The PLL and system clock (SCLK), however, continue to operate in | |
1021 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1022 | up the processor. When in the sleep mode, system DMA access to L1 |
1023 | memory is not supported. | |
1024 | ||
1025 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1026 | endchoice |
1394f032 | 1027 | |
1394f032 | 1028 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1029 | bool "Allow Wakeup from Standby by GPIO" |
1394f032 BW |
1030 | |
1031 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1032 | int "GPIO number" |
1394f032 BW |
1033 | range 0 47 |
1034 | depends on PM_WAKEUP_BY_GPIO | |
1035 | default 2 if BFIN537_STAMP | |
1036 | ||
1037 | choice | |
1038 | prompt "GPIO Polarity" | |
1039 | depends on PM_WAKEUP_BY_GPIO | |
1040 | default PM_WAKEUP_GPIO_POLAR_H | |
1041 | config PM_WAKEUP_GPIO_POLAR_H | |
1042 | bool "Active High" | |
1043 | config PM_WAKEUP_GPIO_POLAR_L | |
1044 | bool "Active Low" | |
1045 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1046 | bool "Falling EDGE" | |
1047 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1048 | bool "Rising EDGE" | |
1049 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1050 | bool "Both EDGE" | |
1051 | endchoice | |
1052 | ||
1efc80b5 MH |
1053 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1054 | depends on PM | |
1055 | ||
1efc80b5 MH |
1056 | config PM_BFIN_WAKE_PH6 |
1057 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1058 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1059 | default n |
1060 | help | |
1061 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1062 | ||
1efc80b5 MH |
1063 | config PM_BFIN_WAKE_GP |
1064 | bool "Allow Wake-Up from GPIOs" | |
1065 | depends on PM && BF54x | |
1066 | default n | |
1067 | help | |
1068 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
1394f032 BW |
1069 | endmenu |
1070 | ||
1394f032 BW |
1071 | menu "CPU Frequency scaling" |
1072 | ||
1073 | source "drivers/cpufreq/Kconfig" | |
1074 | ||
14b03204 MH |
1075 | config CPU_VOLTAGE |
1076 | bool "CPU Voltage scaling" | |
1077 | depends on EXPERIMENTAL | |
1078 | depends on CPU_FREQ | |
1079 | default n | |
1080 | help | |
1081 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1082 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
1083 | manuals. There is a theoretical risk that during VDDINT transitions | |
1084 | the PLL may unlock. | |
1085 | ||
1394f032 BW |
1086 | endmenu |
1087 | ||
1394f032 BW |
1088 | source "net/Kconfig" |
1089 | ||
1090 | source "drivers/Kconfig" | |
1091 | ||
1092 | source "fs/Kconfig" | |
1093 | ||
74ce8322 | 1094 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1095 | |
1096 | source "security/Kconfig" | |
1097 | ||
1098 | source "crypto/Kconfig" | |
1099 | ||
1100 | source "lib/Kconfig" |