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Commit | Line | Data |
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1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config FPU | |
bac7d89e | 12 | def_bool n |
1394f032 BW |
13 | |
14 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 15 | def_bool y |
1394f032 BW |
16 | |
17 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 18 | def_bool n |
1394f032 BW |
19 | |
20 | config BLACKFIN | |
bac7d89e | 21 | def_bool y |
ec7748b5 | 22 | select HAVE_IDE |
538067c8 MF |
23 | select HAVE_KERNEL_GZIP |
24 | select HAVE_KERNEL_BZIP2 | |
25 | select HAVE_KERNEL_LZMA | |
42d4b839 | 26 | select HAVE_OPROFILE |
a4f0b32c | 27 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 28 | |
70f12567 MF |
29 | config GENERIC_BUG |
30 | def_bool y | |
31 | depends on BUG | |
32 | ||
e3defffe | 33 | config ZONE_DMA |
bac7d89e | 34 | def_bool y |
e3defffe | 35 | |
1394f032 | 36 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 37 | def_bool y |
1394f032 BW |
38 | |
39 | config GENERIC_HWEIGHT | |
bac7d89e | 40 | def_bool y |
1394f032 BW |
41 | |
42 | config GENERIC_HARDIRQS | |
bac7d89e | 43 | def_bool y |
1394f032 BW |
44 | |
45 | config GENERIC_IRQ_PROBE | |
bac7d89e | 46 | def_bool y |
1394f032 | 47 | |
b2d1583f | 48 | config GENERIC_GPIO |
bac7d89e | 49 | def_bool y |
1394f032 BW |
50 | |
51 | config FORCE_MAX_ZONEORDER | |
52 | int | |
53 | default "14" | |
54 | ||
55 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 56 | def_bool y |
1394f032 | 57 | |
c7b412f4 MF |
58 | config STACKTRACE_SUPPORT |
59 | def_bool y | |
60 | ||
8f86001f MF |
61 | config TRACE_IRQFLAGS_SUPPORT |
62 | def_bool y | |
63 | ||
1394f032 | 64 | source "init/Kconfig" |
dc52ddc0 | 65 | |
1394f032 BW |
66 | source "kernel/Kconfig.preempt" |
67 | ||
dc52ddc0 MH |
68 | source "kernel/Kconfig.freezer" |
69 | ||
1394f032 BW |
70 | menu "Blackfin Processor Options" |
71 | ||
72 | comment "Processor and Board Settings" | |
73 | ||
74 | choice | |
75 | prompt "CPU" | |
76 | default BF533 | |
77 | ||
2f6f4bcd BW |
78 | config BF512 |
79 | bool "BF512" | |
80 | help | |
81 | BF512 Processor Support. | |
82 | ||
83 | config BF514 | |
84 | bool "BF514" | |
85 | help | |
86 | BF514 Processor Support. | |
87 | ||
88 | config BF516 | |
89 | bool "BF516" | |
90 | help | |
91 | BF516 Processor Support. | |
92 | ||
93 | config BF518 | |
94 | bool "BF518" | |
95 | help | |
96 | BF518 Processor Support. | |
97 | ||
59003145 MH |
98 | config BF522 |
99 | bool "BF522" | |
100 | help | |
101 | BF522 Processor Support. | |
102 | ||
1545a111 MF |
103 | config BF523 |
104 | bool "BF523" | |
105 | help | |
106 | BF523 Processor Support. | |
107 | ||
108 | config BF524 | |
109 | bool "BF524" | |
110 | help | |
111 | BF524 Processor Support. | |
112 | ||
59003145 MH |
113 | config BF525 |
114 | bool "BF525" | |
115 | help | |
116 | BF525 Processor Support. | |
117 | ||
1545a111 MF |
118 | config BF526 |
119 | bool "BF526" | |
120 | help | |
121 | BF526 Processor Support. | |
122 | ||
59003145 MH |
123 | config BF527 |
124 | bool "BF527" | |
125 | help | |
126 | BF527 Processor Support. | |
127 | ||
1394f032 BW |
128 | config BF531 |
129 | bool "BF531" | |
130 | help | |
131 | BF531 Processor Support. | |
132 | ||
133 | config BF532 | |
134 | bool "BF532" | |
135 | help | |
136 | BF532 Processor Support. | |
137 | ||
138 | config BF533 | |
139 | bool "BF533" | |
140 | help | |
141 | BF533 Processor Support. | |
142 | ||
143 | config BF534 | |
144 | bool "BF534" | |
145 | help | |
146 | BF534 Processor Support. | |
147 | ||
148 | config BF536 | |
149 | bool "BF536" | |
150 | help | |
151 | BF536 Processor Support. | |
152 | ||
153 | config BF537 | |
154 | bool "BF537" | |
155 | help | |
156 | BF537 Processor Support. | |
157 | ||
dc26aec2 MH |
158 | config BF538 |
159 | bool "BF538" | |
160 | help | |
161 | BF538 Processor Support. | |
162 | ||
163 | config BF539 | |
164 | bool "BF539" | |
165 | help | |
166 | BF539 Processor Support. | |
167 | ||
24a07a12 RH |
168 | config BF542 |
169 | bool "BF542" | |
170 | help | |
171 | BF542 Processor Support. | |
172 | ||
2f89c063 MF |
173 | config BF542M |
174 | bool "BF542m" | |
175 | help | |
176 | BF542 Processor Support. | |
177 | ||
24a07a12 RH |
178 | config BF544 |
179 | bool "BF544" | |
180 | help | |
181 | BF544 Processor Support. | |
182 | ||
2f89c063 MF |
183 | config BF544M |
184 | bool "BF544m" | |
185 | help | |
186 | BF544 Processor Support. | |
187 | ||
7c7fd170 MF |
188 | config BF547 |
189 | bool "BF547" | |
190 | help | |
191 | BF547 Processor Support. | |
192 | ||
2f89c063 MF |
193 | config BF547M |
194 | bool "BF547m" | |
195 | help | |
196 | BF547 Processor Support. | |
197 | ||
24a07a12 RH |
198 | config BF548 |
199 | bool "BF548" | |
200 | help | |
201 | BF548 Processor Support. | |
202 | ||
2f89c063 MF |
203 | config BF548M |
204 | bool "BF548m" | |
205 | help | |
206 | BF548 Processor Support. | |
207 | ||
24a07a12 RH |
208 | config BF549 |
209 | bool "BF549" | |
210 | help | |
211 | BF549 Processor Support. | |
212 | ||
2f89c063 MF |
213 | config BF549M |
214 | bool "BF549m" | |
215 | help | |
216 | BF549 Processor Support. | |
217 | ||
1394f032 BW |
218 | config BF561 |
219 | bool "BF561" | |
220 | help | |
cd88b4dc | 221 | BF561 Processor Support. |
1394f032 BW |
222 | |
223 | endchoice | |
224 | ||
46fa5eec GY |
225 | config SMP |
226 | depends on BF561 | |
9b9bfded | 227 | select GENERIC_TIME |
46fa5eec GY |
228 | bool "Symmetric multi-processing support" |
229 | ---help--- | |
230 | This enables support for systems with more than one CPU, | |
231 | like the dual core BF561. If you have a system with only one | |
232 | CPU, say N. If you have a system with more than one CPU, say Y. | |
233 | ||
234 | If you don't know what to do here, say N. | |
235 | ||
236 | config NR_CPUS | |
237 | int | |
238 | depends on SMP | |
239 | default 2 if BF561 | |
240 | ||
241 | config IRQ_PER_CPU | |
242 | bool | |
243 | depends on SMP | |
244 | default y | |
245 | ||
0c0497c2 MF |
246 | config BF_REV_MIN |
247 | int | |
2f89c063 | 248 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 249 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 250 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 251 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
252 | |
253 | config BF_REV_MAX | |
254 | int | |
2f89c063 MF |
255 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
256 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 257 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
258 | default 6 if (BF533 || BF532 || BF531) |
259 | ||
1394f032 BW |
260 | choice |
261 | prompt "Silicon Rev" | |
f8b55651 MF |
262 | default BF_REV_0_0 if (BF51x || BF52x) |
263 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 264 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
265 | |
266 | config BF_REV_0_0 | |
267 | bool "0.0" | |
2f89c063 | 268 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
269 | |
270 | config BF_REV_0_1 | |
d07f4380 | 271 | bool "0.1" |
2f89c063 | 272 | depends on (BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
273 | |
274 | config BF_REV_0_2 | |
275 | bool "0.2" | |
2f89c063 | 276 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
277 | |
278 | config BF_REV_0_3 | |
279 | bool "0.3" | |
2f89c063 | 280 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
281 | |
282 | config BF_REV_0_4 | |
283 | bool "0.4" | |
dc26aec2 | 284 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
285 | |
286 | config BF_REV_0_5 | |
287 | bool "0.5" | |
dc26aec2 | 288 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 289 | |
49f7253c MF |
290 | config BF_REV_0_6 |
291 | bool "0.6" | |
292 | depends on (BF533 || BF532 || BF531) | |
293 | ||
de3025f4 JZ |
294 | config BF_REV_ANY |
295 | bool "any" | |
296 | ||
297 | config BF_REV_NONE | |
298 | bool "none" | |
299 | ||
1394f032 BW |
300 | endchoice |
301 | ||
2f6f4bcd BW |
302 | config BF51x |
303 | bool | |
304 | depends on (BF512 || BF514 || BF516 || BF518) | |
305 | default y | |
306 | ||
59003145 MH |
307 | config BF52x |
308 | bool | |
1545a111 | 309 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
310 | default y |
311 | ||
24a07a12 RH |
312 | config BF53x |
313 | bool | |
314 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
315 | default y | |
316 | ||
2f89c063 MF |
317 | config BF54xM |
318 | bool | |
319 | depends on (BF542M || BF544M || BF547M || BF548M || BF549M) | |
320 | default y | |
321 | ||
24a07a12 RH |
322 | config BF54x |
323 | bool | |
2f89c063 | 324 | depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM) |
24a07a12 RH |
325 | default y |
326 | ||
1394f032 BW |
327 | config MEM_GENERIC_BOARD |
328 | bool | |
329 | depends on GENERIC_BOARD | |
330 | default y | |
331 | ||
332 | config MEM_MT48LC64M4A2FB_7E | |
333 | bool | |
334 | depends on (BFIN533_STAMP) | |
335 | default y | |
336 | ||
337 | config MEM_MT48LC16M16A2TG_75 | |
338 | bool | |
339 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 | 340 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
9db144fe | 341 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
1394f032 BW |
342 | default y |
343 | ||
344 | config MEM_MT48LC32M8A2_75 | |
345 | bool | |
dc26aec2 | 346 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
347 | default y |
348 | ||
349 | config MEM_MT48LC8M32B2B5_7 | |
350 | bool | |
351 | depends on (BFIN561_BLUETECHNIX_CM) | |
352 | default y | |
353 | ||
59003145 MH |
354 | config MEM_MT48LC32M16A2TG_75 |
355 | bool | |
8cc7117e | 356 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
59003145 MH |
357 | default y |
358 | ||
4934540d SZ |
359 | config MEM_MT48LC32M8A2_75 |
360 | bool | |
361 | depends on (BFIN518F_EZBRD) | |
362 | default y | |
363 | ||
2f6f4bcd | 364 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 365 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
366 | source "arch/blackfin/mach-bf533/Kconfig" |
367 | source "arch/blackfin/mach-bf561/Kconfig" | |
368 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 369 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 370 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
371 | |
372 | menu "Board customizations" | |
373 | ||
374 | config CMDLINE_BOOL | |
375 | bool "Default bootloader kernel arguments" | |
376 | ||
377 | config CMDLINE | |
378 | string "Initial kernel command string" | |
379 | depends on CMDLINE_BOOL | |
380 | default "console=ttyBF0,57600" | |
381 | help | |
382 | If you don't have a boot loader capable of passing a command line string | |
383 | to the kernel, you may specify one here. As a minimum, you should specify | |
384 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
385 | ||
5f004c20 MF |
386 | config BOOT_LOAD |
387 | hex "Kernel load address for booting" | |
388 | default "0x1000" | |
389 | range 0x1000 0x20000000 | |
390 | help | |
391 | This option allows you to set the load address of the kernel. | |
392 | This can be useful if you are on a board which has a small amount | |
393 | of memory or you wish to reserve some memory at the beginning of | |
394 | the address space. | |
395 | ||
396 | Note that you need to keep this value above 4k (0x1000) as this | |
397 | memory region is used to capture NULL pointer references as well | |
398 | as some core kernel functions. | |
399 | ||
8cc7117e MH |
400 | config ROM_BASE |
401 | hex "Kernel ROM Base" | |
86249911 | 402 | depends on ROMKERNEL |
8cc7117e MH |
403 | default "0x20040000" |
404 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
405 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
406 | help | |
407 | ||
f16295e7 | 408 | comment "Clock/PLL Setup" |
1394f032 BW |
409 | |
410 | config CLKIN_HZ | |
2fb6cb41 | 411 | int "Frequency of the crystal on the board in Hz" |
1394f032 BW |
412 | default "11059200" if BFIN533_STAMP |
413 | default "27000000" if BFIN533_EZKIT | |
2f6f4bcd | 414 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD) |
1394f032 BW |
415 | default "30000000" if BFIN561_EZKIT |
416 | default "24576000" if PNAV10 | |
5d1617b2 | 417 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
418 | help |
419 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
420 | Warning: This value should match the crystal on the board. Otherwise, |
421 | peripherals won't work properly. | |
1394f032 | 422 | |
f16295e7 RG |
423 | config BFIN_KERNEL_CLOCK |
424 | bool "Re-program Clocks while Kernel boots?" | |
425 | default n | |
426 | help | |
427 | This option decides if kernel clocks are re-programed from the | |
428 | bootloader settings. If the clocks are not set, the SDRAM settings | |
429 | are also not changed, and the Bootloader does 100% of the hardware | |
430 | configuration. | |
431 | ||
432 | config PLL_BYPASS | |
e4e9a7ad MF |
433 | bool "Bypass PLL" |
434 | depends on BFIN_KERNEL_CLOCK | |
435 | default n | |
f16295e7 RG |
436 | |
437 | config CLKIN_HALF | |
438 | bool "Half Clock In" | |
439 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
440 | default n | |
441 | help | |
442 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
443 | ||
444 | config VCO_MULT | |
445 | int "VCO Multiplier" | |
446 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
447 | range 1 64 | |
448 | default "22" if BFIN533_EZKIT | |
449 | default "45" if BFIN533_STAMP | |
dc26aec2 | 450 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 451 | default "22" if BFIN533_BLUETECHNIX_CM |
9db144fe | 452 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 453 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 454 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
455 | help |
456 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
457 | PLL Frequency = (Crystal Frequency) * (this setting) | |
458 | ||
459 | choice | |
460 | prompt "Core Clock Divider" | |
461 | depends on BFIN_KERNEL_CLOCK | |
462 | default CCLK_DIV_1 | |
463 | help | |
464 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
465 | Core Frequency = (PLL frequency) / (this setting) | |
466 | ||
467 | config CCLK_DIV_1 | |
468 | bool "1" | |
469 | ||
470 | config CCLK_DIV_2 | |
471 | bool "2" | |
472 | ||
473 | config CCLK_DIV_4 | |
474 | bool "4" | |
475 | ||
476 | config CCLK_DIV_8 | |
477 | bool "8" | |
478 | endchoice | |
479 | ||
480 | config SCLK_DIV | |
481 | int "System Clock Divider" | |
482 | depends on BFIN_KERNEL_CLOCK | |
483 | range 1 15 | |
5f004c20 | 484 | default 5 |
f16295e7 RG |
485 | help |
486 | This sets the frequency of the system clock (including SDRAM or DDR). | |
487 | This can be between 1 and 15 | |
488 | System Clock = (PLL frequency) / (this setting) | |
489 | ||
5f004c20 MF |
490 | choice |
491 | prompt "DDR SDRAM Chip Type" | |
492 | depends on BFIN_KERNEL_CLOCK | |
493 | depends on BF54x | |
494 | default MEM_MT46V32M16_5B | |
495 | ||
496 | config MEM_MT46V32M16_6T | |
497 | bool "MT46V32M16_6T" | |
498 | ||
499 | config MEM_MT46V32M16_5B | |
500 | bool "MT46V32M16_5B" | |
501 | endchoice | |
502 | ||
73feb5c0 MH |
503 | choice |
504 | prompt "DDR/SDRAM Timing" | |
505 | depends on BFIN_KERNEL_CLOCK | |
506 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
507 | help | |
508 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
509 | The calculated SDRAM timing parameters may not be 100% | |
510 | accurate - This option is therefore marked experimental. | |
511 | ||
512 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
513 | bool "Calculate Timings (EXPERIMENTAL)" | |
514 | depends on EXPERIMENTAL | |
515 | ||
516 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
517 | bool "Provide accurate Timings based on target SCLK" | |
518 | help | |
519 | Please consult the Blackfin Hardware Reference Manuals as well | |
520 | as the memory device datasheet. | |
521 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
522 | endchoice | |
523 | ||
524 | menu "Memory Init Control" | |
525 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
526 | ||
527 | config MEM_DDRCTL0 | |
528 | depends on BF54x | |
529 | hex "DDRCTL0" | |
530 | default 0x0 | |
531 | ||
532 | config MEM_DDRCTL1 | |
533 | depends on BF54x | |
534 | hex "DDRCTL1" | |
535 | default 0x0 | |
536 | ||
537 | config MEM_DDRCTL2 | |
538 | depends on BF54x | |
539 | hex "DDRCTL2" | |
540 | default 0x0 | |
541 | ||
542 | config MEM_EBIU_DDRQUE | |
543 | depends on BF54x | |
544 | hex "DDRQUE" | |
545 | default 0x0 | |
546 | ||
547 | config MEM_SDRRC | |
548 | depends on !BF54x | |
549 | hex "SDRRC" | |
550 | default 0x0 | |
551 | ||
552 | config MEM_SDGCTL | |
553 | depends on !BF54x | |
554 | hex "SDGCTL" | |
555 | default 0x0 | |
556 | endmenu | |
557 | ||
f16295e7 RG |
558 | # |
559 | # Max & Min Speeds for various Chips | |
560 | # | |
561 | config MAX_VCO_HZ | |
562 | int | |
2f6f4bcd BW |
563 | default 400000000 if BF512 |
564 | default 400000000 if BF514 | |
565 | default 400000000 if BF516 | |
566 | default 400000000 if BF518 | |
f16295e7 | 567 | default 600000000 if BF522 |
1545a111 MF |
568 | default 400000000 if BF523 |
569 | default 400000000 if BF524 | |
f16295e7 | 570 | default 600000000 if BF525 |
1545a111 | 571 | default 400000000 if BF526 |
f16295e7 RG |
572 | default 600000000 if BF527 |
573 | default 400000000 if BF531 | |
574 | default 400000000 if BF532 | |
575 | default 750000000 if BF533 | |
576 | default 500000000 if BF534 | |
577 | default 400000000 if BF536 | |
578 | default 600000000 if BF537 | |
f72eecb9 RG |
579 | default 533333333 if BF538 |
580 | default 533333333 if BF539 | |
f16295e7 | 581 | default 600000000 if BF542 |
f72eecb9 | 582 | default 533333333 if BF544 |
1545a111 MF |
583 | default 600000000 if BF547 |
584 | default 600000000 if BF548 | |
f72eecb9 | 585 | default 533333333 if BF549 |
f16295e7 RG |
586 | default 600000000 if BF561 |
587 | ||
588 | config MIN_VCO_HZ | |
589 | int | |
590 | default 50000000 | |
591 | ||
592 | config MAX_SCLK_HZ | |
593 | int | |
f72eecb9 | 594 | default 133333333 |
f16295e7 RG |
595 | |
596 | config MIN_SCLK_HZ | |
597 | int | |
598 | default 27000000 | |
599 | ||
600 | comment "Kernel Timer/Scheduler" | |
601 | ||
602 | source kernel/Kconfig.hz | |
603 | ||
8b5f79f9 VM |
604 | config GENERIC_TIME |
605 | bool "Generic time" | |
606 | default y | |
607 | ||
608 | config GENERIC_CLOCKEVENTS | |
609 | bool "Generic clock events" | |
610 | depends on GENERIC_TIME | |
611 | default y | |
612 | ||
1fa9be72 GY |
613 | choice |
614 | prompt "Kernel Tick Source" | |
615 | depends on GENERIC_CLOCKEVENTS | |
616 | default TICKSOURCE_CORETMR | |
617 | ||
618 | config TICKSOURCE_GPTMR0 | |
619 | bool "Gptimer0 (SCLK domain)" | |
620 | select BFIN_GPTIMERS | |
621 | depends on !IPIPE | |
622 | ||
623 | config TICKSOURCE_CORETMR | |
624 | bool "Core timer (CCLK domain)" | |
625 | ||
626 | endchoice | |
627 | ||
8b5f79f9 | 628 | config CYCLES_CLOCKSOURCE |
1fa9be72 | 629 | bool "Use 'CYCLES' as a clocksource" |
8b5f79f9 VM |
630 | depends on GENERIC_CLOCKEVENTS |
631 | depends on !BFIN_SCRATCH_REG_CYCLES | |
1fa9be72 | 632 | depends on !SMP |
8b5f79f9 VM |
633 | help |
634 | If you say Y here, you will enable support for using the 'cycles' | |
635 | registers as a clock source. Doing so means you will be unable to | |
636 | safely write to the 'cycles' register during runtime. You will | |
637 | still be able to read it (such as for performance monitoring), but | |
638 | writing the registers will most likely crash the kernel. | |
639 | ||
1fa9be72 GY |
640 | config GPTMR0_CLOCKSOURCE |
641 | bool "Use GPTimer0 as a clocksource (higher rating)" | |
642 | depends on GENERIC_CLOCKEVENTS | |
643 | depends on !TICKSOURCE_GPTMR0 | |
644 | ||
8b5f79f9 VM |
645 | source kernel/time/Kconfig |
646 | ||
5f004c20 | 647 | comment "Misc" |
971d5bc4 | 648 | |
f0b5d12f MF |
649 | choice |
650 | prompt "Blackfin Exception Scratch Register" | |
651 | default BFIN_SCRATCH_REG_RETN | |
652 | help | |
653 | Select the resource to reserve for the Exception handler: | |
654 | - RETN: Non-Maskable Interrupt (NMI) | |
655 | - RETE: Exception Return (JTAG/ICE) | |
656 | - CYCLES: Performance counter | |
657 | ||
658 | If you are unsure, please select "RETN". | |
659 | ||
660 | config BFIN_SCRATCH_REG_RETN | |
661 | bool "RETN" | |
662 | help | |
663 | Use the RETN register in the Blackfin exception handler | |
664 | as a stack scratch register. This means you cannot | |
665 | safely use NMI on the Blackfin while running Linux, but | |
666 | you can debug the system with a JTAG ICE and use the | |
667 | CYCLES performance registers. | |
668 | ||
669 | If you are unsure, please select "RETN". | |
670 | ||
671 | config BFIN_SCRATCH_REG_RETE | |
672 | bool "RETE" | |
673 | help | |
674 | Use the RETE register in the Blackfin exception handler | |
675 | as a stack scratch register. This means you cannot | |
676 | safely use a JTAG ICE while debugging a Blackfin board, | |
677 | but you can safely use the CYCLES performance registers | |
678 | and the NMI. | |
679 | ||
680 | If you are unsure, please select "RETN". | |
681 | ||
682 | config BFIN_SCRATCH_REG_CYCLES | |
683 | bool "CYCLES" | |
684 | help | |
685 | Use the CYCLES register in the Blackfin exception handler | |
686 | as a stack scratch register. This means you cannot | |
687 | safely use the CYCLES performance registers on a Blackfin | |
688 | board at anytime, but you can debug the system with a JTAG | |
689 | ICE and use the NMI. | |
690 | ||
691 | If you are unsure, please select "RETN". | |
692 | ||
693 | endchoice | |
694 | ||
1394f032 BW |
695 | endmenu |
696 | ||
697 | ||
698 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 699 | depends on !SMP |
1394f032 | 700 | |
1394f032 BW |
701 | comment "Memory Optimizations" |
702 | ||
703 | config I_ENTRY_L1 | |
704 | bool "Locate interrupt entry code in L1 Memory" | |
705 | default y | |
706 | help | |
01dd2fbf ML |
707 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
708 | into L1 instruction memory. (less latency) | |
1394f032 BW |
709 | |
710 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 711 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
712 | default y |
713 | help | |
01dd2fbf | 714 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 715 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 716 | (less latency) |
1394f032 BW |
717 | |
718 | config DO_IRQ_L1 | |
719 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
720 | default y | |
721 | help | |
01dd2fbf ML |
722 | If enabled, the frequently called do_irq dispatcher function is linked |
723 | into L1 instruction memory. (less latency) | |
1394f032 BW |
724 | |
725 | config CORE_TIMER_IRQ_L1 | |
726 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
727 | default y | |
728 | help | |
01dd2fbf ML |
729 | If enabled, the frequently called timer_interrupt() function is linked |
730 | into L1 instruction memory. (less latency) | |
1394f032 BW |
731 | |
732 | config IDLE_L1 | |
733 | bool "Locate frequently idle function in L1 Memory" | |
734 | default y | |
735 | help | |
01dd2fbf ML |
736 | If enabled, the frequently called idle function is linked |
737 | into L1 instruction memory. (less latency) | |
1394f032 BW |
738 | |
739 | config SCHEDULE_L1 | |
740 | bool "Locate kernel schedule function in L1 Memory" | |
741 | default y | |
742 | help | |
01dd2fbf ML |
743 | If enabled, the frequently called kernel schedule is linked |
744 | into L1 instruction memory. (less latency) | |
1394f032 BW |
745 | |
746 | config ARITHMETIC_OPS_L1 | |
747 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
748 | default y | |
749 | help | |
01dd2fbf ML |
750 | If enabled, arithmetic functions are linked |
751 | into L1 instruction memory. (less latency) | |
1394f032 BW |
752 | |
753 | config ACCESS_OK_L1 | |
754 | bool "Locate access_ok function in L1 Memory" | |
755 | default y | |
756 | help | |
01dd2fbf ML |
757 | If enabled, the access_ok function is linked |
758 | into L1 instruction memory. (less latency) | |
1394f032 BW |
759 | |
760 | config MEMSET_L1 | |
761 | bool "Locate memset function in L1 Memory" | |
762 | default y | |
763 | help | |
01dd2fbf ML |
764 | If enabled, the memset function is linked |
765 | into L1 instruction memory. (less latency) | |
1394f032 BW |
766 | |
767 | config MEMCPY_L1 | |
768 | bool "Locate memcpy function in L1 Memory" | |
769 | default y | |
770 | help | |
01dd2fbf ML |
771 | If enabled, the memcpy function is linked |
772 | into L1 instruction memory. (less latency) | |
1394f032 BW |
773 | |
774 | config SYS_BFIN_SPINLOCK_L1 | |
775 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
776 | default y | |
777 | help | |
01dd2fbf ML |
778 | If enabled, sys_bfin_spinlock function is linked |
779 | into L1 instruction memory. (less latency) | |
1394f032 BW |
780 | |
781 | config IP_CHECKSUM_L1 | |
782 | bool "Locate IP Checksum function in L1 Memory" | |
783 | default n | |
784 | help | |
01dd2fbf ML |
785 | If enabled, the IP Checksum function is linked |
786 | into L1 instruction memory. (less latency) | |
1394f032 BW |
787 | |
788 | config CACHELINE_ALIGNED_L1 | |
789 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
790 | default y if !BF54x |
791 | default n if BF54x | |
1394f032 BW |
792 | depends on !BF531 |
793 | help | |
692105b8 | 794 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 795 | into L1 data memory. (less latency) |
1394f032 BW |
796 | |
797 | config SYSCALL_TAB_L1 | |
798 | bool "Locate Syscall Table L1 Data Memory" | |
799 | default n | |
800 | depends on !BF531 | |
801 | help | |
01dd2fbf ML |
802 | If enabled, the Syscall LUT is linked |
803 | into L1 data memory. (less latency) | |
1394f032 BW |
804 | |
805 | config CPLB_SWITCH_TAB_L1 | |
806 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
807 | default n | |
808 | depends on !BF531 | |
809 | help | |
01dd2fbf ML |
810 | If enabled, the CPLB Switch Tables are linked |
811 | into L1 data memory. (less latency) | |
1394f032 | 812 | |
ca87b7ad GY |
813 | config APP_STACK_L1 |
814 | bool "Support locating application stack in L1 Scratch Memory" | |
815 | default y | |
816 | help | |
817 | If enabled the application stack can be located in L1 | |
818 | scratch memory (less latency). | |
819 | ||
820 | Currently only works with FLAT binaries. | |
821 | ||
6ad2b84c MF |
822 | config EXCEPTION_L1_SCRATCH |
823 | bool "Locate exception stack in L1 Scratch Memory" | |
824 | default n | |
f82e0a0c | 825 | depends on !APP_STACK_L1 |
6ad2b84c MF |
826 | help |
827 | Whenever an exception occurs, use the L1 Scratch memory for | |
828 | stack storage. You cannot place the stacks of FLAT binaries | |
829 | in L1 when using this option. | |
830 | ||
831 | If you don't use L1 Scratch, then you should say Y here. | |
832 | ||
251383c7 RG |
833 | comment "Speed Optimizations" |
834 | config BFIN_INS_LOWOVERHEAD | |
835 | bool "ins[bwl] low overhead, higher interrupt latency" | |
836 | default y | |
837 | help | |
838 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
839 | they can be interrupted at any time (even after they have been issued | |
840 | on to the external bus), and re-issued after the interrupt occurs. | |
841 | For memory - this is not a big deal, since memory does not change if | |
842 | it sees a read. | |
843 | ||
844 | If a FIFO is sitting on the end of the read, it will see two reads, | |
845 | when the core only sees one since the FIFO receives both the read | |
846 | which is cancelled (and not delivered to the core) and the one which | |
847 | is re-issued (which is delivered to the core). | |
848 | ||
849 | To solve this, interrupts are turned off before reads occur to | |
850 | I/O space. This option controls which the overhead/latency of | |
851 | controlling interrupts during this time | |
852 | "n" turns interrupts off every read | |
853 | (higher overhead, but lower interrupt latency) | |
854 | "y" turns interrupts off every loop | |
855 | (low overhead, but longer interrupt latency) | |
856 | ||
857 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
858 | interrupt latency issues, it is safe and OK to turn this off. | |
859 | ||
1394f032 BW |
860 | endmenu |
861 | ||
1394f032 BW |
862 | choice |
863 | prompt "Kernel executes from" | |
864 | help | |
865 | Choose the memory type that the kernel will be running in. | |
866 | ||
867 | config RAMKERNEL | |
868 | bool "RAM" | |
869 | help | |
870 | The kernel will be resident in RAM when running. | |
871 | ||
872 | config ROMKERNEL | |
873 | bool "ROM" | |
874 | help | |
875 | The kernel will be resident in FLASH/ROM when running. | |
876 | ||
877 | endchoice | |
878 | ||
879 | source "mm/Kconfig" | |
880 | ||
780431e3 MF |
881 | config BFIN_GPTIMERS |
882 | tristate "Enable Blackfin General Purpose Timers API" | |
883 | default n | |
884 | help | |
885 | Enable support for the General Purpose Timers API. If you | |
886 | are unsure, say N. | |
887 | ||
888 | To compile this driver as a module, choose M here: the module | |
889 | will be called gptimers.ko. | |
890 | ||
1394f032 | 891 | choice |
d292b000 | 892 | prompt "Uncached DMA region" |
1394f032 | 893 | default DMA_UNCACHED_1M |
86ad7932 CC |
894 | config DMA_UNCACHED_4M |
895 | bool "Enable 4M DMA region" | |
1394f032 BW |
896 | config DMA_UNCACHED_2M |
897 | bool "Enable 2M DMA region" | |
898 | config DMA_UNCACHED_1M | |
899 | bool "Enable 1M DMA region" | |
900 | config DMA_UNCACHED_NONE | |
901 | bool "Disable DMA region" | |
902 | endchoice | |
903 | ||
904 | ||
905 | comment "Cache Support" | |
3bebca2d | 906 | config BFIN_ICACHE |
1394f032 | 907 | bool "Enable ICACHE" |
3bebca2d | 908 | config BFIN_DCACHE |
1394f032 | 909 | bool "Enable DCACHE" |
3bebca2d | 910 | config BFIN_DCACHE_BANKA |
1394f032 | 911 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 912 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 913 | default n |
3bebca2d RG |
914 | config BFIN_ICACHE_LOCK |
915 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
916 | |
917 | choice | |
5ba76675 | 918 | prompt "External memory cache policy" |
3bebca2d | 919 | depends on BFIN_DCACHE |
46fa5eec GY |
920 | default BFIN_WB if !SMP |
921 | default BFIN_WT if SMP | |
3bebca2d | 922 | config BFIN_WB |
1394f032 | 923 | bool "Write back" |
46fa5eec | 924 | depends on !SMP |
1394f032 BW |
925 | help |
926 | Write Back Policy: | |
927 | Cached data will be written back to SDRAM only when needed. | |
928 | This can give a nice increase in performance, but beware of | |
929 | broken drivers that do not properly invalidate/flush their | |
930 | cache. | |
931 | ||
932 | Write Through Policy: | |
933 | Cached data will always be written back to SDRAM when the | |
934 | cache is updated. This is a completely safe setting, but | |
935 | performance is worse than Write Back. | |
936 | ||
937 | If you are unsure of the options and you want to be safe, | |
938 | then go with Write Through. | |
939 | ||
3bebca2d | 940 | config BFIN_WT |
1394f032 BW |
941 | bool "Write through" |
942 | help | |
943 | Write Back Policy: | |
944 | Cached data will be written back to SDRAM only when needed. | |
945 | This can give a nice increase in performance, but beware of | |
946 | broken drivers that do not properly invalidate/flush their | |
947 | cache. | |
948 | ||
949 | Write Through Policy: | |
950 | Cached data will always be written back to SDRAM when the | |
951 | cache is updated. This is a completely safe setting, but | |
952 | performance is worse than Write Back. | |
953 | ||
954 | If you are unsure of the options and you want to be safe, | |
955 | then go with Write Through. | |
956 | ||
957 | endchoice | |
958 | ||
5ba76675 GY |
959 | choice |
960 | prompt "L2 SRAM cache policy" | |
961 | depends on (BF54x || BF561) | |
962 | default BFIN_L2_WT | |
963 | config BFIN_L2_WB | |
964 | bool "Write back" | |
965 | depends on !SMP | |
966 | ||
967 | config BFIN_L2_WT | |
968 | bool "Write through" | |
969 | depends on !SMP | |
970 | ||
971 | config BFIN_L2_NOT_CACHED | |
972 | bool "Not cached" | |
973 | ||
974 | endchoice | |
f099f39a | 975 | |
b97b8a99 BS |
976 | config MPU |
977 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
978 | default n | |
979 | help | |
980 | Use the processor's MPU to protect applications from accessing | |
981 | memory they do not own. This comes at a performance penalty | |
982 | and is recommended only for debugging. | |
983 | ||
692105b8 | 984 | comment "Asynchronous Memory Configuration" |
1394f032 | 985 | |
ddf416b2 | 986 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
987 | config C_AMCKEN |
988 | bool "Enable CLKOUT" | |
989 | default y | |
990 | ||
991 | config C_CDPRIO | |
992 | bool "DMA has priority over core for ext. accesses" | |
993 | default n | |
994 | ||
995 | config C_B0PEN | |
996 | depends on BF561 | |
997 | bool "Bank 0 16 bit packing enable" | |
998 | default y | |
999 | ||
1000 | config C_B1PEN | |
1001 | depends on BF561 | |
1002 | bool "Bank 1 16 bit packing enable" | |
1003 | default y | |
1004 | ||
1005 | config C_B2PEN | |
1006 | depends on BF561 | |
1007 | bool "Bank 2 16 bit packing enable" | |
1008 | default y | |
1009 | ||
1010 | config C_B3PEN | |
1011 | depends on BF561 | |
1012 | bool "Bank 3 16 bit packing enable" | |
1013 | default n | |
1014 | ||
1015 | choice | |
692105b8 | 1016 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1017 | default C_AMBEN_ALL |
1018 | ||
1019 | config C_AMBEN | |
1020 | bool "Disable All Banks" | |
1021 | ||
1022 | config C_AMBEN_B0 | |
1023 | bool "Enable Bank 0" | |
1024 | ||
1025 | config C_AMBEN_B0_B1 | |
1026 | bool "Enable Bank 0 & 1" | |
1027 | ||
1028 | config C_AMBEN_B0_B1_B2 | |
1029 | bool "Enable Bank 0 & 1 & 2" | |
1030 | ||
1031 | config C_AMBEN_ALL | |
1032 | bool "Enable All Banks" | |
1033 | endchoice | |
1034 | endmenu | |
1035 | ||
1036 | menu "EBIU_AMBCTL Control" | |
1037 | config BANK_0 | |
c8342f87 | 1038 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1039 | default 0x7BB0 |
c8342f87 MF |
1040 | help |
1041 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1042 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1043 | |
1044 | config BANK_1 | |
c8342f87 | 1045 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1046 | default 0x7BB0 |
197fba56 | 1047 | default 0x5558 if BF54x |
c8342f87 MF |
1048 | help |
1049 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1050 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1051 | |
1052 | config BANK_2 | |
c8342f87 | 1053 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1054 | default 0x7BB0 |
c8342f87 MF |
1055 | help |
1056 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1057 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1058 | |
1059 | config BANK_3 | |
c8342f87 | 1060 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1061 | default 0x99B3 |
c8342f87 MF |
1062 | help |
1063 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1064 | used to control the Asynchronous Memory Bank 3 settings. | |
1065 | ||
1394f032 BW |
1066 | endmenu |
1067 | ||
e40540b3 SZ |
1068 | config EBIU_MBSCTLVAL |
1069 | hex "EBIU Bank Select Control Register" | |
1070 | depends on BF54x | |
1071 | default 0 | |
1072 | ||
1073 | config EBIU_MODEVAL | |
1074 | hex "Flash Memory Mode Control Register" | |
1075 | depends on BF54x | |
1076 | default 1 | |
1077 | ||
1078 | config EBIU_FCTLVAL | |
1079 | hex "Flash Memory Bank Control Register" | |
1080 | depends on BF54x | |
1081 | default 6 | |
1394f032 BW |
1082 | endmenu |
1083 | ||
1084 | ############################################################################# | |
1085 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1086 | ||
1087 | config PCI | |
1088 | bool "PCI support" | |
a95ca3b2 | 1089 | depends on BROKEN |
1394f032 BW |
1090 | help |
1091 | Support for PCI bus. | |
1092 | ||
1093 | source "drivers/pci/Kconfig" | |
1094 | ||
1095 | config HOTPLUG | |
1096 | bool "Support for hot-pluggable device" | |
1097 | help | |
1098 | Say Y here if you want to plug devices into your computer while | |
1099 | the system is running, and be able to use them quickly. In many | |
1100 | cases, the devices can likewise be unplugged at any time too. | |
1101 | ||
1102 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
1103 | size devices such as network cards, modems or hard drives which are | |
1104 | plugged into slots found on all modern laptop computers. Another | |
1105 | example, used on modern desktops as well as laptops, is USB. | |
1106 | ||
a81792f6 JB |
1107 | Enable HOTPLUG and build a modular kernel. Get agent software |
1108 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
1109 | Then your kernel will automatically call out to a user mode "policy |
1110 | agent" (/sbin/hotplug) to load modules and set up software needed | |
1111 | to use devices as you hotplug them. | |
1112 | ||
1113 | source "drivers/pcmcia/Kconfig" | |
1114 | ||
1115 | source "drivers/pci/hotplug/Kconfig" | |
1116 | ||
1117 | endmenu | |
1118 | ||
1119 | menu "Executable file formats" | |
1120 | ||
1121 | source "fs/Kconfig.binfmt" | |
1122 | ||
1123 | endmenu | |
1124 | ||
1125 | menu "Power management options" | |
1126 | source "kernel/power/Kconfig" | |
1127 | ||
f4cb5700 JB |
1128 | config ARCH_SUSPEND_POSSIBLE |
1129 | def_bool y | |
1130 | depends on !SMP | |
1131 | ||
1394f032 | 1132 | choice |
1efc80b5 | 1133 | prompt "Standby Power Saving Mode" |
1394f032 | 1134 | depends on PM |
cfefe3c6 MH |
1135 | default PM_BFIN_SLEEP_DEEPER |
1136 | config PM_BFIN_SLEEP_DEEPER | |
1137 | bool "Sleep Deeper" | |
1138 | help | |
1139 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1140 | power dissipation by disabling the clock to the processor core (CCLK). | |
1141 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1142 | to 0.85 V to provide the greatest power savings, while preserving the | |
1143 | processor state. | |
1144 | The PLL and system clock (SCLK) continue to operate at a very low | |
1145 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1146 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1147 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1148 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1149 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1150 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1151 | ||
1efc80b5 MH |
1152 | If unsure, select "Sleep Deeper". |
1153 | ||
cfefe3c6 MH |
1154 | config PM_BFIN_SLEEP |
1155 | bool "Sleep" | |
1156 | help | |
1157 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1158 | dissipation by disabling the clock to the processor core (CCLK). | |
1159 | The PLL and system clock (SCLK), however, continue to operate in | |
1160 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1161 | up the processor. When in the sleep mode, system DMA access to L1 |
1162 | memory is not supported. | |
1163 | ||
1164 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1165 | endchoice |
1394f032 | 1166 | |
1394f032 | 1167 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1168 | bool "Allow Wakeup from Standby by GPIO" |
ff19fed4 | 1169 | depends on PM && !BF54x |
1394f032 BW |
1170 | |
1171 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1172 | int "GPIO number" |
1394f032 BW |
1173 | range 0 47 |
1174 | depends on PM_WAKEUP_BY_GPIO | |
d1a3336e | 1175 | default 2 |
1394f032 BW |
1176 | |
1177 | choice | |
1178 | prompt "GPIO Polarity" | |
1179 | depends on PM_WAKEUP_BY_GPIO | |
1180 | default PM_WAKEUP_GPIO_POLAR_H | |
1181 | config PM_WAKEUP_GPIO_POLAR_H | |
1182 | bool "Active High" | |
1183 | config PM_WAKEUP_GPIO_POLAR_L | |
1184 | bool "Active Low" | |
1185 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1186 | bool "Falling EDGE" | |
1187 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1188 | bool "Rising EDGE" | |
1189 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1190 | bool "Both EDGE" | |
1191 | endchoice | |
1192 | ||
1efc80b5 MH |
1193 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1194 | depends on PM | |
1195 | ||
1efc80b5 MH |
1196 | config PM_BFIN_WAKE_PH6 |
1197 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1198 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1199 | default n |
1200 | help | |
1201 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1202 | ||
1efc80b5 MH |
1203 | config PM_BFIN_WAKE_GP |
1204 | bool "Allow Wake-Up from GPIOs" | |
1205 | depends on PM && BF54x | |
1206 | default n | |
1207 | help | |
1208 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1209 | (all processors, except ADSP-BF549). This option sets |
1210 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1211 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1212 | On ADSP-BF549 this option enables the the same functionality on the | |
1213 | /MRXON pin also PH7. | |
1214 | ||
1394f032 BW |
1215 | endmenu |
1216 | ||
1394f032 BW |
1217 | menu "CPU Frequency scaling" |
1218 | ||
1219 | source "drivers/cpufreq/Kconfig" | |
1220 | ||
5ad2ca5f MH |
1221 | config BFIN_CPU_FREQ |
1222 | bool | |
1223 | depends on CPU_FREQ | |
1224 | select CPU_FREQ_TABLE | |
1225 | default y | |
1226 | ||
14b03204 MH |
1227 | config CPU_VOLTAGE |
1228 | bool "CPU Voltage scaling" | |
73feb5c0 | 1229 | depends on EXPERIMENTAL |
14b03204 MH |
1230 | depends on CPU_FREQ |
1231 | default n | |
1232 | help | |
1233 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1234 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1235 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1236 | the PLL may unlock. |
1237 | ||
1394f032 BW |
1238 | endmenu |
1239 | ||
1394f032 BW |
1240 | source "net/Kconfig" |
1241 | ||
1242 | source "drivers/Kconfig" | |
1243 | ||
1244 | source "fs/Kconfig" | |
1245 | ||
74ce8322 | 1246 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1247 | |
1248 | source "security/Kconfig" | |
1249 | ||
1250 | source "crypto/Kconfig" | |
1251 | ||
1252 | source "lib/Kconfig" |