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sched/headers: Prepare for new header dependencies before moving code to <linux/sched...
[mirror_ubuntu-artful-kernel.git] / arch / blackfin / kernel / trace.c
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2a12c463
RG		 1/* provide some functions which dump the trace buffer, in a nice way for people
2 * to read it, and understand what is going on
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later
7 */
8
9#include <linux/kernel.h>
10#include <linux/hardirq.h>
11#include <linux/thread_info.h>
12#include <linux/mm.h>
2214f707 13#include <linux/oom.h>
3f07c014 14#include <linux/sched/signal.h>
b17b0153 15#include <linux/sched/debug.h>
2a12c463
RG		 16#include <linux/uaccess.h>
17#include <linux/module.h>
18#include <linux/kallsyms.h>
19#include <linux/err.h>
20#include <linux/fs.h>
df9ee292 21#include <linux/irq.h>
2a12c463
RG		 22#include <asm/dma.h>
23#include <asm/trace.h>
24#include <asm/fixed_code.h>
25#include <asm/traps.h>
d60805ad 26#include <asm/irq_handler.h>
3bed8d67 27#include <asm/pda.h>
2a12c463 28
2a12c463
RG		 29void decode_address(char *buf, unsigned long address)
30{
2a12c463
RG		 31 struct task_struct *p;
32 struct mm_struct *mm;
af1be5a5 33 unsigned long offset;
2a12c463
RG		 34 struct rb_node *n;
35
36#ifdef CONFIG_KALLSYMS
37 unsigned long symsize;
38 const char *symname;
39 char *modname;
40 char *delim = ":";
41 char namebuf[128];
42#endif
43
44 buf += sprintf(buf, "<0x%08lx> ", address);
45
46#ifdef CONFIG_KALLSYMS
47 /* look up the address and see if we are in kernel space */
48 symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
49
50 if (symname) {
51 /* yeah! kernel space! */
52 if (!modname)
53 modname = delim = "";
54 sprintf(buf, "{ %s%s%s%s + 0x%lx }",
55 delim, modname, delim, symname,
56 (unsigned long)offset);
57 return;
58 }
59#endif
60
61 if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
62 /* Problem in fixed code section? */
63 strcat(buf, "/* Maybe fixed code section */");
64 return;
65
66 } else if (address < CONFIG_BOOT_LOAD) {
67 /* Problem somewhere before the kernel start address */
68 strcat(buf, "/* Maybe null pointer? */");
69 return;
70
71 } else if (address >= COREMMR_BASE) {
72 strcat(buf, "/* core mmrs */");
73 return;
74
75 } else if (address >= SYSMMR_BASE) {
76 strcat(buf, "/* system mmrs */");
77 return;
78
79 } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
80 strcat(buf, "/* on-chip L1 ROM */");
81 return;
9a95e2f1
RG		 82
83 } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
84 strcat(buf, "/* on-chip scratchpad */");
85 return;
86
87 } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
88 strcat(buf, "/* unconnected memory */");
89 return;
90
91 } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
92 strcat(buf, "/* reserved memory */");
93 return;
94
95 } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
96 strcat(buf, "/* on-chip Data Bank A */");
97 return;
98
99 } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
100 strcat(buf, "/* on-chip Data Bank B */");
101 return;
2a12c463
RG		 102 }
103
104 /*
105 * Don't walk any of the vmas if we are oopsing, it has been known
106 * to cause problems - corrupt vmas (kernel crashes) cause double faults
107 */
108 if (oops_in_progress) {
109 strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
110 return;
111 }
112
113 /* looks like we're off in user-land, so let's walk all the
114 * mappings of all our processes and see if we can't be a whee
115 * bit more specific
116 */
af1be5a5 117 read_lock(&tasklist_lock);
2a12c463 118 for_each_process(p) {
2214f707 119 struct task_struct *t;
2a12c463 120
2214f707
AV		 121 t = find_lock_task_mm(p);
122 if (!t)
2a12c463 123 continue;
2214f707
AV		 124
125 mm = t->mm;
126 if (!down_read_trylock(&mm->mmap_sem))
127 goto __continue;
2a12c463
RG		 128
129 for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
130 struct vm_area_struct *vma;
131
132 vma = rb_entry(n, struct vm_area_struct, vm_rb);
133
134 if (address >= vma->vm_start && address < vma->vm_end) {
135 char _tmpbuf[256];
2214f707 136 char *name = t->comm;
2a12c463
RG		 137 struct file *file = vma->vm_file;
138
139 if (file) {
9bf39ab2 140 char *d_name = file_path(file, _tmpbuf,
2a12c463
RG		 141 sizeof(_tmpbuf));
142 if (!IS_ERR(d_name))
143 name = d_name;
144 }
145
146 /* FLAT does not have its text aligned to the start of
147 * the map while FDPIC ELF does ...
148 */
149
150 /* before we can check flat/fdpic, we need to
151 * make sure current is valid
152 */
153 if ((unsigned long)current >= FIXED_CODE_START &&
154 !((unsigned long)current & 0x3)) {
155 if (current->mm &&
156 (address > current->mm->start_code) &&
157 (address < current->mm->end_code))
158 offset = address - current->mm->start_code;
159 else
160 offset = (address - vma->vm_start) +
161 (vma->vm_pgoff << PAGE_SHIFT);
162
163 sprintf(buf, "[ %s + 0x%lx ]", name, offset);
164 } else
165 sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
166 name, vma->vm_start, vma->vm_end);
167
168 up_read(&mm->mmap_sem);
2214f707 169 task_unlock(t);
2a12c463
RG		 170
171 if (buf[0] == '\0')
172 sprintf(buf, "[ %s ] dynamic memory", name);
173
174 goto done;
175 }
176 }
177
178 up_read(&mm->mmap_sem);
2214f707
AV		 179__continue:
180 task_unlock(t);
2a12c463
RG		 181 }
182
183 /*
184 * we were unable to find this address anywhere,
185 * or some MMs were skipped because they were in use.
186 */
187 sprintf(buf, "/* kernel dynamic memory */");
188
189done:
af1be5a5 190 read_unlock(&tasklist_lock);
2a12c463
RG		 191}
192
193#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
194
195/*
196 * Similar to get_user, do some address checking, then dereference
197 * Return true on success, false on bad address
198 */
9a95e2f1 199bool get_mem16(unsigned short *val, unsigned short *address)
2a12c463
RG		 200{
201 unsigned long addr = (unsigned long)address;
202
203 /* Check for odd addresses */
204 if (addr & 0x1)
205 return false;
206
2a12c463
RG		 207 switch (bfin_mem_access_type(addr, 2)) {
208 case BFIN_MEM_ACCESS_CORE:
209 case BFIN_MEM_ACCESS_CORE_ONLY:
210 *val = *address;
211 return true;
212 case BFIN_MEM_ACCESS_DMA:
213 dma_memcpy(val, address, 2);
214 return true;
215 case BFIN_MEM_ACCESS_ITEST:
216 isram_memcpy(val, address, 2);
217 return true;
218 default: /* invalid access */
219 return false;
220 }
221}
222
9a95e2f1
RG		 223bool get_instruction(unsigned int *val, unsigned short *address)
224{
225 unsigned long addr = (unsigned long)address;
226 unsigned short opcode0, opcode1;
227
228 /* Check for odd addresses */
229 if (addr & 0x1)
230 return false;
231
232 /* MMR region will never have instructions */
233 if (addr >= SYSMMR_BASE)
234 return false;
235
236 /* Scratchpad will never have instructions */
237 if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
238 return false;
239
240 /* Data banks will never have instructions */
241 if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
242 return false;
243
244 if (!get_mem16(&opcode0, address))
245 return false;
246
247 /* was this a 32-bit instruction? If so, get the next 16 bits */
248 if ((opcode0 & 0xc000) == 0xc000) {
249 if (!get_mem16(&opcode1, address + 1))
250 return false;
251 *val = (opcode0 << 16) + opcode1;
252 } else
253 *val = opcode0;
254
255 return true;
256}
257
258#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
2a12c463
RG		 259/*
260 * decode the instruction if we are printing out the trace, as it
261 * makes things easier to follow, without running it through objdump
9a95e2f1
RG		 262 * Decode the change of flow, and the common load/store instructions
263 * which are the main cause for faults, and discontinuities in the trace
264 * buffer.
2a12c463 265 */
9a95e2f1
RG		 266
267#define ProgCtrl_opcode 0x0000
268#define ProgCtrl_poprnd_bits 0
269#define ProgCtrl_poprnd_mask 0xf
270#define ProgCtrl_prgfunc_bits 4
271#define ProgCtrl_prgfunc_mask 0xf
272#define ProgCtrl_code_bits 8
273#define ProgCtrl_code_mask 0xff
274
275static void decode_ProgCtrl_0(unsigned int opcode)
276{
277 int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
278 int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
279
280 if (prgfunc == 0 && poprnd == 0)
281 pr_cont("NOP");
282 else if (prgfunc == 1 && poprnd == 0)
283 pr_cont("RTS");
284 else if (prgfunc == 1 && poprnd == 1)
285 pr_cont("RTI");
286 else if (prgfunc == 1 && poprnd == 2)
287 pr_cont("RTX");
288 else if (prgfunc == 1 && poprnd == 3)
289 pr_cont("RTN");
290 else if (prgfunc == 1 && poprnd == 4)
291 pr_cont("RTE");
292 else if (prgfunc == 2 && poprnd == 0)
293 pr_cont("IDLE");
294 else if (prgfunc == 2 && poprnd == 3)
295 pr_cont("CSYNC");
296 else if (prgfunc == 2 && poprnd == 4)
297 pr_cont("SSYNC");
298 else if (prgfunc == 2 && poprnd == 5)
299 pr_cont("EMUEXCPT");
300 else if (prgfunc == 3)
301 pr_cont("CLI R%i", poprnd);
302 else if (prgfunc == 4)
303 pr_cont("STI R%i", poprnd);
304 else if (prgfunc == 5)
305 pr_cont("JUMP (P%i)", poprnd);
306 else if (prgfunc == 6)
307 pr_cont("CALL (P%i)", poprnd);
308 else if (prgfunc == 7)
309 pr_cont("CALL (PC + P%i)", poprnd);
310 else if (prgfunc == 8)
311 pr_cont("JUMP (PC + P%i", poprnd);
312 else if (prgfunc == 9)
313 pr_cont("RAISE %i", poprnd);
314 else if (prgfunc == 10)
315 pr_cont("EXCPT %i", poprnd);
316 else
317 pr_cont("0x%04x", opcode);
318
319}
320
321#define BRCC_opcode 0x1000
322#define BRCC_offset_bits 0
323#define BRCC_offset_mask 0x3ff
324#define BRCC_B_bits 10
325#define BRCC_B_mask 0x1
326#define BRCC_T_bits 11
327#define BRCC_T_mask 0x1
328#define BRCC_code_bits 12
329#define BRCC_code_mask 0xf
330
331static void decode_BRCC_0(unsigned int opcode)
2a12c463 332{
9a95e2f1
RG		 333 int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
334 int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
335
336 pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
337}
338
339#define CALLa_opcode 0xe2000000
340#define CALLa_addr_bits 0
341#define CALLa_addr_mask 0xffffff
342#define CALLa_S_bits 24
343#define CALLa_S_mask 0x1
344#define CALLa_code_bits 25
345#define CALLa_code_mask 0x7f
346
347static void decode_CALLa_0(unsigned int opcode)
348{
349 int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
350
351 if (S)
352 pr_cont("CALL pcrel");
353 else
354 pr_cont("JUMP.L");
355}
356
357#define LoopSetup_opcode 0xe0800000
358#define LoopSetup_eoffset_bits 0
359#define LoopSetup_eoffset_mask 0x3ff
360#define LoopSetup_dontcare_bits 10
361#define LoopSetup_dontcare_mask 0x3
362#define LoopSetup_reg_bits 12
363#define LoopSetup_reg_mask 0xf
364#define LoopSetup_soffset_bits 16
365#define LoopSetup_soffset_mask 0xf
366#define LoopSetup_c_bits 20
367#define LoopSetup_c_mask 0x1
368#define LoopSetup_rop_bits 21
369#define LoopSetup_rop_mask 0x3
370#define LoopSetup_code_bits 23
371#define LoopSetup_code_mask 0x1ff
372
373static void decode_LoopSetup_0(unsigned int opcode)
374{
375 int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
376 int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
377 int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
378
379 pr_cont("LSETUP <> LC%i", c);
380 if ((rop & 1) == 1)
381 pr_cont("= P%i", reg);
382 if ((rop & 2) == 2)
383 pr_cont(" >> 0x1");
384}
385
386#define DspLDST_opcode 0x9c00
387#define DspLDST_reg_bits 0
388#define DspLDST_reg_mask 0x7
389#define DspLDST_i_bits 3
390#define DspLDST_i_mask 0x3
391#define DspLDST_m_bits 5
392#define DspLDST_m_mask 0x3
393#define DspLDST_aop_bits 7
394#define DspLDST_aop_mask 0x3
395#define DspLDST_W_bits 9
396#define DspLDST_W_mask 0x1
397#define DspLDST_code_bits 10
398#define DspLDST_code_mask 0x3f
399
400static void decode_dspLDST_0(unsigned int opcode)
401{
402 int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
403 int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
404 int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
405 int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
406 int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
407
408 if (W == 0) {
409 pr_cont("R%i", reg);
410 switch (m) {
411 case 0:
412 pr_cont(" = ");
413 break;
414 case 1:
415 pr_cont(".L = ");
416 break;
417 case 2:
418 pr_cont(".W = ");
419 break;
420 }
421 }
422
423 pr_cont("[ I%i", i);
424
425 switch (aop) {
426 case 0:
427 pr_cont("++ ]");
428 break;
429 case 1:
430 pr_cont("-- ]");
431 break;
432 }
433
434 if (W == 1) {
435 pr_cont(" = R%i", reg);
436 switch (m) {
437 case 1:
438 pr_cont(".L = ");
439 break;
440 case 2:
441 pr_cont(".W = ");
442 break;
443 }
444 }
445}
446
447#define LDST_opcode 0x9000
448#define LDST_reg_bits 0
449#define LDST_reg_mask 0x7
450#define LDST_ptr_bits 3
451#define LDST_ptr_mask 0x7
452#define LDST_Z_bits 6
453#define LDST_Z_mask 0x1
454#define LDST_aop_bits 7
455#define LDST_aop_mask 0x3
456#define LDST_W_bits 9
457#define LDST_W_mask 0x1
458#define LDST_sz_bits 10
459#define LDST_sz_mask 0x3
460#define LDST_code_bits 12
461#define LDST_code_mask 0xf
462
463static void decode_LDST_0(unsigned int opcode)
464{
465 int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
466 int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
467 int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
468 int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
469 int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
470 int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
471
472 if (W == 0)
473 pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
474
475 switch (sz) {
476 case 1:
477 pr_cont("W");
478 break;
479 case 2:
480 pr_cont("B");
481 break;
482 }
483
484 pr_cont("[P%i", ptr);
485
486 switch (aop) {
487 case 0:
488 pr_cont("++");
489 break;
490 case 1:
491 pr_cont("--");
492 break;
493 }
494 pr_cont("]");
495
496 if (W == 1)
497 pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
498
499 if (sz) {
500 if (Z)
501 pr_cont(" (X)");
502 else
503 pr_cont(" (Z)");
504 }
505}
506
507#define LDSTii_opcode 0xa000
508#define LDSTii_reg_bit 0
509#define LDSTii_reg_mask 0x7
510#define LDSTii_ptr_bit 3
511#define LDSTii_ptr_mask 0x7
512#define LDSTii_offset_bit 6
513#define LDSTii_offset_mask 0xf
514#define LDSTii_op_bit 10
515#define LDSTii_op_mask 0x3
516#define LDSTii_W_bit 12
517#define LDSTii_W_mask 0x1
518#define LDSTii_code_bit 13
519#define LDSTii_code_mask 0x7
520
521static void decode_LDSTii_0(unsigned int opcode)
522{
523 int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
524 int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
525 int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
526 int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
527 int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
528
529 if (W == 0) {
530 pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
531 op == 1 || op == 2 ? "" : "W", ptr, offset);
532 if (op == 2)
533 pr_cont("(Z)");
534 if (op == 3)
535 pr_cont("(X)");
536 } else {
537 pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
538 offset, op == 3 ? "P" : "R", reg);
539 }
540}
541
542#define LDSTidxI_opcode 0xe4000000
543#define LDSTidxI_offset_bits 0
544#define LDSTidxI_offset_mask 0xffff
545#define LDSTidxI_reg_bits 16
546#define LDSTidxI_reg_mask 0x7
547#define LDSTidxI_ptr_bits 19
548#define LDSTidxI_ptr_mask 0x7
549#define LDSTidxI_sz_bits 22
550#define LDSTidxI_sz_mask 0x3
551#define LDSTidxI_Z_bits 24
552#define LDSTidxI_Z_mask 0x1
553#define LDSTidxI_W_bits 25
554#define LDSTidxI_W_mask 0x1
555#define LDSTidxI_code_bits 26
556#define LDSTidxI_code_mask 0x3f
557
558static void decode_LDSTidxI_0(unsigned int opcode)
559{
560 int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
561 int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
562 int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
563 int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
564 int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
565 int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
566
567 if (W == 0)
568 pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
569
570 if (sz == 1)
571 pr_cont("W");
572 if (sz == 2)
573 pr_cont("B");
574
575 pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
576 (offset & 0x1f) << 2);
577
578 if (W == 0 && sz != 0) {
579 if (Z)
580 pr_cont("(X)");
2a12c463 581 else
9a95e2f1 582 pr_cont("(Z)");
2a12c463
RG		 583 }
584
9a95e2f1
RG		 585 if (W == 1)
586 pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
587
588}
589
590static void decode_opcode(unsigned int opcode)
591{
592#ifdef CONFIG_BUG
593 if (opcode == BFIN_BUG_OPCODE)
594 pr_cont("BUG");
595 else
596#endif
597 if ((opcode & 0xffffff00) == ProgCtrl_opcode)
598 decode_ProgCtrl_0(opcode);
599 else if ((opcode & 0xfffff000) == BRCC_opcode)
600 decode_BRCC_0(opcode);
601 else if ((opcode & 0xfffff000) == 0x2000)
602 pr_cont("JUMP.S");
603 else if ((opcode & 0xfe000000) == CALLa_opcode)
604 decode_CALLa_0(opcode);
605 else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
606 decode_LoopSetup_0(opcode);
607 else if ((opcode & 0xfffffc00) == DspLDST_opcode)
608 decode_dspLDST_0(opcode);
609 else if ((opcode & 0xfffff000) == LDST_opcode)
610 decode_LDST_0(opcode);
611 else if ((opcode & 0xffffe000) == LDSTii_opcode)
612 decode_LDSTii_0(opcode);
613 else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
614 decode_LDSTidxI_0(opcode);
615 else if (opcode & 0xffff0000)
616 pr_cont("0x%08x", opcode);
617 else
618 pr_cont("0x%04x", opcode);
619}
620
621#define BIT_MULTI_INS 0x08000000
622static void decode_instruction(unsigned short *address)
623{
624 unsigned int opcode;
625
626 if (!get_instruction(&opcode, address))
627 return;
628
629 decode_opcode(opcode);
630
631 /* If things are a 32-bit instruction, it has the possibility of being
632 * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
633 * This test collidates with the unlink instruction, so disallow that
634 */
635 if ((opcode & 0xc0000000) == 0xc0000000 &&
636 (opcode & BIT_MULTI_INS) &&
637 (opcode & 0xe8000000) != 0xe8000000) {
638 pr_cont(" || ");
639 if (!get_instruction(&opcode, address + 2))
640 return;
641 decode_opcode(opcode);
642 pr_cont(" || ");
643 if (!get_instruction(&opcode, address + 3))
644 return;
645 decode_opcode(opcode);
646 }
2a12c463
RG		 647}
648#endif
649
650void dump_bfin_trace_buffer(void)
651{
2a12c463 652#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
d60805ad 653 int tflags, i = 0, fault = 0;
2a12c463
RG		 654 char buf[150];
655 unsigned short *addr;
d60805ad 656 unsigned int cpu = raw_smp_processor_id();
2a12c463
RG		 657#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
658 int j, index;
659#endif
660
661 trace_buffer_save(tflags);
662
d28cff4b 663 pr_notice("Hardware Trace:\n");
2a12c463
RG		 664
665#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
d28cff4b 666 pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
2a12c463
RG		 667#endif
668
669 if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
670 for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
d60805ad
RG		 671 addr = (unsigned short *)bfin_read_TBUF();
672 decode_address(buf, (unsigned long)addr);
d28cff4b 673 pr_notice("%4i Target : %s\n", i, buf);
d60805ad
RG		 674 /* Normally, the faulting instruction doesn't go into
675 * the trace buffer, (since it doesn't commit), so
676 * we print out the fault address here
677 */
a80d5f44
RG		 678 if (!fault && addr == ((unsigned short *)evt_ivhw)) {
679 addr = (unsigned short *)bfin_read_TBUF();
680 decode_address(buf, (unsigned long)addr);
681 pr_notice(" FAULT : %s ", buf);
682 decode_instruction(addr);
683 pr_cont("\n");
684 fault = 1;
685 continue;
686 }
d60805ad
RG		 687 if (!fault && addr == (unsigned short *)trap &&
688 (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) {
689 decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
690 pr_notice(" FAULT : %s ", buf);
691 decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr);
692 pr_cont("\n");
693 fault = 1;
694 }
2a12c463
RG		 695 addr = (unsigned short *)bfin_read_TBUF();
696 decode_address(buf, (unsigned long)addr);
d28cff4b 697 pr_notice(" Source : %s ", buf);
2a12c463 698 decode_instruction(addr);
d28cff4b 699 pr_cont("\n");
2a12c463
RG		 700 }
701 }
702
703#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
704 if (trace_buff_offset)
705 index = trace_buff_offset / 4;
706 else
707 index = EXPAND_LEN;
708
709 j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
710 while (j) {
711 decode_address(buf, software_trace_buff[index]);
d28cff4b 712 pr_notice("%4i Target : %s\n", i, buf);
2a12c463
RG		 713 index -= 1;
714 if (index < 0)
715 index = EXPAND_LEN;
716 decode_address(buf, software_trace_buff[index]);
d28cff4b 717 pr_notice(" Source : %s ", buf);
2a12c463 718 decode_instruction((unsigned short *)software_trace_buff[index]);
d28cff4b 719 pr_cont("\n");
2a12c463
RG		 720 index -= 1;
721 if (index < 0)
722 index = EXPAND_LEN;
723 j--;
724 i++;
725 }
726#endif
727
728 trace_buffer_restore(tflags);
729#endif
2a12c463
RG		 730}
731EXPORT_SYMBOL(dump_bfin_trace_buffer);
732
733void dump_bfin_process(struct pt_regs *fp)
734{
2a12c463
RG		 735 /* We should be able to look at fp->ipend, but we don't push it on the
736 * stack all the time, so do this until we fix that */
737 unsigned int context = bfin_read_IPEND();
738
739 if (oops_in_progress)
d28cff4b 740 pr_emerg("Kernel OOPS in progress\n");
2a12c463
RG		 741
742 if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
d28cff4b 743 pr_notice("HW Error context\n");
2a12c463 744 else if (context & 0x0020)
d28cff4b 745 pr_notice("Deferred Exception context\n");
2a12c463 746 else if (context & 0x3FC0)
d28cff4b 747 pr_notice("Interrupt context\n");
2a12c463 748 else if (context & 0x4000)
d28cff4b 749 pr_notice("Deferred Interrupt context\n");
2a12c463 750 else if (context & 0x8000)
d28cff4b 751 pr_notice("Kernel process context\n");
2a12c463
RG		 752
753 /* Because we are crashing, and pointers could be bad, we check things
754 * pretty closely before we use them
755 */
756 if ((unsigned long)current >= FIXED_CODE_START &&
757 !((unsigned long)current & 0x3) && current->pid) {
d28cff4b 758 pr_notice("CURRENT PROCESS:\n");
2a12c463 759 if (current->comm >= (char *)FIXED_CODE_START)
d28cff4b 760 pr_notice("COMM=%s PID=%d",
2a12c463
RG		 761 current->comm, current->pid);
762 else
d28cff4b 763 pr_notice("COMM= invalid");
2a12c463 764
d28cff4b
RG		 765 pr_cont(" CPU=%d\n", current_thread_info()->cpu);
766 if (!((unsigned long)current->mm & 0x3) &&
767 (unsigned long)current->mm >= FIXED_CODE_START) {
768 pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
2a12c463
RG		 769 (void *)current->mm->start_code,
770 (void *)current->mm->end_code,
771 (void *)current->mm->start_data,
d28cff4b
RG		 772 (void *)current->mm->end_data);
773 pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
2a12c463
RG		 774 (void *)current->mm->end_data,
775 (void *)current->mm->brk,
776 (void *)current->mm->start_stack);
d28cff4b
RG		 777 } else
778 pr_notice("invalid mm\n");
2a12c463 779 } else
d28cff4b 780 pr_notice("No Valid process in current context\n");
2a12c463
RG		 781}
782
783void dump_bfin_mem(struct pt_regs *fp)
784{
2a12c463
RG		 785 unsigned short *addr, *erraddr, val = 0, err = 0;
786 char sti = 0, buf[6];
787
788 erraddr = (void *)fp->pc;
789
d28cff4b 790 pr_notice("return address: [0x%p]; contents of:", erraddr);
2a12c463
RG		 791
792 for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
793 addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
794 addr++) {
795 if (!((unsigned long)addr & 0xF))
d28cff4b 796 pr_notice("0x%p: ", addr);
2a12c463 797
9a95e2f1 798 if (!get_mem16(&val, addr)) {
2a12c463
RG		 799 val = 0;
800 sprintf(buf, "????");
801 } else
802 sprintf(buf, "%04x", val);
803
804 if (addr == erraddr) {
d28cff4b 805 pr_cont("[%s]", buf);
2a12c463
RG		 806 err = val;
807 } else
d28cff4b 808 pr_cont(" %s ", buf);
2a12c463
RG		 809
810 /* Do any previous instructions turn on interrupts? */
811 if (addr <= erraddr && /* in the past */
812 ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
813 val == 0x017b)) /* [SP++] = RETI */
814 sti = 1;
815 }
816
d28cff4b 817 pr_cont("\n");
2a12c463
RG		 818
819 /* Hardware error interrupts can be deferred */
820 if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
821 oops_in_progress)){
d28cff4b 822 pr_notice("Looks like this was a deferred error - sorry\n");
2a12c463 823#ifndef CONFIG_DEBUG_HWERR
d28cff4b
RG		 824 pr_notice("The remaining message may be meaningless\n");
825 pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
2a12c463
RG		 826#else
827 /* If we are handling only one peripheral interrupt
828 * and current mm and pid are valid, and the last error
829 * was in that user space process's text area
830 * print it out - because that is where the problem exists
831 */
832 if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
833 (current->pid && current->mm)) {
834 /* And the last RETI points to the current userspace context */
835 if ((fp + 1)->pc >= current->mm->start_code &&
836 (fp + 1)->pc <= current->mm->end_code) {
d28cff4b
RG		 837 pr_notice("It might be better to look around here :\n");
838 pr_notice("-------------------------------------------\n");
2a12c463 839 show_regs(fp + 1);
d28cff4b 840 pr_notice("-------------------------------------------\n");
2a12c463
RG		 841 }
842 }
843#endif
844 }
2a12c463
RG		 845}
846
847void show_regs(struct pt_regs *fp)
848{
2a12c463
RG		 849 char buf[150];
850 struct irqaction *action;
851 unsigned int i;
852 unsigned long flags = 0;
853 unsigned int cpu = raw_smp_processor_id();
854 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
855
d28cff4b 856 pr_notice("\n");
a43cb95d
TH		 857 show_regs_print_info(KERN_NOTICE);
858
2a12c463 859 if (CPUID != bfin_cpuid())
d28cff4b 860 pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
2a12c463
RG		 861 "but running on:0x%04x (Rev %d)\n",
862 CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
863
d28cff4b 864 pr_notice("ADSP-%s-0.%d",
2a12c463
RG		 865 CPU, bfin_compiled_revid());
866
867 if (bfin_compiled_revid() != bfin_revid())
d28cff4b 868 pr_cont("(Detected 0.%d)", bfin_revid());
2a12c463 869
d28cff4b 870 pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
2a12c463
RG		 871 get_cclk()/1000000, get_sclk()/1000000,
872#ifdef CONFIG_MPU
873 "mpu on"
874#else
875 "mpu off"
876#endif
877 );
878
d28cff4b 879 pr_notice("%s", linux_banner);
2a12c463 880
d28cff4b
RG		 881 pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
882 pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
2a12c463
RG		 883 (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
884 if (fp->ipend & EVT_IRPTEN)
d28cff4b 885 pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
2a12c463
RG		 886 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
887 EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
d28cff4b 888 pr_notice(" Peripheral interrupts masked off\n");
2a12c463 889 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
d28cff4b 890 pr_notice(" Kernel interrupts masked off\n");
2a12c463 891 if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
d28cff4b 892 pr_notice(" HWERRCAUSE: 0x%lx\n",
2a12c463
RG		 893 (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
894#ifdef EBIU_ERRMST
895 /* If the error was from the EBIU, print it out */
896 if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
d28cff4b 897 pr_notice(" EBIU Error Reason : 0x%04x\n",
2a12c463 898 bfin_read_EBIU_ERRMST());
d28cff4b 899 pr_notice(" EBIU Error Address : 0x%08x\n",
2a12c463
RG		 900 bfin_read_EBIU_ERRADD());
901 }
902#endif
903 }
d28cff4b 904 pr_notice(" EXCAUSE : 0x%lx\n",
2a12c463
RG		 905 fp->seqstat & SEQSTAT_EXCAUSE);
906 for (i = 2; i <= 15 ; i++) {
907 if (fp->ipend & (1 << i)) {
908 if (i != 4) {
909 decode_address(buf, bfin_read32(EVT0 + 4*i));
d28cff4b 910 pr_notice(" physical IVG%i asserted : %s\n", i, buf);
2a12c463 911 } else
d28cff4b 912 pr_notice(" interrupts disabled\n");
2a12c463
RG		 913 }
914 }
915
916 /* if no interrupts are going off, don't print this out */
917 if (fp->ipend & ~0x3F) {
918 for (i = 0; i < (NR_IRQS - 1); i++) {
28a283aa 919 struct irq_desc *desc = irq_to_desc(i);
2a12c463 920 if (!in_atomic)
28a283aa 921 raw_spin_lock_irqsave(&desc->lock, flags);
2a12c463 922
28a283aa 923 action = desc->action;
2a12c463
RG		 924 if (!action)
925 goto unlock;
926
927 decode_address(buf, (unsigned int)action->handler);
d28cff4b 928 pr_notice(" logical irq %3d mapped : %s", i, buf);
2a12c463
RG		 929 for (action = action->next; action; action = action->next) {
930 decode_address(buf, (unsigned int)action->handler);
d28cff4b 931 pr_cont(", %s", buf);
2a12c463 932 }
d28cff4b 933 pr_cont("\n");
2a12c463
RG		 934unlock:
935 if (!in_atomic)
28a283aa 936 raw_spin_unlock_irqrestore(&desc->lock, flags);
2a12c463
RG		 937 }
938 }
939
940 decode_address(buf, fp->rete);
d28cff4b 941 pr_notice(" RETE: %s\n", buf);
2a12c463 942 decode_address(buf, fp->retn);
d28cff4b 943 pr_notice(" RETN: %s\n", buf);
2a12c463 944 decode_address(buf, fp->retx);
d28cff4b 945 pr_notice(" RETX: %s\n", buf);
2a12c463 946 decode_address(buf, fp->rets);
d28cff4b 947 pr_notice(" RETS: %s\n", buf);
2a12c463 948 decode_address(buf, fp->pc);
d28cff4b 949 pr_notice(" PC : %s\n", buf);
2a12c463
RG		 950
951 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
952 (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
953 decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
d28cff4b 954 pr_notice("DCPLB_FAULT_ADDR: %s\n", buf);
2a12c463 955 decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
d28cff4b 956 pr_notice("ICPLB_FAULT_ADDR: %s\n", buf);
2a12c463
RG		 957 }
958
d28cff4b
RG		 959 pr_notice("PROCESSOR STATE:\n");
960 pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
2a12c463 961 fp->r0, fp->r1, fp->r2, fp->r3);
d28cff4b 962 pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
2a12c463 963 fp->r4, fp->r5, fp->r6, fp->r7);
d28cff4b 964 pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
2a12c463 965 fp->p0, fp->p1, fp->p2, fp->p3);
d28cff4b 966 pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
2a12c463 967 fp->p4, fp->p5, fp->fp, (long)fp);
d28cff4b 968 pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
2a12c463 969 fp->lb0, fp->lt0, fp->lc0);
d28cff4b 970 pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
2a12c463 971 fp->lb1, fp->lt1, fp->lc1);
d28cff4b 972 pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
2a12c463 973 fp->b0, fp->l0, fp->m0, fp->i0);
d28cff4b 974 pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
2a12c463 975 fp->b1, fp->l1, fp->m1, fp->i1);
d28cff4b 976 pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
2a12c463 977 fp->b2, fp->l2, fp->m2, fp->i2);
d28cff4b 978 pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
2a12c463 979 fp->b3, fp->l3, fp->m3, fp->i3);
d28cff4b 980 pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
2a12c463
RG		 981 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
982
d28cff4b 983 pr_notice("USP : %08lx ASTAT: %08lx\n",
2a12c463
RG		 984 rdusp(), fp->astat);
985
d28cff4b 986 pr_notice("\n");
2a12c463 987}
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