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Blackfin arch: put quotes around error to silence a ton of warnings from gcc-4.3
[mirror_ubuntu-artful-kernel.git] / arch / blackfin / mach-common / ints-priority.c
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1394f032 1/*
cfefe3c6 2 * File: arch/blackfin/mach-common/ints-priority.c
1394f032
BW		 3 * Based on:
4 * Author:
5 *
6 * Created: ?
d2d50aa9 7 * Description: Set up the interrupt priorities
1394f032
BW		 8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
cfefe3c6 16 * Copyright 2004-2008 Analog Devices Inc.
1394f032
BW		 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48#ifdef BF537_FAMILY
49# define BF537_GENERIC_ERROR_INT_DEMUX
50#else
51# undef BF537_GENERIC_ERROR_INT_DEMUX
52#endif
53
54/*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
a99bbccd
MF		 61/* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67unsigned long irq_flags = 0x1f;
fe8015ce 68EXPORT_SYMBOL(irq_flags);
1394f032
BW		 69
70/* The number of spurious interrupts */
71atomic_t num_spurious;
72
cfefe3c6
MH		 73#ifdef CONFIG_PM
74unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
4a88d0ce 75unsigned vr_wakeup;
cfefe3c6
MH		 76#endif
77
1394f032 78struct ivgx {
464abc5d 79 /* irq number for request_irq, available in mach-bf5xx/irq.h */
24a07a12 80 unsigned int irqno;
1394f032 81 /* corresponding bit in the SIC_ISR register */
24a07a12 82 unsigned int isrflag;
1394f032
BW		 83} ivg_table[NR_PERI_INTS];
84
85struct ivg_slice {
86 /* position of first irq in ivg_table for given ivg */
87 struct ivgx *ifirst;
88 struct ivgx *istop;
89} ivg7_13[IVG13 - IVG7 + 1];
90
1394f032
BW		 91
92/*
93 * Search SIC_IAR and fill tables with the irqvalues
94 * and their positions in the SIC_ISR register.
95 */
96static void __init search_IAR(void)
97{
98 unsigned ivg, irq_pos = 0;
99 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
100 int irqn;
101
34e0fc89 102 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
1394f032
BW		 103
104 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
105 int iar_shift = (irqn & 7) * 4;
2c4f829b 106 if (ivg == (0xf &
dc26aec2 107#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) || defined(CONFIG_BF539)
34e0fc89 108 bfin_read32((unsigned long *)SIC_IAR0 +
dc26aec2
MH		 109 ((irqn % 32) >> 3) + ((irqn / 32) *
110 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
59003145
MH		 111#else
112 bfin_read32((unsigned long *)SIC_IAR0 +
dc26aec2 113 (irqn >> 3)) >> iar_shift)) {
59003145 114#endif
1394f032 115 ivg_table[irq_pos].irqno = IVG7 + irqn;
24a07a12 116 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
1394f032
BW		 117 ivg7_13[ivg].istop++;
118 irq_pos++;
119 }
120 }
121 }
122}
123
124/*
464abc5d 125 * This is for core internal IRQs
1394f032
BW		 126 */
127
464abc5d 128static void bfin_ack_noop(unsigned int irq)
1394f032
BW		 129{
130 /* Dummy function. */
131}
132
133static void bfin_core_mask_irq(unsigned int irq)
134{
135 irq_flags &= ~(1 << irq);
136 if (!irqs_disabled())
137 local_irq_enable();
138}
139
140static void bfin_core_unmask_irq(unsigned int irq)
141{
142 irq_flags |= 1 << irq;
143 /*
144 * If interrupts are enabled, IMASK must contain the same value
145 * as irq_flags. Make sure that invariant holds. If interrupts
146 * are currently disabled we need not do anything; one of the
147 * callers will take care of setting IMASK to the proper value
148 * when reenabling interrupts.
149 * local_irq_enable just does "STI irq_flags", so it's exactly
150 * what we need.
151 */
152 if (!irqs_disabled())
153 local_irq_enable();
154 return;
155}
156
157static void bfin_internal_mask_irq(unsigned int irq)
158{
59003145 159#ifdef CONFIG_BF53x
1394f032 160 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
464abc5d 161 ~(1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 162#else
163 unsigned mask_bank, mask_bit;
464abc5d
MH		 164 mask_bank = SIC_SYSIRQ(irq) / 32;
165 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 166 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
167 ~(1 << mask_bit));
24a07a12 168#endif
1394f032
BW		 169 SSYNC();
170}
171
172static void bfin_internal_unmask_irq(unsigned int irq)
173{
59003145 174#ifdef CONFIG_BF53x
1394f032 175 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
464abc5d 176 (1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 177#else
178 unsigned mask_bank, mask_bit;
464abc5d
MH		 179 mask_bank = SIC_SYSIRQ(irq) / 32;
180 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 181 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
182 (1 << mask_bit));
24a07a12 183#endif
1394f032
BW		 184 SSYNC();
185}
186
cfefe3c6
MH		 187#ifdef CONFIG_PM
188int bfin_internal_set_wake(unsigned int irq, unsigned int state)
189{
4a88d0ce 190 unsigned bank, bit, wakeup = 0;
cfefe3c6 191 unsigned long flags;
464abc5d
MH		 192 bank = SIC_SYSIRQ(irq) / 32;
193 bit = SIC_SYSIRQ(irq) % 32;
cfefe3c6 194
4a88d0ce
MH		 195 switch (irq) {
196#ifdef IRQ_RTC
197 case IRQ_RTC:
198 wakeup |= WAKE;
199 break;
200#endif
201#ifdef IRQ_CAN0_RX
202 case IRQ_CAN0_RX:
203 wakeup |= CANWE;
204 break;
205#endif
206#ifdef IRQ_CAN1_RX
207 case IRQ_CAN1_RX:
208 wakeup |= CANWE;
209 break;
210#endif
211#ifdef IRQ_USB_INT0
212 case IRQ_USB_INT0:
213 wakeup |= USBWE;
214 break;
215#endif
216#ifdef IRQ_KEY
217 case IRQ_KEY:
218 wakeup |= KPADWE;
219 break;
220#endif
d310fb4b 221#ifdef CONFIG_BF54x
4a88d0ce
MH		 222 case IRQ_CNT:
223 wakeup |= ROTWE;
224 break;
225#endif
226 default:
227 break;
228 }
229
cfefe3c6
MH		 230 local_irq_save(flags);
231
4a88d0ce 232 if (state) {
cfefe3c6 233 bfin_sic_iwr[bank] |= (1 << bit);
4a88d0ce
MH		 234 vr_wakeup |= wakeup;
235
236 } else {
cfefe3c6 237 bfin_sic_iwr[bank] &= ~(1 << bit);
4a88d0ce
MH		 238 vr_wakeup &= ~wakeup;
239 }
cfefe3c6
MH		 240
241 local_irq_restore(flags);
242
243 return 0;
244}
245#endif
246
1394f032 247static struct irq_chip bfin_core_irqchip = {
763e63c6 248 .name = "CORE",
464abc5d 249 .ack = bfin_ack_noop,
1394f032
BW		 250 .mask = bfin_core_mask_irq,
251 .unmask = bfin_core_unmask_irq,
252};
253
254static struct irq_chip bfin_internal_irqchip = {
763e63c6 255 .name = "INTN",
464abc5d 256 .ack = bfin_ack_noop,
1394f032
BW		 257 .mask = bfin_internal_mask_irq,
258 .unmask = bfin_internal_unmask_irq,
ce3b7bb6
MH		 259 .mask_ack = bfin_internal_mask_irq,
260 .disable = bfin_internal_mask_irq,
261 .enable = bfin_internal_unmask_irq,
cfefe3c6
MH		 262#ifdef CONFIG_PM
263 .set_wake = bfin_internal_set_wake,
264#endif
1394f032
BW		 265};
266
267#ifdef BF537_GENERIC_ERROR_INT_DEMUX
268static int error_int_mask;
269
1394f032
BW		 270static void bfin_generic_error_mask_irq(unsigned int irq)
271{
272 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
273
464abc5d
MH		 274 if (!error_int_mask)
275 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 276}
277
278static void bfin_generic_error_unmask_irq(unsigned int irq)
279{
464abc5d 280 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 281 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
282}
283
284static struct irq_chip bfin_generic_error_irqchip = {
763e63c6 285 .name = "ERROR",
464abc5d
MH		 286 .ack = bfin_ack_noop,
287 .mask_ack = bfin_generic_error_mask_irq,
1394f032
BW		 288 .mask = bfin_generic_error_mask_irq,
289 .unmask = bfin_generic_error_unmask_irq,
290};
291
292static void bfin_demux_error_irq(unsigned int int_err_irq,
2c4f829b 293 struct irq_desc *inta_desc)
1394f032
BW		 294{
295 int irq = 0;
296
297 SSYNC();
298
299#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
300 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
301 irq = IRQ_MAC_ERROR;
302 else
303#endif
304 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
305 irq = IRQ_SPORT0_ERROR;
306 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
307 irq = IRQ_SPORT1_ERROR;
308 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
309 irq = IRQ_PPI_ERROR;
310 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
311 irq = IRQ_CAN_ERROR;
312 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
313 irq = IRQ_SPI_ERROR;
314 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
315 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
316 irq = IRQ_UART0_ERROR;
317 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
318 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
319 irq = IRQ_UART1_ERROR;
320
321 if (irq) {
322 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
323 struct irq_desc *desc = irq_desc + irq;
324 desc->handle_irq(irq, desc);
325 } else {
326
327 switch (irq) {
328 case IRQ_PPI_ERROR:
329 bfin_write_PPI_STATUS(PPI_ERR_MASK);
330 break;
331#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
332 case IRQ_MAC_ERROR:
333 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
334 break;
335#endif
336 case IRQ_SPORT0_ERROR:
337 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
338 break;
339
340 case IRQ_SPORT1_ERROR:
341 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
342 break;
343
344 case IRQ_CAN_ERROR:
345 bfin_write_CAN_GIS(CAN_ERR_MASK);
346 break;
347
348 case IRQ_SPI_ERROR:
349 bfin_write_SPI_STAT(SPI_ERR_MASK);
350 break;
351
352 default:
353 break;
354 }
355
356 pr_debug("IRQ %d:"
34e0fc89
MH		 357 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
358 irq);
1394f032
BW		 359 }
360 } else
361 printk(KERN_ERR
362 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
363 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
b85d858b 364 __func__, __FILE__, __LINE__);
1394f032 365
1394f032
BW		 366}
367#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
368
bfd15117
GY		 369static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
370{
371 struct irq_desc *desc = irq_desc + irq;
372 /* May not call generic set_irq_handler() due to spinlock
373 recursion. */
374 desc->handle_irq = handle;
375}
376
a055b2b4 377#if !defined(CONFIG_BF54x)
1394f032
BW		 378
379static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
380static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
381
affee2b2 382extern void bfin_gpio_irq_prepare(unsigned gpio);
6fce6a8d 383
1394f032
BW		 384static void bfin_gpio_ack_irq(unsigned int irq)
385{
386 u16 gpionr = irq - IRQ_PF0;
387
388 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
389 set_gpio_data(gpionr, 0);
390 SSYNC();
391 }
392}
393
394static void bfin_gpio_mask_ack_irq(unsigned int irq)
395{
396 u16 gpionr = irq - IRQ_PF0;
397
398 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
399 set_gpio_data(gpionr, 0);
400 SSYNC();
401 }
402
403 set_gpio_maska(gpionr, 0);
404 SSYNC();
405}
406
407static void bfin_gpio_mask_irq(unsigned int irq)
408{
409 set_gpio_maska(irq - IRQ_PF0, 0);
410 SSYNC();
411}
412
413static void bfin_gpio_unmask_irq(unsigned int irq)
414{
415 set_gpio_maska(irq - IRQ_PF0, 1);
416 SSYNC();
417}
418
419static unsigned int bfin_gpio_irq_startup(unsigned int irq)
420{
1394f032
BW		 421 u16 gpionr = irq - IRQ_PF0;
422
affee2b2
MH		 423 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
424 bfin_gpio_irq_prepare(gpionr);
1394f032
BW		 425
426 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
427 bfin_gpio_unmask_irq(irq);
428
affee2b2 429 return 0;
1394f032
BW		 430}
431
432static void bfin_gpio_irq_shutdown(unsigned int irq)
433{
434 bfin_gpio_mask_irq(irq);
1394f032
BW		 435 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
436}
437
438static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
439{
1394f032
BW		 440 u16 gpionr = irq - IRQ_PF0;
441
442 if (type == IRQ_TYPE_PROBE) {
443 /* only probe unenabled GPIO interrupt lines */
444 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
445 return 0;
446 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
447 }
448
449 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
34e0fc89 450 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
affee2b2
MH		 451 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
452 bfin_gpio_irq_prepare(gpionr);
1394f032
BW		 453
454 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
455 } else {
456 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
457 return 0;
458 }
459
f1bceb47 460 set_gpio_inen(gpionr, 0);
1394f032 461 set_gpio_dir(gpionr, 0);
1394f032
BW		 462
463 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
464 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
465 set_gpio_both(gpionr, 1);
466 else
467 set_gpio_both(gpionr, 0);
468
469 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
470 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
471 else
472 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
473
f1bceb47
MH		 474 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
475 set_gpio_edge(gpionr, 1);
476 set_gpio_inen(gpionr, 1);
477 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
478 set_gpio_data(gpionr, 0);
479
480 } else {
481 set_gpio_edge(gpionr, 0);
482 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
483 set_gpio_inen(gpionr, 1);
484 }
485
1394f032
BW		 486 SSYNC();
487
488 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
bfd15117 489 bfin_set_irq_handler(irq, handle_edge_irq);
1394f032 490 else
bfd15117 491 bfin_set_irq_handler(irq, handle_level_irq);
1394f032
BW		 492
493 return 0;
494}
495
cfefe3c6
MH		 496#ifdef CONFIG_PM
497int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
498{
499 unsigned gpio = irq_to_gpio(irq);
500
501 if (state)
502 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
503 else
504 gpio_pm_wakeup_free(gpio);
505
506 return 0;
507}
508#endif
509
1394f032 510static struct irq_chip bfin_gpio_irqchip = {
763e63c6 511 .name = "GPIO",
1394f032
BW		 512 .ack = bfin_gpio_ack_irq,
513 .mask = bfin_gpio_mask_irq,
514 .mask_ack = bfin_gpio_mask_ack_irq,
515 .unmask = bfin_gpio_unmask_irq,
1f2d1869
MH		 516 .disable = bfin_gpio_mask_irq,
517 .enable = bfin_gpio_unmask_irq,
1394f032
BW		 518 .set_type = bfin_gpio_irq_type,
519 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 520 .shutdown = bfin_gpio_irq_shutdown,
521#ifdef CONFIG_PM
522 .set_wake = bfin_gpio_set_wake,
523#endif
1394f032
BW		 524};
525
2c4f829b
MH		 526static void bfin_demux_gpio_irq(unsigned int inta_irq,
527 struct irq_desc *desc)
1394f032 528{
2c4f829b
MH		 529 unsigned int i, gpio, mask, irq, search = 0;
530
531 switch (inta_irq) {
532#if defined(CONFIG_BF53x)
533 case IRQ_PROG_INTA:
534 irq = IRQ_PF0;
535 search = 1;
536 break;
537# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
538 case IRQ_MAC_RX:
539 irq = IRQ_PH0;
540 break;
541# endif
dc26aec2
MH		 542#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
543 case IRQ_PORTF_INTA:
544 irq = IRQ_PF0;
545 break;
2c4f829b
MH		 546#elif defined(CONFIG_BF52x)
547 case IRQ_PORTF_INTA:
548 irq = IRQ_PF0;
549 break;
550 case IRQ_PORTG_INTA:
551 irq = IRQ_PG0;
552 break;
553 case IRQ_PORTH_INTA:
554 irq = IRQ_PH0;
555 break;
556#elif defined(CONFIG_BF561)
557 case IRQ_PROG0_INTA:
558 irq = IRQ_PF0;
559 break;
560 case IRQ_PROG1_INTA:
561 irq = IRQ_PF16;
562 break;
563 case IRQ_PROG2_INTA:
564 irq = IRQ_PF32;
565 break;
566#endif
567 default:
568 BUG();
569 return;
570 }
571
572 if (search) {
cfefe3c6 573 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
2c4f829b
MH		 574 irq += i;
575
576 mask = get_gpiop_data(i) &
577 (gpio_enabled[gpio_bank(i)] &
578 get_gpiop_maska(i));
579
580 while (mask) {
581 if (mask & 1) {
582 desc = irq_desc + irq;
583 desc->handle_irq(irq, desc);
584 }
585 irq++;
586 mask >>= 1;
1394f032 587 }
1394f032 588 }
2c4f829b
MH		 589 } else {
590 gpio = irq_to_gpio(irq);
591 mask = get_gpiop_data(gpio) &
592 (gpio_enabled[gpio_bank(gpio)] &
593 get_gpiop_maska(gpio));
594
595 do {
596 if (mask & 1) {
597 desc = irq_desc + irq;
598 desc->handle_irq(irq, desc);
599 }
600 irq++;
601 mask >>= 1;
602 } while (mask);
1394f032 603 }
2c4f829b 604
1394f032
BW		 605}
606
a055b2b4 607#else /* CONFIG_BF54x */
34e0fc89
MH		 608
609#define NR_PINT_SYS_IRQS 4
610#define NR_PINT_BITS 32
611#define NR_PINTS 160
612#define IRQ_NOT_AVAIL 0xFF
613
614#define PINT_2_BANK(x) ((x) >> 5)
615#define PINT_2_BIT(x) ((x) & 0x1F)
616#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
617
618static unsigned char irq2pint_lut[NR_PINTS];
e3f23000 619static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
34e0fc89 620
8baf560b
MH		 621static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
622static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
623
624
34e0fc89
MH		 625struct pin_int_t {
626 unsigned int mask_set;
627 unsigned int mask_clear;
628 unsigned int request;
629 unsigned int assign;
630 unsigned int edge_set;
631 unsigned int edge_clear;
632 unsigned int invert_set;
633 unsigned int invert_clear;
634 unsigned int pinstate;
635 unsigned int latch;
636};
637
638static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
639 (struct pin_int_t *)PINT0_MASK_SET,
640 (struct pin_int_t *)PINT1_MASK_SET,
641 (struct pin_int_t *)PINT2_MASK_SET,
642 (struct pin_int_t *)PINT3_MASK_SET,
643};
644
affee2b2
MH		 645extern void bfin_gpio_irq_prepare(unsigned gpio);
646
464abc5d 647inline unsigned short get_irq_base(u8 bank, u8 bmap)
34e0fc89
MH		 648{
649
650 u16 irq_base;
651
652 if (bank < 2) { /*PA-PB */
653 irq_base = IRQ_PA0 + bmap * 16;
654 } else { /*PC-PJ */
655 irq_base = IRQ_PC0 + bmap * 16;
656 }
657
658 return irq_base;
659
660}
661
662 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
663void init_pint_lut(void)
664{
665 u16 bank, bit, irq_base, bit_pos;
666 u32 pint_assign;
667 u8 bmap;
668
669 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
670
671 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
672
673 pint_assign = pint[bank]->assign;
674
675 for (bit = 0; bit < NR_PINT_BITS; bit++) {
676
677 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
678
679 irq_base = get_irq_base(bank, bmap);
680
681 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
682 bit_pos = bit + bank * NR_PINT_BITS;
683
e3f23000 684 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
34e0fc89
MH		 685 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
686
687 }
688
689 }
690
691}
692
34e0fc89
MH		 693static void bfin_gpio_ack_irq(unsigned int irq)
694{
695 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
8baf560b
MH		 696 u32 pintbit = PINT_BIT(pint_val);
697 u8 bank = PINT_2_BANK(pint_val);
698
699 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
700 if (pint[bank]->invert_set & pintbit)
701 pint[bank]->invert_clear = pintbit;
702 else
703 pint[bank]->invert_set = pintbit;
704 }
705 pint[bank]->request = pintbit;
34e0fc89 706
34e0fc89
MH		 707 SSYNC();
708}
709
710static void bfin_gpio_mask_ack_irq(unsigned int irq)
711{
712 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 713 u32 pintbit = PINT_BIT(pint_val);
714 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 715
8baf560b
MH		 716 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
717 if (pint[bank]->invert_set & pintbit)
718 pint[bank]->invert_clear = pintbit;
719 else
720 pint[bank]->invert_set = pintbit;
721 }
722
e3f23000
MH		 723 pint[bank]->request = pintbit;
724 pint[bank]->mask_clear = pintbit;
34e0fc89
MH		 725 SSYNC();
726}
727
728static void bfin_gpio_mask_irq(unsigned int irq)
729{
730 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
731
732 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
733 SSYNC();
734}
735
736static void bfin_gpio_unmask_irq(unsigned int irq)
737{
738 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 739 u32 pintbit = PINT_BIT(pint_val);
740 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 741
e3f23000
MH		 742 pint[bank]->request = pintbit;
743 pint[bank]->mask_set = pintbit;
34e0fc89
MH		 744 SSYNC();
745}
746
747static unsigned int bfin_gpio_irq_startup(unsigned int irq)
748{
8baf560b 749 u16 gpionr = irq_to_gpio(irq);
34e0fc89
MH		 750 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
751
50e163ce
MH		 752 if (pint_val == IRQ_NOT_AVAIL) {
753 printk(KERN_ERR
754 "GPIO IRQ %d :Not in PINT Assign table "
755 "Reconfigure Interrupt to Port Assignemt\n", irq);
34e0fc89 756 return -ENODEV;
50e163ce 757 }
34e0fc89 758
affee2b2
MH		 759 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
760 bfin_gpio_irq_prepare(gpionr);
34e0fc89
MH		 761
762 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
763 bfin_gpio_unmask_irq(irq);
764
affee2b2 765 return 0;
34e0fc89
MH		 766}
767
768static void bfin_gpio_irq_shutdown(unsigned int irq)
769{
8baf560b
MH		 770 u16 gpionr = irq_to_gpio(irq);
771
34e0fc89 772 bfin_gpio_mask_irq(irq);
8baf560b 773 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
34e0fc89
MH		 774}
775
776static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
777{
778
8baf560b 779 u16 gpionr = irq_to_gpio(irq);
34e0fc89 780 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 781 u32 pintbit = PINT_BIT(pint_val);
782 u8 bank = PINT_2_BANK(pint_val);
34e0fc89
MH		 783
784 if (pint_val == IRQ_NOT_AVAIL)
785 return -ENODEV;
786
787 if (type == IRQ_TYPE_PROBE) {
788 /* only probe unenabled GPIO interrupt lines */
789 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
790 return 0;
791 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
792 }
793
794 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
795 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
affee2b2
MH		 796 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
797 bfin_gpio_irq_prepare(gpionr);
34e0fc89
MH		 798
799 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
800 } else {
801 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
802 return 0;
803 }
804
34e0fc89 805 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
e3f23000 806 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
34e0fc89 807 else
8baf560b 808 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
34e0fc89 809
8baf560b
MH		 810 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
811 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
34e0fc89 812
8baf560b 813 gpio_both_edge_triggered[bank] |= pintbit;
34e0fc89 814
8baf560b
MH		 815 if (gpio_get_value(gpionr))
816 pint[bank]->invert_set = pintbit;
817 else
818 pint[bank]->invert_clear = pintbit;
819 } else {
820 gpio_both_edge_triggered[bank] &= ~pintbit;
821 }
822
823 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
824 pint[bank]->edge_set = pintbit;
bfd15117 825 bfin_set_irq_handler(irq, handle_edge_irq);
8baf560b
MH		 826 } else {
827 pint[bank]->edge_clear = pintbit;
bfd15117 828 bfin_set_irq_handler(irq, handle_level_irq);
8baf560b
MH		 829 }
830
831 SSYNC();
34e0fc89
MH		 832
833 return 0;
834}
835
cfefe3c6
MH		 836#ifdef CONFIG_PM
837u32 pint_saved_masks[NR_PINT_SYS_IRQS];
838u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
839
840int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
841{
842 u32 pint_irq;
843 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
844 u32 bank = PINT_2_BANK(pint_val);
845 u32 pintbit = PINT_BIT(pint_val);
846
847 switch (bank) {
848 case 0:
849 pint_irq = IRQ_PINT0;
850 break;
851 case 2:
852 pint_irq = IRQ_PINT2;
853 break;
854 case 3:
855 pint_irq = IRQ_PINT3;
856 break;
857 case 1:
858 pint_irq = IRQ_PINT1;
859 break;
860 default:
861 return -EINVAL;
862 }
863
864 bfin_internal_set_wake(pint_irq, state);
865
866 if (state)
867 pint_wakeup_masks[bank] |= pintbit;
868 else
869 pint_wakeup_masks[bank] &= ~pintbit;
870
871 return 0;
872}
873
874u32 bfin_pm_setup(void)
875{
876 u32 val, i;
877
878 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
879 val = pint[i]->mask_clear;
880 pint_saved_masks[i] = val;
881 if (val ^ pint_wakeup_masks[i]) {
882 pint[i]->mask_clear = val;
883 pint[i]->mask_set = pint_wakeup_masks[i];
884 }
885 }
886
887 return 0;
888}
889
890void bfin_pm_restore(void)
891{
892 u32 i, val;
893
894 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
895 val = pint_saved_masks[i];
896 if (val ^ pint_wakeup_masks[i]) {
897 pint[i]->mask_clear = pint[i]->mask_clear;
898 pint[i]->mask_set = val;
899 }
900 }
901}
902#endif
903
34e0fc89 904static struct irq_chip bfin_gpio_irqchip = {
763e63c6 905 .name = "GPIO",
34e0fc89
MH		 906 .ack = bfin_gpio_ack_irq,
907 .mask = bfin_gpio_mask_irq,
908 .mask_ack = bfin_gpio_mask_ack_irq,
909 .unmask = bfin_gpio_unmask_irq,
1f2d1869
MH		 910 .disable = bfin_gpio_mask_irq,
911 .enable = bfin_gpio_unmask_irq,
34e0fc89
MH		 912 .set_type = bfin_gpio_irq_type,
913 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 914 .shutdown = bfin_gpio_irq_shutdown,
915#ifdef CONFIG_PM
916 .set_wake = bfin_gpio_set_wake,
917#endif
34e0fc89
MH		 918};
919
2c4f829b
MH		 920static void bfin_demux_gpio_irq(unsigned int inta_irq,
921 struct irq_desc *desc)
34e0fc89
MH		 922{
923 u8 bank, pint_val;
924 u32 request, irq;
925
2c4f829b 926 switch (inta_irq) {
34e0fc89
MH		 927 case IRQ_PINT0:
928 bank = 0;
929 break;
930 case IRQ_PINT2:
931 bank = 2;
932 break;
933 case IRQ_PINT3:
934 bank = 3;
935 break;
936 case IRQ_PINT1:
937 bank = 1;
938 break;
e3f23000
MH		 939 default:
940 return;
34e0fc89
MH		 941 }
942
943 pint_val = bank * NR_PINT_BITS;
944
945 request = pint[bank]->request;
946
947 while (request) {
948 if (request & 1) {
e3f23000
MH		 949 irq = pint2irq_lut[pint_val] + SYS_IRQS;
950 desc = irq_desc + irq;
34e0fc89
MH		 951 desc->handle_irq(irq, desc);
952 }
953 pint_val++;
954 request >>= 1;
955 }
956
957}
a055b2b4 958#endif
1394f032 959
8be80ed3
BS		 960void __init init_exception_vectors(void)
961{
962 SSYNC();
963
f0b5d12f
MF		 964 /* cannot program in software:
965 * evt0 - emulation (jtag)
966 * evt1 - reset
967 */
968 bfin_write_EVT2(evt_nmi);
8be80ed3
BS		 969 bfin_write_EVT3(trap);
970 bfin_write_EVT5(evt_ivhw);
971 bfin_write_EVT6(evt_timer);
972 bfin_write_EVT7(evt_evt7);
973 bfin_write_EVT8(evt_evt8);
974 bfin_write_EVT9(evt_evt9);
975 bfin_write_EVT10(evt_evt10);
976 bfin_write_EVT11(evt_evt11);
977 bfin_write_EVT12(evt_evt12);
978 bfin_write_EVT13(evt_evt13);
979 bfin_write_EVT14(evt14_softirq);
980 bfin_write_EVT15(evt_system_call);
981 CSYNC();
982}
983
1394f032
BW		 984/*
985 * This function should be called during kernel startup to initialize
986 * the BFin IRQ handling routines.
987 */
988int __init init_arch_irq(void)
989{
990 int irq;
991 unsigned long ilat = 0;
992 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
dc26aec2 993#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
24a07a12
RH		 994 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
995 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
a055b2b4 996# ifdef CONFIG_BF54x
59003145 997 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
a055b2b4 998# endif
24a07a12 999#else
1394f032 1000 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
24a07a12 1001#endif
1394f032
BW		 1002
1003 local_irq_disable();
1004
d70536ec 1005#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
95a86b5e
MF		 1006 /* Clear EMAC Interrupt Status bits so we can demux it later */
1007 bfin_write_EMAC_SYSTAT(-1);
1008#endif
1009
a055b2b4
MF		 1010#ifdef CONFIG_BF54x
1011# ifdef CONFIG_PINTx_REASSIGN
34e0fc89
MH		 1012 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1013 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1014 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1015 pint[3]->assign = CONFIG_PINT3_ASSIGN;
a055b2b4 1016# endif
34e0fc89
MH		 1017 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1018 init_pint_lut();
1019#endif
1020
1021 for (irq = 0; irq <= SYS_IRQS; irq++) {
1394f032
BW		 1022 if (irq <= IRQ_CORETMR)
1023 set_irq_chip(irq, &bfin_core_irqchip);
1024 else
1025 set_irq_chip(irq, &bfin_internal_irqchip);
1394f032 1026
464abc5d 1027 switch (irq) {
59003145 1028#if defined(CONFIG_BF53x)
464abc5d 1029 case IRQ_PROG_INTA:
a055b2b4 1030# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
464abc5d 1031 case IRQ_MAC_RX:
a055b2b4 1032# endif
59003145 1033#elif defined(CONFIG_BF54x)
464abc5d
MH		 1034 case IRQ_PINT0:
1035 case IRQ_PINT1:
1036 case IRQ_PINT2:
1037 case IRQ_PINT3:
59003145 1038#elif defined(CONFIG_BF52x)
464abc5d
MH		 1039 case IRQ_PORTF_INTA:
1040 case IRQ_PORTG_INTA:
1041 case IRQ_PORTH_INTA:
2c4f829b 1042#elif defined(CONFIG_BF561)
464abc5d
MH		 1043 case IRQ_PROG0_INTA:
1044 case IRQ_PROG1_INTA:
1045 case IRQ_PROG2_INTA:
dc26aec2
MH		 1046#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1047 case IRQ_PORTF_INTA:
1394f032 1048#endif
dc26aec2 1049
464abc5d
MH		 1050 set_irq_chained_handler(irq,
1051 bfin_demux_gpio_irq);
1052 break;
1394f032 1053#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d 1054 case IRQ_GENERIC_ERROR:
1394f032 1055 set_irq_handler(irq, bfin_demux_error_irq);
464abc5d
MH		 1056
1057 break;
1394f032 1058#endif
464abc5d
MH		 1059 default:
1060 set_irq_handler(irq, handle_simple_irq);
1061 break;
1062 }
1394f032 1063 }
464abc5d 1064
1394f032 1065#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d
MH		 1066 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1067 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1068 handle_level_irq);
1394f032
BW		 1069#endif
1070
464abc5d
MH		 1071 /* if configured as edge, then will be changed to do_edge_IRQ */
1072 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1073 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1074 handle_level_irq);
2c4f829b 1075
a055b2b4 1076
1394f032
BW		 1077 bfin_write_IMASK(0);
1078 CSYNC();
1079 ilat = bfin_read_ILAT();
1080 CSYNC();
1081 bfin_write_ILAT(ilat);
1082 CSYNC();
1083
34e0fc89 1084 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1394f032
BW		 1085 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1086 * local_irq_enable()
1087 */
1088 program_IAR();
1089 /* Therefore it's better to setup IARs before interrupts enabled */
1090 search_IAR();
1091
1092 /* Enable interrupts IVG7-15 */
1093 irq_flags = irq_flags | IMASK_IVG15 |
1094 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
34e0fc89 1095 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1394f032 1096
dc26aec2 1097#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
56f5f590 1098 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
55546ac4
MH		 1099#if defined(CONFIG_BF52x)
1100 /* BF52x system reset does not properly reset SIC_IWR1 which
1101 * will screw up the bootrom as it relies on MDMA0/1 waking it
1102 * up from IDLE instructions. See this report for more info:
1103 * http://blackfin.uclinux.org/gf/tracker/4323
1104 */
1105 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1106#else
56f5f590 1107 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
55546ac4 1108#endif
fe9ec9b9 1109# ifdef CONFIG_BF54x
56f5f590 1110 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
fe9ec9b9
MH		 1111# endif
1112#else
56f5f590 1113 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
fe9ec9b9
MH		 1114#endif
1115
1394f032
BW		 1116 return 0;
1117}
1118
1119#ifdef CONFIG_DO_IRQ_L1
a055b2b4 1120__attribute__((l1_text))
1394f032 1121#endif
1394f032
BW		 1122void do_irq(int vec, struct pt_regs *fp)
1123{
1124 if (vec == EVT_IVTMR_P) {
1125 vec = IRQ_CORETMR;
1126 } else {
1127 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1128 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
dc26aec2 1129#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
24a07a12 1130 unsigned long sic_status[3];
1394f032 1131
4fb45241
MH		 1132 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1133 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
59003145 1134#ifdef CONFIG_BF54x
4fb45241 1135 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
59003145 1136#endif
1f83b8f1 1137 for (;; ivg++) {
24a07a12
RH		 1138 if (ivg >= ivg_stop) {
1139 atomic_inc(&num_spurious);
1140 return;
1141 }
34e0fc89 1142 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
24a07a12
RH		 1143 break;
1144 }
1145#else
1146 unsigned long sic_status;
464abc5d 1147
1394f032
BW		 1148 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1149
1150 for (;; ivg++) {
1151 if (ivg >= ivg_stop) {
1152 atomic_inc(&num_spurious);
1153 return;
1154 } else if (sic_status & ivg->isrflag)
1155 break;
1156 }
24a07a12 1157#endif
1394f032
BW		 1158 vec = ivg->irqno;
1159 }
1160 asm_do_IRQ(vec, fp);
1394f032 1161}
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