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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
041cadca MS |
2 | |
3 | / { | |
4 | #address-cells = <1>; | |
5 | #size-cells = <1>; | |
6 | ||
7 | cpus { | |
8 | #address-cells = <1>; | |
9 | #size-cells = <0>; | |
10 | ||
11 | cpu@0 { | |
12 | device_type = "cpu"; | |
13 | reg = <0>; | |
14 | model = "ti,c64x+"; | |
15 | }; | |
16 | cpu@1 { | |
17 | device_type = "cpu"; | |
18 | reg = <1>; | |
19 | model = "ti,c64x+"; | |
20 | }; | |
21 | cpu@2 { | |
22 | device_type = "cpu"; | |
23 | reg = <2>; | |
24 | model = "ti,c64x+"; | |
25 | }; | |
26 | cpu@3 { | |
27 | device_type = "cpu"; | |
28 | reg = <3>; | |
29 | model = "ti,c64x+"; | |
30 | }; | |
31 | cpu@4 { | |
32 | device_type = "cpu"; | |
33 | reg = <4>; | |
34 | model = "ti,c64x+"; | |
35 | }; | |
36 | cpu@5 { | |
37 | device_type = "cpu"; | |
38 | reg = <5>; | |
39 | model = "ti,c64x+"; | |
40 | }; | |
41 | }; | |
42 | ||
43 | soc { | |
44 | compatible = "simple-bus"; | |
45 | model = "tms320c6472"; | |
46 | #address-cells = <1>; | |
47 | #size-cells = <1>; | |
48 | ranges; | |
49 | ||
50 | core_pic: interrupt-controller { | |
51 | compatible = "ti,c64x+core-pic"; | |
52 | interrupt-controller; | |
53 | #interrupt-cells = <1>; | |
54 | }; | |
55 | ||
56 | megamod_pic: interrupt-controller@1800000 { | |
57 | compatible = "ti,c64x+megamod-pic"; | |
58 | interrupt-controller; | |
59 | #interrupt-cells = <1>; | |
60 | reg = <0x1800000 0x1000>; | |
61 | interrupt-parent = <&core_pic>; | |
62 | }; | |
63 | ||
64 | cache-controller@1840000 { | |
65 | compatible = "ti,c64x+cache"; | |
66 | reg = <0x01840000 0x8400>; | |
67 | }; | |
68 | ||
69 | timer0: timer@25e0000 { | |
70 | compatible = "ti,c64x+timer64"; | |
71 | ti,core-mask = < 0x01 >; | |
72 | reg = <0x25e0000 0x40>; | |
73 | }; | |
74 | ||
75 | timer1: timer@25f0000 { | |
76 | compatible = "ti,c64x+timer64"; | |
77 | ti,core-mask = < 0x02 >; | |
78 | reg = <0x25f0000 0x40>; | |
79 | }; | |
80 | ||
81 | timer2: timer@2600000 { | |
82 | compatible = "ti,c64x+timer64"; | |
83 | ti,core-mask = < 0x04 >; | |
84 | reg = <0x2600000 0x40>; | |
85 | }; | |
86 | ||
87 | timer3: timer@2610000 { | |
88 | compatible = "ti,c64x+timer64"; | |
89 | ti,core-mask = < 0x08 >; | |
90 | reg = <0x2610000 0x40>; | |
91 | }; | |
92 | ||
93 | timer4: timer@2620000 { | |
94 | compatible = "ti,c64x+timer64"; | |
95 | ti,core-mask = < 0x10 >; | |
96 | reg = <0x2620000 0x40>; | |
97 | }; | |
98 | ||
99 | timer5: timer@2630000 { | |
100 | compatible = "ti,c64x+timer64"; | |
101 | ti,core-mask = < 0x20 >; | |
102 | reg = <0x2630000 0x40>; | |
103 | }; | |
104 | ||
105 | clock-controller@29a0000 { | |
106 | compatible = "ti,c6472-pll", "ti,c64x+pll"; | |
107 | reg = <0x029a0000 0x200>; | |
108 | ti,c64x+pll-bypass-delay = <200>; | |
109 | ti,c64x+pll-reset-delay = <12000>; | |
110 | ti,c64x+pll-lock-delay = <80000>; | |
111 | }; | |
112 | ||
113 | device-state-controller@2a80000 { | |
114 | compatible = "ti,c64x+dscr"; | |
115 | reg = <0x02a80000 0x1000>; | |
116 | ||
117 | ti,dscr-devstat = <0>; | |
118 | ti,dscr-silicon-rev = <0x70c 16 0xff>; | |
119 | ||
120 | ti,dscr-mac-fuse-regs = <0x700 1 2 3 4 | |
121 | 0x704 5 6 0 0>; | |
122 | ||
123 | ti,dscr-rmii-resets = <0x208 1 | |
124 | 0x20c 1>; | |
125 | ||
126 | ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a | |
127 | 0x40c 0x420 0xbea7 | |
128 | 0x41c 0x420 0xbea7>; | |
129 | ||
130 | ti,dscr-privperm = <0x41c 0xaaaaaaaa>; | |
131 | ||
132 | ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>; | |
133 | }; | |
134 | }; | |
135 | }; |