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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/i386/kernel/head.S -- the 32-bit startup code. | |
3 | * | |
4 | * Copyright (C) 1991, 1992 Linus Torvalds | |
5 | * | |
6 | * Enhanced CPU detection and feature setting code by Mike Jagdis | |
7 | * and Martin Mares, November 1997. | |
8 | */ | |
9 | ||
10 | .text | |
1da177e4 LT |
11 | #include <linux/threads.h> |
12 | #include <linux/linkage.h> | |
13 | #include <asm/segment.h> | |
14 | #include <asm/page.h> | |
15 | #include <asm/pgtable.h> | |
16 | #include <asm/desc.h> | |
17 | #include <asm/cache.h> | |
18 | #include <asm/thread_info.h> | |
86feeaa8 | 19 | #include <asm/asm-offsets.h> |
1da177e4 LT |
20 | #include <asm/setup.h> |
21 | ||
22 | /* | |
23 | * References to members of the new_cpu_data structure. | |
24 | */ | |
25 | ||
26 | #define X86 new_cpu_data+CPUINFO_x86 | |
27 | #define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor | |
28 | #define X86_MODEL new_cpu_data+CPUINFO_x86_model | |
29 | #define X86_MASK new_cpu_data+CPUINFO_x86_mask | |
30 | #define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math | |
31 | #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level | |
32 | #define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability | |
33 | #define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id | |
34 | ||
35 | /* | |
36 | * This is how much memory *in addition to the memory covered up to | |
37 | * and including _end* we need mapped initially. We need one bit for | |
38 | * each possible page, but only in low memory, which means | |
39 | * 2^32/4096/8 = 128K worst case (4G/4G split.) | |
40 | * | |
41 | * Modulo rounding, each megabyte assigned here requires a kilobyte of | |
42 | * memory, which is currently unreclaimed. | |
43 | * | |
44 | * This should be a multiple of a page. | |
45 | */ | |
46 | #define INIT_MAP_BEYOND_END (128*1024) | |
47 | ||
48 | ||
49 | /* | |
50 | * 32-bit kernel entrypoint; only used by the boot CPU. On entry, | |
51 | * %esi points to the real-mode code as a 32-bit pointer. | |
52 | * CS and DS must be 4 GB flat segments, but we don't depend on | |
53 | * any particular GDT layout, because we load our own as soon as we | |
54 | * can. | |
55 | */ | |
56 | ENTRY(startup_32) | |
57 | ||
c9ccf30d RR |
58 | #ifdef CONFIG_PARAVIRT |
59 | movl %cs, %eax | |
60 | testl $0x3, %eax | |
61 | jnz startup_paravirt | |
62 | #endif | |
63 | ||
1da177e4 LT |
64 | /* |
65 | * Set segments to known values. | |
66 | */ | |
67 | cld | |
68 | lgdt boot_gdt_descr - __PAGE_OFFSET | |
69 | movl $(__BOOT_DS),%eax | |
70 | movl %eax,%ds | |
71 | movl %eax,%es | |
72 | movl %eax,%fs | |
73 | movl %eax,%gs | |
74 | ||
75 | /* | |
76 | * Clear BSS first so that there are no surprises... | |
77 | * No need to cld as DF is already clear from cld above... | |
78 | */ | |
79 | xorl %eax,%eax | |
80 | movl $__bss_start - __PAGE_OFFSET,%edi | |
81 | movl $__bss_stop - __PAGE_OFFSET,%ecx | |
82 | subl %edi,%ecx | |
83 | shrl $2,%ecx | |
84 | rep ; stosl | |
484b90c4 VG |
85 | /* |
86 | * Copy bootup parameters out of the way. | |
87 | * Note: %esi still has the pointer to the real-mode data. | |
88 | * With the kexec as boot loader, parameter segment might be loaded beyond | |
89 | * kernel image and might not even be addressable by early boot page tables. | |
90 | * (kexec on panic case). Hence copy out the parameters before initializing | |
91 | * page tables. | |
92 | */ | |
93 | movl $(boot_params - __PAGE_OFFSET),%edi | |
94 | movl $(PARAM_SIZE/4),%ecx | |
95 | cld | |
96 | rep | |
97 | movsl | |
98 | movl boot_params - __PAGE_OFFSET + NEW_CL_POINTER,%esi | |
99 | andl %esi,%esi | |
100 | jnz 2f # New command line protocol | |
101 | cmpw $(OLD_CL_MAGIC),OLD_CL_MAGIC_ADDR | |
102 | jne 1f | |
103 | movzwl OLD_CL_OFFSET,%esi | |
104 | addl $(OLD_CL_BASE_ADDR),%esi | |
105 | 2: | |
4e498b66 | 106 | movl $(boot_command_line - __PAGE_OFFSET),%edi |
484b90c4 VG |
107 | movl $(COMMAND_LINE_SIZE/4),%ecx |
108 | rep | |
109 | movsl | |
110 | 1: | |
1da177e4 LT |
111 | |
112 | /* | |
113 | * Initialize page tables. This creates a PDE and a set of page | |
114 | * tables, which are located immediately beyond _end. The variable | |
115 | * init_pg_tables_end is set up to point to the first "safe" location. | |
116 | * Mappings are created both at virtual address 0 (identity mapping) | |
117 | * and PAGE_OFFSET for up to _end+sizeof(page tables)+INIT_MAP_BEYOND_END. | |
118 | * | |
119 | * Warning: don't use %esi or the stack in this code. However, %esp | |
120 | * can be used as a GPR if you really need it... | |
121 | */ | |
122 | page_pde_offset = (__PAGE_OFFSET >> 20); | |
123 | ||
124 | movl $(pg0 - __PAGE_OFFSET), %edi | |
125 | movl $(swapper_pg_dir - __PAGE_OFFSET), %edx | |
126 | movl $0x007, %eax /* 0x007 = PRESENT+RW+USER */ | |
127 | 10: | |
128 | leal 0x007(%edi),%ecx /* Create PDE entry */ | |
129 | movl %ecx,(%edx) /* Store identity PDE entry */ | |
130 | movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */ | |
131 | addl $4,%edx | |
132 | movl $1024, %ecx | |
133 | 11: | |
134 | stosl | |
135 | addl $0x1000,%eax | |
136 | loop 11b | |
137 | /* End condition: we must map up to and including INIT_MAP_BEYOND_END */ | |
138 | /* bytes beyond the end of our own page tables; the +0x007 is the attribute bits */ | |
139 | leal (INIT_MAP_BEYOND_END+0x007)(%edi),%ebp | |
140 | cmpl %ebp,%eax | |
141 | jb 10b | |
142 | movl %edi,(init_pg_tables_end - __PAGE_OFFSET) | |
143 | ||
144 | #ifdef CONFIG_SMP | |
145 | xorl %ebx,%ebx /* This is the boot CPU (BSP) */ | |
146 | jmp 3f | |
147 | ||
148 | /* | |
149 | * Non-boot CPU entry point; entered from trampoline.S | |
150 | * We can't lgdt here, because lgdt itself uses a data segment, but | |
151 | * we know the trampoline has already loaded the boot_gdt_table GDT | |
152 | * for us. | |
153 | */ | |
154 | ENTRY(startup_32_smp) | |
155 | cld | |
156 | movl $(__BOOT_DS),%eax | |
157 | movl %eax,%ds | |
158 | movl %eax,%es | |
159 | movl %eax,%fs | |
160 | movl %eax,%gs | |
161 | ||
162 | /* | |
163 | * New page tables may be in 4Mbyte page mode and may | |
164 | * be using the global pages. | |
165 | * | |
166 | * NOTE! If we are on a 486 we may have no cr4 at all! | |
167 | * So we do not try to touch it unless we really have | |
168 | * some bits in it to set. This won't work if the BSP | |
169 | * implements cr4 but this AP does not -- very unlikely | |
170 | * but be warned! The same applies to the pse feature | |
171 | * if not equally supported. --macro | |
172 | * | |
173 | * NOTE! We have to correct for the fact that we're | |
174 | * not yet offset PAGE_OFFSET.. | |
175 | */ | |
176 | #define cr4_bits mmu_cr4_features-__PAGE_OFFSET | |
177 | movl cr4_bits,%edx | |
178 | andl %edx,%edx | |
179 | jz 6f | |
180 | movl %cr4,%eax # Turn on paging options (PSE,PAE,..) | |
181 | orl %edx,%eax | |
182 | movl %eax,%cr4 | |
183 | ||
184 | btl $5, %eax # check if PAE is enabled | |
185 | jnc 6f | |
186 | ||
187 | /* Check if extended functions are implemented */ | |
188 | movl $0x80000000, %eax | |
189 | cpuid | |
190 | cmpl $0x80000000, %eax | |
191 | jbe 6f | |
192 | mov $0x80000001, %eax | |
193 | cpuid | |
194 | /* Execute Disable bit supported? */ | |
195 | btl $20, %edx | |
196 | jnc 6f | |
197 | ||
198 | /* Setup EFER (Extended Feature Enable Register) */ | |
199 | movl $0xc0000080, %ecx | |
200 | rdmsr | |
201 | ||
202 | btsl $11, %eax | |
203 | /* Make changes effective */ | |
204 | wrmsr | |
205 | ||
206 | 6: | |
207 | /* This is a secondary processor (AP) */ | |
208 | xorl %ebx,%ebx | |
209 | incl %ebx | |
210 | ||
211 | 3: | |
212 | #endif /* CONFIG_SMP */ | |
213 | ||
214 | /* | |
215 | * Enable paging | |
216 | */ | |
217 | movl $swapper_pg_dir-__PAGE_OFFSET,%eax | |
218 | movl %eax,%cr3 /* set the page table pointer.. */ | |
219 | movl %cr0,%eax | |
220 | orl $0x80000000,%eax | |
221 | movl %eax,%cr0 /* ..and set paging (PG) bit */ | |
222 | ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */ | |
223 | 1: | |
224 | /* Set up the stack pointer */ | |
225 | lss stack_start,%esp | |
226 | ||
227 | /* | |
228 | * Initialize eflags. Some BIOS's leave bits like NT set. This would | |
229 | * confuse the debugger if this code is traced. | |
230 | * XXX - best to initialize before switching to protected mode. | |
231 | */ | |
232 | pushl $0 | |
233 | popfl | |
234 | ||
235 | #ifdef CONFIG_SMP | |
236 | andl %ebx,%ebx | |
237 | jz 1f /* Initial CPU cleans BSS */ | |
238 | jmp checkCPUtype | |
239 | 1: | |
240 | #endif /* CONFIG_SMP */ | |
241 | ||
242 | /* | |
243 | * start system 32-bit setup. We need to re-do some of the things done | |
244 | * in 16-bit mode for the "real" operations. | |
245 | */ | |
246 | call setup_idt | |
247 | ||
1da177e4 LT |
248 | checkCPUtype: |
249 | ||
250 | movl $-1,X86_CPUID # -1 for no CPUID initially | |
251 | ||
252 | /* check if it is 486 or 386. */ | |
253 | /* | |
254 | * XXX - this does a lot of unnecessary setup. Alignment checks don't | |
255 | * apply at our cpl of 0 and the stack ought to be aligned already, and | |
256 | * we don't need to preserve eflags. | |
257 | */ | |
258 | ||
259 | movb $3,X86 # at least 386 | |
260 | pushfl # push EFLAGS | |
261 | popl %eax # get EFLAGS | |
262 | movl %eax,%ecx # save original EFLAGS | |
263 | xorl $0x240000,%eax # flip AC and ID bits in EFLAGS | |
264 | pushl %eax # copy to EFLAGS | |
265 | popfl # set EFLAGS | |
266 | pushfl # get new EFLAGS | |
267 | popl %eax # put it in eax | |
268 | xorl %ecx,%eax # change in flags | |
269 | pushl %ecx # restore original EFLAGS | |
270 | popfl | |
271 | testl $0x40000,%eax # check if AC bit changed | |
272 | je is386 | |
273 | ||
274 | movb $4,X86 # at least 486 | |
275 | testl $0x200000,%eax # check if ID bit changed | |
276 | je is486 | |
277 | ||
278 | /* get vendor info */ | |
279 | xorl %eax,%eax # call CPUID with 0 -> return vendor ID | |
280 | cpuid | |
281 | movl %eax,X86_CPUID # save CPUID level | |
282 | movl %ebx,X86_VENDOR_ID # lo 4 chars | |
283 | movl %edx,X86_VENDOR_ID+4 # next 4 chars | |
284 | movl %ecx,X86_VENDOR_ID+8 # last 4 chars | |
285 | ||
286 | orl %eax,%eax # do we have processor info as well? | |
287 | je is486 | |
288 | ||
289 | movl $1,%eax # Use the CPUID instruction to get CPU type | |
290 | cpuid | |
291 | movb %al,%cl # save reg for future use | |
292 | andb $0x0f,%ah # mask processor family | |
293 | movb %ah,X86 | |
294 | andb $0xf0,%al # mask model | |
295 | shrb $4,%al | |
296 | movb %al,X86_MODEL | |
297 | andb $0x0f,%cl # mask mask revision | |
298 | movb %cl,X86_MASK | |
299 | movl %edx,X86_CAPABILITY | |
300 | ||
301 | is486: movl $0x50022,%ecx # set AM, WP, NE and MP | |
302 | jmp 2f | |
303 | ||
304 | is386: movl $2,%ecx # set MP | |
305 | 2: movl %cr0,%eax | |
306 | andl $0x80000011,%eax # Save PG,PE,ET | |
307 | orl %ecx,%eax | |
308 | movl %eax,%cr0 | |
309 | ||
310 | call check_x87 | |
f95d47ca | 311 | call setup_pda |
1da177e4 LT |
312 | lgdt cpu_gdt_descr |
313 | lidt idt_descr | |
314 | ljmp $(__KERNEL_CS),$1f | |
315 | 1: movl $(__KERNEL_DS),%eax # reload all the segment registers | |
316 | movl %eax,%ss # after changing gdt. | |
317 | ||
318 | movl $(__USER_DS),%eax # DS/ES contains default USER segment | |
319 | movl %eax,%ds | |
320 | movl %eax,%es | |
321 | ||
464d1a78 JF |
322 | xorl %eax,%eax # Clear GS and LDT |
323 | movl %eax,%gs | |
1da177e4 | 324 | lldt %ax |
f95d47ca JF |
325 | |
326 | movl $(__KERNEL_PDA),%eax | |
464d1a78 | 327 | mov %eax,%fs |
f95d47ca | 328 | |
1da177e4 | 329 | cld # gcc2 wants the direction flag cleared at all times |
26fd5e08 | 330 | pushl $0 # fake return address for unwinder |
1da177e4 | 331 | #ifdef CONFIG_SMP |
d92de65c SL |
332 | movb ready, %cl |
333 | movb $1, ready | |
29fe5f3b AK |
334 | cmpb $0,%cl # the first CPU calls start_kernel |
335 | jne initialize_secondary # all other CPUs call initialize_secondary | |
1da177e4 | 336 | #endif /* CONFIG_SMP */ |
29fe5f3b | 337 | jmp start_kernel |
1da177e4 LT |
338 | |
339 | /* | |
340 | * We depend on ET to be correct. This checks for 287/387. | |
341 | */ | |
342 | check_x87: | |
343 | movb $0,X86_HARD_MATH | |
344 | clts | |
345 | fninit | |
346 | fstsw %ax | |
347 | cmpb $0,%al | |
348 | je 1f | |
349 | movl %cr0,%eax /* no coprocessor: have to set bits */ | |
350 | xorl $4,%eax /* set EM */ | |
351 | movl %eax,%cr0 | |
352 | ret | |
353 | ALIGN | |
354 | 1: movb $1,X86_HARD_MATH | |
355 | .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */ | |
356 | ret | |
357 | ||
f95d47ca JF |
358 | /* |
359 | * Point the GDT at this CPU's PDA. On boot this will be | |
360 | * cpu_gdt_table and boot_pda; for secondary CPUs, these will be | |
361 | * that CPU's GDT and PDA. | |
362 | */ | |
363 | setup_pda: | |
364 | /* get the PDA pointer */ | |
365 | movl start_pda, %eax | |
366 | ||
367 | /* slot the PDA address into the GDT */ | |
368 | mov cpu_gdt_descr+2, %ecx | |
369 | mov %ax, (__KERNEL_PDA+0+2)(%ecx) /* base & 0x0000ffff */ | |
370 | shr $16, %eax | |
371 | mov %al, (__KERNEL_PDA+4+0)(%ecx) /* base & 0x00ff0000 */ | |
372 | mov %ah, (__KERNEL_PDA+4+3)(%ecx) /* base & 0xff000000 */ | |
373 | ret | |
374 | ||
1da177e4 LT |
375 | /* |
376 | * setup_idt | |
377 | * | |
378 | * sets up a idt with 256 entries pointing to | |
379 | * ignore_int, interrupt gates. It doesn't actually load | |
380 | * idt - that can be done only after paging has been enabled | |
381 | * and the kernel moved to PAGE_OFFSET. Interrupts | |
382 | * are enabled elsewhere, when we can be relatively | |
383 | * sure everything is ok. | |
384 | * | |
385 | * Warning: %esi is live across this function. | |
386 | */ | |
387 | setup_idt: | |
388 | lea ignore_int,%edx | |
389 | movl $(__KERNEL_CS << 16),%eax | |
390 | movw %dx,%ax /* selector = 0x0010 = cs */ | |
391 | movw $0x8E00,%dx /* interrupt gate - dpl=0, present */ | |
392 | ||
393 | lea idt_table,%edi | |
394 | mov $256,%ecx | |
395 | rp_sidt: | |
396 | movl %eax,(%edi) | |
397 | movl %edx,4(%edi) | |
398 | addl $8,%edi | |
399 | dec %ecx | |
400 | jne rp_sidt | |
ec5c0926 CE |
401 | |
402 | .macro set_early_handler handler,trapno | |
403 | lea \handler,%edx | |
404 | movl $(__KERNEL_CS << 16),%eax | |
405 | movw %dx,%ax | |
406 | movw $0x8E00,%dx /* interrupt gate - dpl=0, present */ | |
407 | lea idt_table,%edi | |
408 | movl %eax,8*\trapno(%edi) | |
409 | movl %edx,8*\trapno+4(%edi) | |
410 | .endm | |
411 | ||
412 | set_early_handler handler=early_divide_err,trapno=0 | |
413 | set_early_handler handler=early_illegal_opcode,trapno=6 | |
414 | set_early_handler handler=early_protection_fault,trapno=13 | |
415 | set_early_handler handler=early_page_fault,trapno=14 | |
416 | ||
1da177e4 LT |
417 | ret |
418 | ||
ec5c0926 CE |
419 | early_divide_err: |
420 | xor %edx,%edx | |
421 | pushl $0 /* fake errcode */ | |
422 | jmp early_fault | |
423 | ||
424 | early_illegal_opcode: | |
425 | movl $6,%edx | |
426 | pushl $0 /* fake errcode */ | |
427 | jmp early_fault | |
428 | ||
429 | early_protection_fault: | |
430 | movl $13,%edx | |
431 | jmp early_fault | |
432 | ||
433 | early_page_fault: | |
434 | movl $14,%edx | |
435 | jmp early_fault | |
436 | ||
437 | early_fault: | |
438 | cld | |
439 | #ifdef CONFIG_PRINTK | |
440 | movl $(__KERNEL_DS),%eax | |
441 | movl %eax,%ds | |
442 | movl %eax,%es | |
443 | cmpl $2,early_recursion_flag | |
444 | je hlt_loop | |
445 | incl early_recursion_flag | |
446 | movl %cr2,%eax | |
447 | pushl %eax | |
448 | pushl %edx /* trapno */ | |
449 | pushl $fault_msg | |
450 | #ifdef CONFIG_EARLY_PRINTK | |
451 | call early_printk | |
452 | #else | |
453 | call printk | |
454 | #endif | |
455 | #endif | |
456 | hlt_loop: | |
457 | hlt | |
458 | jmp hlt_loop | |
459 | ||
1da177e4 LT |
460 | /* This is the default interrupt "handler" :-) */ |
461 | ALIGN | |
462 | ignore_int: | |
463 | cld | |
d59745ce | 464 | #ifdef CONFIG_PRINTK |
1da177e4 LT |
465 | pushl %eax |
466 | pushl %ecx | |
467 | pushl %edx | |
468 | pushl %es | |
469 | pushl %ds | |
470 | movl $(__KERNEL_DS),%eax | |
471 | movl %eax,%ds | |
472 | movl %eax,%es | |
ec5c0926 CE |
473 | cmpl $2,early_recursion_flag |
474 | je hlt_loop | |
475 | incl early_recursion_flag | |
1da177e4 LT |
476 | pushl 16(%esp) |
477 | pushl 24(%esp) | |
478 | pushl 32(%esp) | |
479 | pushl 40(%esp) | |
480 | pushl $int_msg | |
c0cdf193 IM |
481 | #ifdef CONFIG_EARLY_PRINTK |
482 | call early_printk | |
483 | #else | |
1da177e4 | 484 | call printk |
c0cdf193 | 485 | #endif |
1da177e4 LT |
486 | addl $(5*4),%esp |
487 | popl %ds | |
488 | popl %es | |
489 | popl %edx | |
490 | popl %ecx | |
491 | popl %eax | |
d59745ce | 492 | #endif |
1da177e4 LT |
493 | iret |
494 | ||
c9ccf30d RR |
495 | #ifdef CONFIG_PARAVIRT |
496 | startup_paravirt: | |
497 | cld | |
498 | movl $(init_thread_union+THREAD_SIZE),%esp | |
499 | ||
500 | /* We take pains to preserve all the regs. */ | |
501 | pushl %edx | |
502 | pushl %ecx | |
503 | pushl %eax | |
504 | ||
505 | /* paravirt.o is last in link, and that probe fn never returns */ | |
506 | pushl $__start_paravirtprobe | |
507 | 1: | |
508 | movl 0(%esp), %eax | |
509 | pushl (%eax) | |
510 | movl 8(%esp), %eax | |
511 | call *(%esp) | |
512 | popl %eax | |
513 | ||
514 | movl 4(%esp), %eax | |
515 | movl 8(%esp), %ecx | |
516 | movl 12(%esp), %edx | |
517 | ||
518 | addl $4, (%esp) | |
519 | jmp 1b | |
520 | #endif | |
521 | ||
1da177e4 LT |
522 | /* |
523 | * Real beginning of normal "text" segment | |
524 | */ | |
525 | ENTRY(stext) | |
526 | ENTRY(_stext) | |
527 | ||
528 | /* | |
529 | * BSS section | |
530 | */ | |
531 | .section ".bss.page_aligned","w" | |
532 | ENTRY(swapper_pg_dir) | |
533 | .fill 1024,4,0 | |
534 | ENTRY(empty_zero_page) | |
535 | .fill 4096,1,0 | |
536 | ||
537 | /* | |
538 | * This starts the data section. | |
539 | */ | |
540 | .data | |
f95d47ca JF |
541 | ENTRY(start_pda) |
542 | .long boot_pda | |
1da177e4 LT |
543 | |
544 | ENTRY(stack_start) | |
545 | .long init_thread_union+THREAD_SIZE | |
546 | .long __BOOT_DS | |
547 | ||
548 | ready: .byte 0 | |
549 | ||
ec5c0926 CE |
550 | early_recursion_flag: |
551 | .long 0 | |
552 | ||
1da177e4 LT |
553 | int_msg: |
554 | .asciz "Unknown interrupt or fault at EIP %p %p %p\n" | |
555 | ||
ec5c0926 CE |
556 | fault_msg: |
557 | .ascii "Int %d: CR2 %p err %p EIP %p CS %p flags %p\n" | |
558 | .asciz "Stack: %p %p %p %p %p %p %p %p\n" | |
559 | ||
1da177e4 LT |
560 | /* |
561 | * The IDT and GDT 'descriptors' are a strange 48-bit object | |
562 | * only used by the lidt and lgdt instructions. They are not | |
563 | * like usual segment descriptors - they consist of a 16-bit | |
564 | * segment size, and 32-bit linear address value: | |
565 | */ | |
566 | ||
567 | .globl boot_gdt_descr | |
568 | .globl idt_descr | |
1da177e4 LT |
569 | |
570 | ALIGN | |
571 | # early boot GDT descriptor (must use 1:1 address mapping) | |
572 | .word 0 # 32 bit align gdt_desc.address | |
573 | boot_gdt_descr: | |
574 | .word __BOOT_DS+7 | |
575 | .long boot_gdt_table - __PAGE_OFFSET | |
576 | ||
577 | .word 0 # 32-bit align idt_desc.address | |
578 | idt_descr: | |
579 | .word IDT_ENTRIES*8-1 # idt contains 256 entries | |
580 | .long idt_table | |
581 | ||
582 | # boot GDT descriptor (later on used by CPU#0): | |
583 | .word 0 # 32 bit align gdt_desc.address | |
f95d47ca | 584 | ENTRY(cpu_gdt_descr) |
1da177e4 LT |
585 | .word GDT_ENTRIES*8-1 |
586 | .long cpu_gdt_table | |
587 | ||
1da177e4 LT |
588 | /* |
589 | * The boot_gdt_table must mirror the equivalent in setup.S and is | |
590 | * used only for booting. | |
591 | */ | |
592 | .align L1_CACHE_BYTES | |
593 | ENTRY(boot_gdt_table) | |
594 | .fill GDT_ENTRY_BOOT_CS,8,0 | |
595 | .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */ | |
596 | .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */ | |
597 | ||
598 | /* | |
599 | * The Global Descriptor Table contains 28 quadwords, per-CPU. | |
600 | */ | |
4ef0652a | 601 | .align L1_CACHE_BYTES |
1da177e4 LT |
602 | ENTRY(cpu_gdt_table) |
603 | .quad 0x0000000000000000 /* NULL descriptor */ | |
604 | .quad 0x0000000000000000 /* 0x0b reserved */ | |
605 | .quad 0x0000000000000000 /* 0x13 reserved */ | |
606 | .quad 0x0000000000000000 /* 0x1b reserved */ | |
607 | .quad 0x0000000000000000 /* 0x20 unused */ | |
608 | .quad 0x0000000000000000 /* 0x28 unused */ | |
609 | .quad 0x0000000000000000 /* 0x33 TLS entry 1 */ | |
610 | .quad 0x0000000000000000 /* 0x3b TLS entry 2 */ | |
611 | .quad 0x0000000000000000 /* 0x43 TLS entry 3 */ | |
612 | .quad 0x0000000000000000 /* 0x4b reserved */ | |
613 | .quad 0x0000000000000000 /* 0x53 reserved */ | |
614 | .quad 0x0000000000000000 /* 0x5b reserved */ | |
615 | ||
616 | .quad 0x00cf9a000000ffff /* 0x60 kernel 4GB code at 0x00000000 */ | |
617 | .quad 0x00cf92000000ffff /* 0x68 kernel 4GB data at 0x00000000 */ | |
618 | .quad 0x00cffa000000ffff /* 0x73 user 4GB code at 0x00000000 */ | |
619 | .quad 0x00cff2000000ffff /* 0x7b user 4GB data at 0x00000000 */ | |
620 | ||
621 | .quad 0x0000000000000000 /* 0x80 TSS descriptor */ | |
622 | .quad 0x0000000000000000 /* 0x88 LDT descriptor */ | |
623 | ||
e6a9918c ZA |
624 | /* |
625 | * Segments used for calling PnP BIOS have byte granularity. | |
626 | * They code segments and data segments have fixed 64k limits, | |
627 | * the transfer segment sizes are set at run time. | |
628 | */ | |
629 | .quad 0x00409a000000ffff /* 0x90 32-bit code */ | |
630 | .quad 0x00009a000000ffff /* 0x98 16-bit code */ | |
631 | .quad 0x000092000000ffff /* 0xa0 16-bit data */ | |
5fe9fe3c ZA |
632 | .quad 0x0000920000000000 /* 0xa8 16-bit data */ |
633 | .quad 0x0000920000000000 /* 0xb0 16-bit data */ | |
99022c46 | 634 | |
1da177e4 LT |
635 | /* |
636 | * The APM segments have byte granularity and their bases | |
99022c46 | 637 | * are set at run time. All have 64k limits. |
1da177e4 | 638 | */ |
99022c46 ZA |
639 | .quad 0x00409a000000ffff /* 0xb8 APM CS code */ |
640 | .quad 0x00009a000000ffff /* 0xc0 APM CS 16 code (16 bit) */ | |
641 | .quad 0x004092000000ffff /* 0xc8 APM DS data */ | |
1da177e4 | 642 | |
be44d2aa | 643 | .quad 0x00c0920000000000 /* 0xd0 - ESPFIX SS */ |
f95d47ca | 644 | .quad 0x00cf92000000ffff /* 0xd8 - PDA */ |
1da177e4 LT |
645 | .quad 0x0000000000000000 /* 0xe0 - unused */ |
646 | .quad 0x0000000000000000 /* 0xe8 - unused */ | |
647 | .quad 0x0000000000000000 /* 0xf0 - unused */ | |
648 | .quad 0x0000000000000000 /* 0xf8 - GDT entry 31: double-fault TSS */ | |
649 |