[mirror_ubuntu-bionic-kernel.git] / arch / ia64 / sn / kernel / sn2 / ptc_deadlock.S

/* 
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
 */

#include <asm/types.h>
#include <asm/sn/shub_mmr.h>

#define DEADLOCKBIT	SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
#define WRITECOUNTMASK	SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK
#define ALIAS_OFFSET	8


	.global	sn2_ptc_deadlock_recovery_core
	.proc  	sn2_ptc_deadlock_recovery_core

sn2_ptc_deadlock_recovery_core:
	.regstk 6,0,0,0

	ptc0  	 = in0
	data0 	 = in1
	ptc1  	 = in2
	data1 	 = in3
	piowc 	 = in4
	zeroval  = in5
	piowcphy = r30
	psrsave  = r2
	scr1	 = r16
	scr2	 = r17
	mask	 = r18


	extr.u	piowcphy=piowc,0,61;;	// Convert piowc to uncached physical address
	dep	piowcphy=-1,piowcphy,63,1
	movl	mask=WRITECOUNTMASK
	mov	r8=r0

1:
	add	scr2=ALIAS_OFFSET,piowc	// Address of WRITE_STATUS alias register 
	;;
	ld8.acq	scr1=[scr2];;

5:	ld8.acq	scr1=[piowc];;		// Wait for PIOs to complete.
	hint	@pause
	and	scr2=scr1,mask;;	// mask of writecount bits
	cmp.ne	p6,p0=zeroval,scr2
(p6)	br.cond.sptk 5b
	

	////////////// BEGIN PHYSICAL MODE ////////////////////
	mov psrsave=psr			// Disable IC (no PMIs)
	rsm psr.i | psr.dt | psr.ic;;
	srlz.i;;

	st8.rel [ptc0]=data0		// Write PTC0 & wait for completion.

5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.
	hint	@pause
	and	scr2=scr1,mask;;	// mask of writecount bits
	cmp.ne	p6,p0=zeroval,scr2
(p6)	br.cond.sptk 5b;;

	tbit.nz	p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK
(p7)	cmp.ne p7,p0=r0,ptc1;;		// Test for non-null ptc1
	
(p7)	st8.rel [ptc1]=data1;;		// Now write PTC1.

5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.
	hint	@pause
	and	scr2=scr1,mask;;	// mask of writecount bits
	cmp.ne	p6,p0=zeroval,scr2
(p6)	br.cond.sptk 5b
	
	tbit.nz	p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK

	mov psr.l=psrsave;;		// Reenable IC
	srlz.i;;
	////////////// END   PHYSICAL MODE ////////////////////

(p8)	add	r8=1,r8
(p8)	br.cond.spnt 1b;;		// Repeat if DEADLOCK occurred.

	br.ret.sptk	rp
	.endp sn2_ptc_deadlock_recovery_core
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
470ceb05	6	* Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
1da177e4 LT	7	*/
1da177e4 LT	8
8e4641b3	9	#include <asm/types.h>
1da177e4 LT	10	#include <asm/sn/shub_mmr.h>
	11
	12	#define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
	13	#define WRITECOUNTMASK SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK
470ceb05	14	#define ALIAS_OFFSET 8
1da177e4 LT	15
	16
	17	.global sn2_ptc_deadlock_recovery_core
	18	.proc sn2_ptc_deadlock_recovery_core
	19
	20	sn2_ptc_deadlock_recovery_core:
	21	.regstk 6,0,0,0
	22
	23	ptc0 = in0
	24	data0 = in1
	25	ptc1 = in2
	26	data1 = in3
	27	piowc = in4
	28	zeroval = in5
	29	piowcphy = r30
	30	psrsave = r2
	31	scr1 = r16
	32	scr2 = r17
	33	mask = r18
	34
	35
	36	extr.u piowcphy=piowc,0,61;; // Convert piowc to uncached physical address
	37	dep piowcphy=-1,piowcphy,63,1
	38	movl mask=WRITECOUNTMASK
470ceb05	39	mov r8=r0
1da177e4 LT	40
	41	1:
	42	add scr2=ALIAS_OFFSET,piowc // Address of WRITE_STATUS alias register
470ceb05 JS	43	;;
470ceb05 JS	44	ld8.acq scr1=[scr2];;
1da177e4 LT	45
1da177e4 LT	46	5: ld8.acq scr1=[piowc];; // Wait for PIOs to complete.
470ceb05	47	hint @pause
1da177e4 LT	48	and scr2=scr1,mask;; // mask of writecount bits
	49	cmp.ne p6,p0=zeroval,scr2
	50	(p6) br.cond.sptk 5b
	51
	52
	53
	54	////////////// BEGIN PHYSICAL MODE ////////////////////
	55	mov psrsave=psr // Disable IC (no PMIs)
	56	rsm psr.i \| psr.dt \| psr.ic;;
	57	srlz.i;;
	58
	59	st8.rel [ptc0]=data0 // Write PTC0 & wait for completion.
	60
	61	5: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete.
470ceb05	62	hint @pause
1da177e4 LT	63	and scr2=scr1,mask;; // mask of writecount bits
	64	cmp.ne p6,p0=zeroval,scr2
	65	(p6) br.cond.sptk 5b;;
	66
	67	tbit.nz p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK
	68	(p7) cmp.ne p7,p0=r0,ptc1;; // Test for non-null ptc1
	69
	70	(p7) st8.rel [ptc1]=data1;; // Now write PTC1.
	71
	72	5: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete.
470ceb05	73	hint @pause
1da177e4 LT	74	and scr2=scr1,mask;; // mask of writecount bits
	75	cmp.ne p6,p0=zeroval,scr2
	76	(p6) br.cond.sptk 5b
	77
	78	tbit.nz p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK
	79
	80	mov psr.l=psrsave;; // Reenable IC
	81	srlz.i;;
	82	////////////// END PHYSICAL MODE ////////////////////
	83
470ceb05	84	(p8) add r8=1,r8
1da177e4 LT	85	(p8) br.cond.spnt 1b;; // Repeat if DEADLOCK occurred.
	86
	87	br.ret.sptk rp
	88	.endp sn2_ptc_deadlock_recovery_core