[mirror_ubuntu-zesty-kernel.git] / arch / ia64 / sn / pci / pcibr / pcibr_provider.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2001-2004, 2006 Silicon Graphics, Inc. All rights reserved.
 */

#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/export.h>
#include <asm/sn/addrs.h>
#include <asm/sn/geo.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/pic.h>
#include <asm/sn/sn2/sn_hwperf.h>
#include "xtalk/xwidgetdev.h"
#include "xtalk/hubdev.h"

int
sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp,
                      char **ssdt)
{
	struct ia64_sal_retval ret_stuff;
	u64 busnum;
	u64 segment;

	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	segment = soft->pbi_buscommon.bs_persist_segment;
	busnum = soft->pbi_buscommon.bs_persist_busnum;
	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
			busnum, (u64) device, (u64) resp, (u64)ia64_tpa(ssdt),
			0, 0);

	return (int)ret_stuff.v0;
}

int
sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
		       void *resp)
{
	struct ia64_sal_retval ret_stuff;
	u64 busnum;
	u64 segment;

	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	segment = soft->pbi_buscommon.bs_persist_segment;
	busnum = soft->pbi_buscommon.bs_persist_busnum;
	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
			segment, busnum, (u64) device, (u64) action,
			(u64) resp, 0, 0);

	return (int)ret_stuff.v0;
}

static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
{
	struct ia64_sal_retval ret_stuff;
	u64 busnum;
	int segment;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	segment = soft->pbi_buscommon.bs_persist_segment;
	busnum = soft->pbi_buscommon.bs_persist_busnum;
	SAL_CALL_NOLOCK(ret_stuff,
			(u64) SN_SAL_IOIF_ERROR_INTERRUPT,
			(u64) segment, (u64) busnum, 0, 0, 0, 0, 0);

	return (int)ret_stuff.v0;
}

u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus)
{
	long rc;
	u16 uninitialized_var(ioboard);		/* GCC be quiet */
	nasid_t nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);

	rc = ia64_sn_sysctl_ioboard_get(nasid, &ioboard);
	if (rc) {
		printk(KERN_WARNING "ia64_sn_sysctl_ioboard_get failed: %ld\n",
		       rc);
		return 0;
	}

	return ioboard;
}

/* 
 * PCI Bridge Error interrupt handler.  Gets invoked whenever a PCI 
 * bridge sends an error interrupt.
 */
static irqreturn_t
pcibr_error_intr_handler(int irq, void *arg)
{
	struct pcibus_info *soft = arg;

	if (sal_pcibr_error_interrupt(soft) < 0)
		panic("pcibr_error_intr_handler(): Fatal Bridge Error");

	return IRQ_HANDLED;
}

void *
pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
{
	int nasid, cnode, j;
	struct hubdev_info *hubdev_info;
	struct pcibus_info *soft;
	struct sn_flush_device_kernel *sn_flush_device_kernel;
	struct sn_flush_device_common *common;

	if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
		return NULL;
	}

	/*
	 * Allocate kernel bus soft and copy from prom.
	 */

	soft = kmemdup(prom_bussoft, sizeof(struct pcibus_info), GFP_KERNEL);
	if (!soft) {
		return NULL;
	}

	soft->pbi_buscommon.bs_base = (unsigned long)
		ioremap(REGION_OFFSET(soft->pbi_buscommon.bs_base),
			sizeof(struct pic));

	spin_lock_init(&soft->pbi_lock);

	/*
	 * register the bridge's error interrupt handler
	 */
	if (request_irq(SGI_PCIASIC_ERROR, pcibr_error_intr_handler,
			IRQF_SHARED, "PCIBR error", (void *)(soft))) {
		printk(KERN_WARNING
		       "pcibr cannot allocate interrupt for error handler\n");
	}
	irq_set_handler(SGI_PCIASIC_ERROR, handle_level_irq);
	sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);

	/* 
	 * Update the Bridge with the "kernel" pagesize 
	 */
	if (PAGE_SIZE < 16384) {
		pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
	} else {
		pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
	}

	nasid = NASID_GET(soft->pbi_buscommon.bs_base);
	cnode = nasid_to_cnodeid(nasid);
	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);

	if (hubdev_info->hdi_flush_nasid_list.widget_p) {
		sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
		    widget_p[(int)soft->pbi_buscommon.bs_xid];
		if (sn_flush_device_kernel) {
			for (j = 0; j < DEV_PER_WIDGET;
			     j++, sn_flush_device_kernel++) {
				common = sn_flush_device_kernel->common;
				if (common->sfdl_slot == -1)
					continue;
				if ((common->sfdl_persistent_segment ==
				     soft->pbi_buscommon.bs_persist_segment) &&
				     (common->sfdl_persistent_busnum ==
				     soft->pbi_buscommon.bs_persist_busnum))
					common->sfdl_pcibus_info =
					    soft;
			}
		}
	}

	/* Setup the PMU ATE map */
	soft->pbi_int_ate_resource.lowest_free_index = 0;
	soft->pbi_int_ate_resource.ate =
	    kzalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);

	if (!soft->pbi_int_ate_resource.ate) {
		kfree(soft);
		return NULL;
	}

	return soft;
}

void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
{
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;
	int bit = sn_irq_info->irq_int_bit;

	if (! sn_irq_info->irq_bridge)
		return;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (pcidev_info) {
		pcibus_info =
		    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
		    pdi_pcibus_info;
		pcireg_force_intr_set(pcibus_info, bit);
	}
}

void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
{
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;
	int bit = sn_irq_info->irq_int_bit;
	u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (pcidev_info) {
		pcibus_info =
		    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
		    pdi_pcibus_info;

		/* Disable the device's IRQ   */
		pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));

		/* Change the device's IRQ    */
		pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);

		/* Re-enable the device's IRQ */
		pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));

		pcibr_force_interrupt(sn_irq_info);
	}
}

/*
 * Provider entries for PIC/CP
 */

struct sn_pcibus_provider pcibr_provider = {
	.dma_map = pcibr_dma_map,
	.dma_map_consistent = pcibr_dma_map_consistent,
	.dma_unmap = pcibr_dma_unmap,
	.bus_fixup = pcibr_bus_fixup,
	.force_interrupt = pcibr_force_interrupt,
	.target_interrupt = pcibr_target_interrupt
};

int
pcibr_init_provider(void)
{
	sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
	sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;

	return 0;
}

EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);
EXPORT_SYMBOL_GPL(sn_ioboard_to_pci_bus);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
8ea6091f	6	* Copyright (C) 2001-2004, 2006 Silicon Graphics, Inc. All rights reserved.
1da177e4 LT	7	*/
1da177e4 LT	8
1da177e4	9	#include <linux/interrupt.h>
c13cf371	10	#include <linux/types.h>
5a0e3ad6	11	#include <linux/slab.h>
1da177e4	12	#include <linux/pci.h>
bd3ff194	13	#include <linux/export.h>
c13cf371	14	#include <asm/sn/addrs.h>
1da177e4	15	#include <asm/sn/geo.h>
c13cf371	16	#include <asm/sn/pcibr_provider.h>
9b08ebd1 MM	17	#include <asm/sn/pcibus_provider_defs.h>
9b08ebd1 MM	18	#include <asm/sn/pcidev.h>
c13cf371	19	#include <asm/sn/sn_sal.h>
1ee27a4e	20	#include <asm/sn/pic.h>
5390970d	21	#include <asm/sn/sn2/sn_hwperf.h>
c13cf371 PB	22	#include "xtalk/xwidgetdev.h"
c13cf371 PB	23	#include "xtalk/hubdev.h"
1da177e4	24
6f354b01	25	int
6f09a925 JK	26	sal_pcibr_slot_enable(struct pcibus_info soft, int device, void resp,
6f09a925 JK	27	char **ssdt)
6f354b01 PB	28	{
6f354b01 PB	29	struct ia64_sal_retval ret_stuff;
53493dcf	30	u64 busnum;
ac354a89	31	u64 segment;
6f354b01 PB	32
	33	ret_stuff.status = 0;
	34	ret_stuff.v0 = 0;
	35
ac354a89	36	segment = soft->pbi_buscommon.bs_persist_segment;
6f354b01	37	busnum = soft->pbi_buscommon.bs_persist_busnum;
ac354a89	38	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
6f09a925 JK	39	busnum, (u64) device, (u64) resp, (u64)ia64_tpa(ssdt),
6f09a925 JK	40	0, 0);
6f354b01 PB	41
	42	return (int)ret_stuff.v0;
	43	}
	44
	45	int
	46	sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
	47	void *resp)
	48	{
	49	struct ia64_sal_retval ret_stuff;
53493dcf	50	u64 busnum;
ac354a89	51	u64 segment;
6f354b01 PB	52
	53	ret_stuff.status = 0;
	54	ret_stuff.v0 = 0;
	55
ac354a89	56	segment = soft->pbi_buscommon.bs_persist_segment;
6f354b01 PB	57	busnum = soft->pbi_buscommon.bs_persist_busnum;
6f354b01 PB	58	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
ac354a89 MH	59	segment, busnum, (u64) device, (u64) action,
ac354a89 MH	60	(u64) resp, 0, 0);
6f354b01 PB	61
	62	return (int)ret_stuff.v0;
	63	}
	64
1da177e4 LT	65	static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
	66	{
	67	struct ia64_sal_retval ret_stuff;
53493dcf	68	u64 busnum;
1da177e4 LT	69	int segment;
	70	ret_stuff.status = 0;
	71	ret_stuff.v0 = 0;
	72
674c6479	73	segment = soft->pbi_buscommon.bs_persist_segment;
1da177e4 LT	74	busnum = soft->pbi_buscommon.bs_persist_busnum;
	75	SAL_CALL_NOLOCK(ret_stuff,
	76	(u64) SN_SAL_IOIF_ERROR_INTERRUPT,
	77	(u64) segment, (u64) busnum, 0, 0, 0, 0, 0);
	78
	79	return (int)ret_stuff.v0;
	80	}
	81
f90aa8c4 PB	82	u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus)
f90aa8c4 PB	83	{
e088a4ad	84	long rc;
256a7e09	85	u16 uninitialized_var(ioboard); /* GCC be quiet */
f90aa8c4 PB	86	nasid_t nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);
	87
	88	rc = ia64_sn_sysctl_ioboard_get(nasid, &ioboard);
	89	if (rc) {
	90	printk(KERN_WARNING "ia64_sn_sysctl_ioboard_get failed: %ld\n",
	91	rc);
	92	return 0;
	93	}
	94
	95	return ioboard;
	96	}
	97
1da177e4 LT	98	/*
	99	* PCI Bridge Error interrupt handler. Gets invoked whenever a PCI
	100	* bridge sends an error interrupt.
	101	*/
	102	static irqreturn_t
a23b7cb9	103	pcibr_error_intr_handler(int irq, void *arg)
1da177e4	104	{
15aafa2f	105	struct pcibus_info *soft = arg;
1da177e4	106
15aafa2f	107	if (sal_pcibr_error_interrupt(soft) < 0)
1da177e4	108	panic("pcibr_error_intr_handler(): Fatal Bridge Error");
15aafa2f	109
1da177e4 LT	110	return IRQ_HANDLED;
	111	}
	112
	113	void *
7c2a6c62	114	pcibr_bus_fixup(struct pcibus_bussoft prom_bussoft, struct pci_controller controller)
1da177e4 LT	115	{
	116	int nasid, cnode, j;
	117	struct hubdev_info *hubdev_info;
	118	struct pcibus_info *soft;
6d6e4200 PB	119	struct sn_flush_device_kernel *sn_flush_device_kernel;
6d6e4200 PB	120	struct sn_flush_device_common *common;
1da177e4 LT	121
	122	if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
	123	return NULL;
	124	}
	125
	126	/*
	127	* Allocate kernel bus soft and copy from prom.
	128	*/
	129
a4b1d1b3	130	soft = kmemdup(prom_bussoft, sizeof(struct pcibus_info), GFP_KERNEL);
1da177e4 LT	131	if (!soft) {
	132	return NULL;
	133	}
	134
1ee27a4e JS	135	soft->pbi_buscommon.bs_base = (unsigned long)
	136	ioremap(REGION_OFFSET(soft->pbi_buscommon.bs_base),
	137	sizeof(struct pic));
1da177e4 LT	138
	139	spin_lock_init(&soft->pbi_lock);
	140
	141	/*
	142	* register the bridge's error interrupt handler
	143	*/
a23b7cb9	144	if (request_irq(SGI_PCIASIC_ERROR, pcibr_error_intr_handler,
121a4226	145	IRQF_SHARED, "PCIBR error", (void *)(soft))) {
1da177e4 LT	146	printk(KERN_WARNING
	147	"pcibr cannot allocate interrupt for error handler\n");
	148	}
48e30fa0	149	irq_set_handler(SGI_PCIASIC_ERROR, handle_level_irq);
6e9de181	150	sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
1da177e4 LT	151
	152	/*
	153	* Update the Bridge with the "kernel" pagesize
	154	*/
	155	if (PAGE_SIZE < 16384) {
	156	pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
	157	} else {
	158	pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
	159	}
	160
	161	nasid = NASID_GET(soft->pbi_buscommon.bs_base);
	162	cnode = nasid_to_cnodeid(nasid);
	163	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
	164
	165	if (hubdev_info->hdi_flush_nasid_list.widget_p) {
6d6e4200	166	sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
1da177e4	167	widget_p[(int)soft->pbi_buscommon.bs_xid];
6d6e4200	168	if (sn_flush_device_kernel) {
1da177e4	169	for (j = 0; j < DEV_PER_WIDGET;
6d6e4200 PB	170	j++, sn_flush_device_kernel++) {
	171	common = sn_flush_device_kernel->common;
	172	if (common->sfdl_slot == -1)
1da177e4	173	continue;
6d6e4200	174	if ((common->sfdl_persistent_segment ==
674c6479	175	soft->pbi_buscommon.bs_persist_segment) &&
6d6e4200	176	(common->sfdl_persistent_busnum ==
674c6479	177	soft->pbi_buscommon.bs_persist_busnum))
6d6e4200	178	common->sfdl_pcibus_info =
1da177e4 LT	179	soft;
	180	}
	181	}
	182	}
	183
	184	/* Setup the PMU ATE map */
	185	soft->pbi_int_ate_resource.lowest_free_index = 0;
	186	soft->pbi_int_ate_resource.ate =
8ed9b2c7 JS	187	kzalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);
	188
	189	if (!soft->pbi_int_ate_resource.ate) {
	190	kfree(soft);
	191	return NULL;
	192	}
1da177e4 LT	193
	194	return soft;
	195	}
	196
	197	void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
	198	{
	199	struct pcidev_info *pcidev_info;
	200	struct pcibus_info *pcibus_info;
	201	int bit = sn_irq_info->irq_int_bit;
	202
735e60f4 MM	203	if (! sn_irq_info->irq_bridge)
	204	return;
	205
1da177e4 LT	206	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	207	if (pcidev_info) {
	208	pcibus_info =
	209	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	210	pdi_pcibus_info;
	211	pcireg_force_intr_set(pcibus_info, bit);
	212	}
	213	}
	214
8409668b	215	void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
1da177e4 LT	216	{
	217	struct pcidev_info *pcidev_info;
	218	struct pcibus_info *pcibus_info;
	219	int bit = sn_irq_info->irq_int_bit;
53493dcf	220	u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
1da177e4 LT	221
	222	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	223	if (pcidev_info) {
	224	pcibus_info =
	225	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	226	pdi_pcibus_info;
	227
	228	/* Disable the device's IRQ */
6fb93a92	229	pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));
1da177e4 LT	230
	231	/* Change the device's IRQ */
	232	pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);
	233
	234	/* Re-enable the device's IRQ */
6fb93a92	235	pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));
1da177e4 LT	236
	237	pcibr_force_interrupt(sn_irq_info);
	238	}
	239	}
e955d825 MM	240
	241	/*
	242	* Provider entries for PIC/CP
	243	*/
	244
	245	struct sn_pcibus_provider pcibr_provider = {
	246	.dma_map = pcibr_dma_map,
	247	.dma_map_consistent = pcibr_dma_map_consistent,
	248	.dma_unmap = pcibr_dma_unmap,
	249	.bus_fixup = pcibr_bus_fixup,
8409668b MM	250	.force_interrupt = pcibr_force_interrupt,
8409668b MM	251	.target_interrupt = pcibr_target_interrupt
e955d825 MM	252	};
	253
	254	int
	255	pcibr_init_provider(void)
	256	{
	257	sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
	258	sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;
	259
	260	return 0;
	261	}
6f354b01 PB	262
	263	EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
	264	EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);
f90aa8c4	265	EXPORT_SYMBOL_GPL(sn_ioboard_to_pci_bus);