]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * BRIEF MODULE DESCRIPTION | |
3 | * Au1000 interrupt routines. | |
4 | * | |
5 | * Copyright 2001 MontaVista Software Inc. | |
6 | * Author: MontaVista Software, Inc. | |
7 | * ppopov@mvista.com or source@mvista.com | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License along | |
26 | * with this program; if not, write to the Free Software Foundation, Inc., | |
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
28 | */ | |
29 | #include <linux/config.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/irq.h> | |
33 | #include <linux/kernel_stat.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/signal.h> | |
36 | #include <linux/sched.h> | |
37 | #include <linux/types.h> | |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/timex.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/random.h> | |
43 | #include <linux/delay.h> | |
44 | #include <linux/bitops.h> | |
45 | ||
46 | #include <asm/bootinfo.h> | |
47 | #include <asm/io.h> | |
48 | #include <asm/mipsregs.h> | |
49 | #include <asm/system.h> | |
50 | #include <asm/mach-au1x00/au1000.h> | |
51 | #ifdef CONFIG_MIPS_PB1000 | |
52 | #include <asm/mach-pb1x00/pb1000.h> | |
53 | #endif | |
54 | ||
55 | #undef DEBUG_IRQ | |
56 | #ifdef DEBUG_IRQ | |
57 | /* note: prints function name for you */ | |
58 | #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) | |
59 | #else | |
60 | #define DPRINTK(fmt, args...) | |
61 | #endif | |
62 | ||
63 | #define EXT_INTC0_REQ0 2 /* IP 2 */ | |
64 | #define EXT_INTC0_REQ1 3 /* IP 3 */ | |
65 | #define EXT_INTC1_REQ0 4 /* IP 4 */ | |
66 | #define EXT_INTC1_REQ1 5 /* IP 5 */ | |
67 | #define MIPS_TIMER_IP 7 /* IP 7 */ | |
68 | ||
69 | extern asmlinkage void au1000_IRQ(void); | |
70 | extern void set_debug_traps(void); | |
71 | extern irq_cpustat_t irq_stat [NR_CPUS]; | |
72 | ||
73 | static void setup_local_irq(unsigned int irq, int type, int int_req); | |
74 | static unsigned int startup_irq(unsigned int irq); | |
75 | static void end_irq(unsigned int irq_nr); | |
76 | static inline void mask_and_ack_level_irq(unsigned int irq_nr); | |
77 | static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); | |
78 | static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr); | |
79 | static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr); | |
80 | inline void local_enable_irq(unsigned int irq_nr); | |
81 | inline void local_disable_irq(unsigned int irq_nr); | |
82 | ||
83 | void (*board_init_irq)(void); | |
84 | ||
85 | #ifdef CONFIG_PM | |
86 | extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs); | |
87 | #endif | |
88 | ||
89 | static DEFINE_SPINLOCK(irq_lock); | |
90 | ||
91 | ||
92 | static unsigned int startup_irq(unsigned int irq_nr) | |
93 | { | |
94 | local_enable_irq(irq_nr); | |
95 | return 0; | |
96 | } | |
97 | ||
98 | ||
99 | static void shutdown_irq(unsigned int irq_nr) | |
100 | { | |
101 | local_disable_irq(irq_nr); | |
102 | return; | |
103 | } | |
104 | ||
105 | ||
106 | inline void local_enable_irq(unsigned int irq_nr) | |
107 | { | |
108 | if (irq_nr > AU1000_LAST_INTC0_INT) { | |
109 | au_writel(1<<(irq_nr-32), IC1_MASKSET); | |
110 | au_writel(1<<(irq_nr-32), IC1_WAKESET); | |
111 | } | |
112 | else { | |
113 | au_writel(1<<irq_nr, IC0_MASKSET); | |
114 | au_writel(1<<irq_nr, IC0_WAKESET); | |
115 | } | |
116 | au_sync(); | |
117 | } | |
118 | ||
119 | ||
120 | inline void local_disable_irq(unsigned int irq_nr) | |
121 | { | |
122 | if (irq_nr > AU1000_LAST_INTC0_INT) { | |
123 | au_writel(1<<(irq_nr-32), IC1_MASKCLR); | |
124 | au_writel(1<<(irq_nr-32), IC1_WAKECLR); | |
125 | } | |
126 | else { | |
127 | au_writel(1<<irq_nr, IC0_MASKCLR); | |
128 | au_writel(1<<irq_nr, IC0_WAKECLR); | |
129 | } | |
130 | au_sync(); | |
131 | } | |
132 | ||
133 | ||
134 | static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) | |
135 | { | |
136 | if (irq_nr > AU1000_LAST_INTC0_INT) { | |
137 | au_writel(1<<(irq_nr-32), IC1_RISINGCLR); | |
138 | au_writel(1<<(irq_nr-32), IC1_MASKCLR); | |
139 | } | |
140 | else { | |
141 | au_writel(1<<irq_nr, IC0_RISINGCLR); | |
142 | au_writel(1<<irq_nr, IC0_MASKCLR); | |
143 | } | |
144 | au_sync(); | |
145 | } | |
146 | ||
147 | ||
148 | static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) | |
149 | { | |
150 | if (irq_nr > AU1000_LAST_INTC0_INT) { | |
151 | au_writel(1<<(irq_nr-32), IC1_FALLINGCLR); | |
152 | au_writel(1<<(irq_nr-32), IC1_MASKCLR); | |
153 | } | |
154 | else { | |
155 | au_writel(1<<irq_nr, IC0_FALLINGCLR); | |
156 | au_writel(1<<irq_nr, IC0_MASKCLR); | |
157 | } | |
158 | au_sync(); | |
159 | } | |
160 | ||
161 | ||
162 | static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) | |
163 | { | |
164 | /* This may assume that we don't get interrupts from | |
165 | * both edges at once, or if we do, that we don't care. | |
166 | */ | |
167 | if (irq_nr > AU1000_LAST_INTC0_INT) { | |
168 | au_writel(1<<(irq_nr-32), IC1_FALLINGCLR); | |
169 | au_writel(1<<(irq_nr-32), IC1_RISINGCLR); | |
170 | au_writel(1<<(irq_nr-32), IC1_MASKCLR); | |
171 | } | |
172 | else { | |
173 | au_writel(1<<irq_nr, IC0_FALLINGCLR); | |
174 | au_writel(1<<irq_nr, IC0_RISINGCLR); | |
175 | au_writel(1<<irq_nr, IC0_MASKCLR); | |
176 | } | |
177 | au_sync(); | |
178 | } | |
179 | ||
180 | ||
181 | static inline void mask_and_ack_level_irq(unsigned int irq_nr) | |
182 | { | |
183 | ||
184 | local_disable_irq(irq_nr); | |
185 | au_sync(); | |
186 | #if defined(CONFIG_MIPS_PB1000) | |
187 | if (irq_nr == AU1000_GPIO_15) { | |
188 | au_writel(0x8000, PB1000_MDR); /* ack int */ | |
189 | au_sync(); | |
190 | } | |
191 | #endif | |
192 | return; | |
193 | } | |
194 | ||
195 | ||
196 | static void end_irq(unsigned int irq_nr) | |
197 | { | |
198 | if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { | |
199 | local_enable_irq(irq_nr); | |
200 | } | |
201 | #if defined(CONFIG_MIPS_PB1000) | |
202 | if (irq_nr == AU1000_GPIO_15) { | |
203 | au_writel(0x4000, PB1000_MDR); /* enable int */ | |
204 | au_sync(); | |
205 | } | |
206 | #endif | |
207 | } | |
208 | ||
209 | unsigned long save_local_and_disable(int controller) | |
210 | { | |
211 | int i; | |
212 | unsigned long flags, mask; | |
213 | ||
214 | spin_lock_irqsave(&irq_lock, flags); | |
215 | if (controller) { | |
216 | mask = au_readl(IC1_MASKSET); | |
217 | for (i=32; i<64; i++) { | |
218 | local_disable_irq(i); | |
219 | } | |
220 | } | |
221 | else { | |
222 | mask = au_readl(IC0_MASKSET); | |
223 | for (i=0; i<32; i++) { | |
224 | local_disable_irq(i); | |
225 | } | |
226 | } | |
227 | spin_unlock_irqrestore(&irq_lock, flags); | |
228 | ||
229 | return mask; | |
230 | } | |
231 | ||
232 | void restore_local_and_enable(int controller, unsigned long mask) | |
233 | { | |
234 | int i; | |
235 | unsigned long flags, new_mask; | |
236 | ||
237 | spin_lock_irqsave(&irq_lock, flags); | |
238 | for (i=0; i<32; i++) { | |
239 | if (mask & (1<<i)) { | |
240 | if (controller) | |
241 | local_enable_irq(i+32); | |
242 | else | |
243 | local_enable_irq(i); | |
244 | } | |
245 | } | |
246 | if (controller) | |
247 | new_mask = au_readl(IC1_MASKSET); | |
248 | else | |
249 | new_mask = au_readl(IC0_MASKSET); | |
250 | ||
251 | spin_unlock_irqrestore(&irq_lock, flags); | |
252 | } | |
253 | ||
254 | ||
255 | static struct hw_interrupt_type rise_edge_irq_type = { | |
256 | "Au1000 Rise Edge", | |
257 | startup_irq, | |
258 | shutdown_irq, | |
259 | local_enable_irq, | |
260 | local_disable_irq, | |
261 | mask_and_ack_rise_edge_irq, | |
262 | end_irq, | |
263 | NULL | |
264 | }; | |
265 | ||
266 | static struct hw_interrupt_type fall_edge_irq_type = { | |
267 | "Au1000 Fall Edge", | |
268 | startup_irq, | |
269 | shutdown_irq, | |
270 | local_enable_irq, | |
271 | local_disable_irq, | |
272 | mask_and_ack_fall_edge_irq, | |
273 | end_irq, | |
274 | NULL | |
275 | }; | |
276 | ||
277 | static struct hw_interrupt_type either_edge_irq_type = { | |
278 | "Au1000 Rise or Fall Edge", | |
279 | startup_irq, | |
280 | shutdown_irq, | |
281 | local_enable_irq, | |
282 | local_disable_irq, | |
283 | mask_and_ack_either_edge_irq, | |
284 | end_irq, | |
285 | NULL | |
286 | }; | |
287 | ||
288 | static struct hw_interrupt_type level_irq_type = { | |
289 | "Au1000 Level", | |
290 | startup_irq, | |
291 | shutdown_irq, | |
292 | local_enable_irq, | |
293 | local_disable_irq, | |
294 | mask_and_ack_level_irq, | |
295 | end_irq, | |
296 | NULL | |
297 | }; | |
298 | ||
299 | #ifdef CONFIG_PM | |
300 | void startup_match20_interrupt(void) | |
301 | { | |
302 | local_enable_irq(AU1000_TOY_MATCH2_INT); | |
303 | } | |
304 | #endif | |
305 | ||
306 | static void setup_local_irq(unsigned int irq_nr, int type, int int_req) | |
307 | { | |
308 | if (irq_nr > AU1000_MAX_INTR) return; | |
309 | /* Config2[n], Config1[n], Config0[n] */ | |
310 | if (irq_nr > AU1000_LAST_INTC0_INT) { | |
311 | switch (type) { | |
312 | case INTC_INT_RISE_EDGE: /* 0:0:1 */ | |
313 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | |
314 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); | |
315 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); | |
316 | irq_desc[irq_nr].handler = &rise_edge_irq_type; | |
317 | break; | |
318 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ | |
319 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | |
320 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); | |
321 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | |
322 | irq_desc[irq_nr].handler = &fall_edge_irq_type; | |
323 | break; | |
324 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ | |
325 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | |
326 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); | |
327 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); | |
328 | irq_desc[irq_nr].handler = &either_edge_irq_type; | |
329 | break; | |
330 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ | |
331 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); | |
332 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); | |
333 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); | |
334 | irq_desc[irq_nr].handler = &level_irq_type; | |
335 | break; | |
336 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ | |
337 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); | |
338 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); | |
339 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | |
340 | irq_desc[irq_nr].handler = &level_irq_type; | |
341 | break; | |
342 | case INTC_INT_DISABLED: /* 0:0:0 */ | |
343 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | |
344 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); | |
345 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | |
346 | break; | |
347 | default: /* disable the interrupt */ | |
348 | printk("unexpected int type %d (irq %d)\n", type, irq_nr); | |
349 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | |
350 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); | |
351 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | |
352 | return; | |
353 | } | |
354 | if (int_req) /* assign to interrupt request 1 */ | |
355 | au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR); | |
356 | else /* assign to interrupt request 0 */ | |
357 | au_writel(1<<(irq_nr-32), IC1_ASSIGNSET); | |
358 | au_writel(1<<(irq_nr-32), IC1_SRCSET); | |
359 | au_writel(1<<(irq_nr-32), IC1_MASKCLR); | |
360 | au_writel(1<<(irq_nr-32), IC1_WAKECLR); | |
361 | } | |
362 | else { | |
363 | switch (type) { | |
364 | case INTC_INT_RISE_EDGE: /* 0:0:1 */ | |
365 | au_writel(1<<irq_nr, IC0_CFG2CLR); | |
366 | au_writel(1<<irq_nr, IC0_CFG1CLR); | |
367 | au_writel(1<<irq_nr, IC0_CFG0SET); | |
368 | irq_desc[irq_nr].handler = &rise_edge_irq_type; | |
369 | break; | |
370 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ | |
371 | au_writel(1<<irq_nr, IC0_CFG2CLR); | |
372 | au_writel(1<<irq_nr, IC0_CFG1SET); | |
373 | au_writel(1<<irq_nr, IC0_CFG0CLR); | |
374 | irq_desc[irq_nr].handler = &fall_edge_irq_type; | |
375 | break; | |
376 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ | |
377 | au_writel(1<<irq_nr, IC0_CFG2CLR); | |
378 | au_writel(1<<irq_nr, IC0_CFG1SET); | |
379 | au_writel(1<<irq_nr, IC0_CFG0SET); | |
380 | irq_desc[irq_nr].handler = &either_edge_irq_type; | |
381 | break; | |
382 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ | |
383 | au_writel(1<<irq_nr, IC0_CFG2SET); | |
384 | au_writel(1<<irq_nr, IC0_CFG1CLR); | |
385 | au_writel(1<<irq_nr, IC0_CFG0SET); | |
386 | irq_desc[irq_nr].handler = &level_irq_type; | |
387 | break; | |
388 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ | |
389 | au_writel(1<<irq_nr, IC0_CFG2SET); | |
390 | au_writel(1<<irq_nr, IC0_CFG1SET); | |
391 | au_writel(1<<irq_nr, IC0_CFG0CLR); | |
392 | irq_desc[irq_nr].handler = &level_irq_type; | |
393 | break; | |
394 | case INTC_INT_DISABLED: /* 0:0:0 */ | |
395 | au_writel(1<<irq_nr, IC0_CFG0CLR); | |
396 | au_writel(1<<irq_nr, IC0_CFG1CLR); | |
397 | au_writel(1<<irq_nr, IC0_CFG2CLR); | |
398 | break; | |
399 | default: /* disable the interrupt */ | |
400 | printk("unexpected int type %d (irq %d)\n", type, irq_nr); | |
401 | au_writel(1<<irq_nr, IC0_CFG0CLR); | |
402 | au_writel(1<<irq_nr, IC0_CFG1CLR); | |
403 | au_writel(1<<irq_nr, IC0_CFG2CLR); | |
404 | return; | |
405 | } | |
406 | if (int_req) /* assign to interrupt request 1 */ | |
407 | au_writel(1<<irq_nr, IC0_ASSIGNCLR); | |
408 | else /* assign to interrupt request 0 */ | |
409 | au_writel(1<<irq_nr, IC0_ASSIGNSET); | |
410 | au_writel(1<<irq_nr, IC0_SRCSET); | |
411 | au_writel(1<<irq_nr, IC0_MASKCLR); | |
412 | au_writel(1<<irq_nr, IC0_WAKECLR); | |
413 | } | |
414 | au_sync(); | |
415 | } | |
416 | ||
417 | ||
418 | void __init arch_init_irq(void) | |
419 | { | |
420 | int i; | |
421 | unsigned long cp0_status; | |
422 | au1xxx_irq_map_t *imp; | |
423 | extern au1xxx_irq_map_t au1xxx_irq_map[]; | |
424 | extern au1xxx_irq_map_t au1xxx_ic0_map[]; | |
425 | extern int au1xxx_nr_irqs; | |
426 | extern int au1xxx_ic0_nr_irqs; | |
427 | ||
428 | cp0_status = read_c0_status(); | |
429 | memset(irq_desc, 0, sizeof(irq_desc)); | |
430 | set_except_vector(0, au1000_IRQ); | |
431 | ||
432 | /* Initialize interrupt controllers to a safe state. | |
433 | */ | |
434 | au_writel(0xffffffff, IC0_CFG0CLR); | |
435 | au_writel(0xffffffff, IC0_CFG1CLR); | |
436 | au_writel(0xffffffff, IC0_CFG2CLR); | |
437 | au_writel(0xffffffff, IC0_MASKCLR); | |
438 | au_writel(0xffffffff, IC0_ASSIGNSET); | |
439 | au_writel(0xffffffff, IC0_WAKECLR); | |
440 | au_writel(0xffffffff, IC0_SRCSET); | |
441 | au_writel(0xffffffff, IC0_FALLINGCLR); | |
442 | au_writel(0xffffffff, IC0_RISINGCLR); | |
443 | au_writel(0x00000000, IC0_TESTBIT); | |
444 | ||
445 | au_writel(0xffffffff, IC1_CFG0CLR); | |
446 | au_writel(0xffffffff, IC1_CFG1CLR); | |
447 | au_writel(0xffffffff, IC1_CFG2CLR); | |
448 | au_writel(0xffffffff, IC1_MASKCLR); | |
449 | au_writel(0xffffffff, IC1_ASSIGNSET); | |
450 | au_writel(0xffffffff, IC1_WAKECLR); | |
451 | au_writel(0xffffffff, IC1_SRCSET); | |
452 | au_writel(0xffffffff, IC1_FALLINGCLR); | |
453 | au_writel(0xffffffff, IC1_RISINGCLR); | |
454 | au_writel(0x00000000, IC1_TESTBIT); | |
455 | ||
456 | /* Initialize IC0, which is fixed per processor. | |
457 | */ | |
458 | imp = au1xxx_ic0_map; | |
459 | for (i=0; i<au1xxx_ic0_nr_irqs; i++) { | |
460 | setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); | |
461 | imp++; | |
462 | } | |
463 | ||
464 | /* Now set up the irq mapping for the board. | |
465 | */ | |
466 | imp = au1xxx_irq_map; | |
467 | for (i=0; i<au1xxx_nr_irqs; i++) { | |
468 | setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); | |
469 | imp++; | |
470 | } | |
471 | ||
472 | set_c0_status(ALLINTS); | |
473 | ||
474 | /* Board specific IRQ initialization. | |
475 | */ | |
476 | if (board_init_irq) | |
477 | (*board_init_irq)(); | |
478 | } | |
479 | ||
480 | ||
481 | /* | |
482 | * Interrupts are nested. Even if an interrupt handler is registered | |
483 | * as "fast", we might get another interrupt before we return from | |
484 | * intcX_reqX_irqdispatch(). | |
485 | */ | |
486 | ||
487 | void intc0_req0_irqdispatch(struct pt_regs *regs) | |
488 | { | |
489 | int irq = 0; | |
490 | static unsigned long intc0_req0 = 0; | |
491 | ||
492 | intc0_req0 |= au_readl(IC0_REQ0INT); | |
493 | ||
494 | if (!intc0_req0) return; | |
495 | ||
496 | /* | |
497 | * Because of the tight timing of SETUP token to reply | |
498 | * transactions, the USB devices-side packet complete | |
499 | * interrupt needs the highest priority. | |
500 | */ | |
501 | if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) { | |
502 | intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT); | |
503 | do_IRQ(AU1000_USB_DEV_REQ_INT, regs); | |
504 | return; | |
505 | } | |
506 | ||
507 | irq = au_ffs(intc0_req0) - 1; | |
508 | intc0_req0 &= ~(1<<irq); | |
509 | do_IRQ(irq, regs); | |
510 | } | |
511 | ||
512 | ||
513 | void intc0_req1_irqdispatch(struct pt_regs *regs) | |
514 | { | |
515 | int irq = 0; | |
516 | static unsigned long intc0_req1 = 0; | |
517 | ||
518 | intc0_req1 |= au_readl(IC0_REQ1INT); | |
519 | ||
520 | if (!intc0_req1) return; | |
521 | ||
522 | irq = au_ffs(intc0_req1) - 1; | |
523 | intc0_req1 &= ~(1<<irq); | |
524 | #ifdef CONFIG_PM | |
525 | if (irq == AU1000_TOY_MATCH2_INT) { | |
526 | mask_and_ack_rise_edge_irq(irq); | |
527 | counter0_irq(irq, NULL, regs); | |
528 | local_enable_irq(irq); | |
529 | } | |
530 | else | |
531 | #endif | |
532 | { | |
533 | do_IRQ(irq, regs); | |
534 | } | |
535 | } | |
536 | ||
537 | ||
538 | /* | |
539 | * Interrupt Controller 1: | |
540 | * interrupts 32 - 63 | |
541 | */ | |
542 | void intc1_req0_irqdispatch(struct pt_regs *regs) | |
543 | { | |
544 | int irq = 0; | |
545 | static unsigned long intc1_req0 = 0; | |
546 | ||
547 | intc1_req0 |= au_readl(IC1_REQ0INT); | |
548 | ||
549 | if (!intc1_req0) return; | |
550 | ||
551 | irq = au_ffs(intc1_req0) - 1; | |
552 | intc1_req0 &= ~(1<<irq); | |
553 | irq += 32; | |
554 | do_IRQ(irq, regs); | |
555 | } | |
556 | ||
557 | ||
558 | void intc1_req1_irqdispatch(struct pt_regs *regs) | |
559 | { | |
560 | int irq = 0; | |
561 | static unsigned long intc1_req1 = 0; | |
562 | ||
563 | intc1_req1 |= au_readl(IC1_REQ1INT); | |
564 | ||
565 | if (!intc1_req1) return; | |
566 | ||
567 | irq = au_ffs(intc1_req1) - 1; | |
568 | intc1_req1 &= ~(1<<irq); | |
569 | irq += 32; | |
570 | do_IRQ(irq, regs); | |
571 | } | |
572 | ||
573 | #ifdef CONFIG_PM | |
574 | ||
575 | /* Save/restore the interrupt controller state. | |
576 | * Called from the save/restore core registers as part of the | |
577 | * au_sleep function in power.c.....maybe I should just pm_register() | |
578 | * them instead? | |
579 | */ | |
580 | static uint sleep_intctl_config0[2]; | |
581 | static uint sleep_intctl_config1[2]; | |
582 | static uint sleep_intctl_config2[2]; | |
583 | static uint sleep_intctl_src[2]; | |
584 | static uint sleep_intctl_assign[2]; | |
585 | static uint sleep_intctl_wake[2]; | |
586 | static uint sleep_intctl_mask[2]; | |
587 | ||
588 | void | |
589 | save_au1xxx_intctl(void) | |
590 | { | |
591 | sleep_intctl_config0[0] = au_readl(IC0_CFG0RD); | |
592 | sleep_intctl_config1[0] = au_readl(IC0_CFG1RD); | |
593 | sleep_intctl_config2[0] = au_readl(IC0_CFG2RD); | |
594 | sleep_intctl_src[0] = au_readl(IC0_SRCRD); | |
595 | sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD); | |
596 | sleep_intctl_wake[0] = au_readl(IC0_WAKERD); | |
597 | sleep_intctl_mask[0] = au_readl(IC0_MASKRD); | |
598 | ||
599 | sleep_intctl_config0[1] = au_readl(IC1_CFG0RD); | |
600 | sleep_intctl_config1[1] = au_readl(IC1_CFG1RD); | |
601 | sleep_intctl_config2[1] = au_readl(IC1_CFG2RD); | |
602 | sleep_intctl_src[1] = au_readl(IC1_SRCRD); | |
603 | sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD); | |
604 | sleep_intctl_wake[1] = au_readl(IC1_WAKERD); | |
605 | sleep_intctl_mask[1] = au_readl(IC1_MASKRD); | |
606 | } | |
607 | ||
608 | /* For most restore operations, we clear the entire register and | |
609 | * then set the bits we found during the save. | |
610 | */ | |
611 | void | |
612 | restore_au1xxx_intctl(void) | |
613 | { | |
614 | au_writel(0xffffffff, IC0_MASKCLR); au_sync(); | |
615 | ||
616 | au_writel(0xffffffff, IC0_CFG0CLR); au_sync(); | |
617 | au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync(); | |
618 | au_writel(0xffffffff, IC0_CFG1CLR); au_sync(); | |
619 | au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync(); | |
620 | au_writel(0xffffffff, IC0_CFG2CLR); au_sync(); | |
621 | au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync(); | |
622 | au_writel(0xffffffff, IC0_SRCCLR); au_sync(); | |
623 | au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync(); | |
624 | au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync(); | |
625 | au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync(); | |
626 | au_writel(0xffffffff, IC0_WAKECLR); au_sync(); | |
627 | au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync(); | |
628 | au_writel(0xffffffff, IC0_RISINGCLR); au_sync(); | |
629 | au_writel(0xffffffff, IC0_FALLINGCLR); au_sync(); | |
630 | au_writel(0x00000000, IC0_TESTBIT); au_sync(); | |
631 | ||
632 | au_writel(0xffffffff, IC1_MASKCLR); au_sync(); | |
633 | ||
634 | au_writel(0xffffffff, IC1_CFG0CLR); au_sync(); | |
635 | au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync(); | |
636 | au_writel(0xffffffff, IC1_CFG1CLR); au_sync(); | |
637 | au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync(); | |
638 | au_writel(0xffffffff, IC1_CFG2CLR); au_sync(); | |
639 | au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync(); | |
640 | au_writel(0xffffffff, IC1_SRCCLR); au_sync(); | |
641 | au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync(); | |
642 | au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync(); | |
643 | au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync(); | |
644 | au_writel(0xffffffff, IC1_WAKECLR); au_sync(); | |
645 | au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync(); | |
646 | au_writel(0xffffffff, IC1_RISINGCLR); au_sync(); | |
647 | au_writel(0xffffffff, IC1_FALLINGCLR); au_sync(); | |
648 | au_writel(0x00000000, IC1_TESTBIT); au_sync(); | |
649 | ||
650 | au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync(); | |
651 | ||
652 | au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync(); | |
653 | } | |
654 | #endif /* CONFIG_PM */ |