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1da177e4 LT |
1 | /* |
2 | * Copyright 2001 MontaVista Software Inc. | |
3 | * Author: jsun@mvista.com or jsun@junsun.net | |
4 | * | |
5 | * First-level interrupt dispatcher for ocelot board. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | #include <asm/asm.h> | |
13 | #include <asm/mipsregs.h> | |
14 | #include <asm/addrspace.h> | |
15 | #include <asm/regdef.h> | |
16 | #include <asm/stackframe.h> | |
17 | ||
18 | /* | |
19 | * first level interrupt dispatcher for ocelot board - | |
20 | * We check for the timer first, then check PCI ints A and D. | |
21 | * Then check for serial IRQ and fall through. | |
22 | */ | |
23 | .align 5 | |
24 | NESTED(ocelot_handle_int, PT_SIZE, sp) | |
25 | SAVE_ALL | |
26 | CLI | |
27 | .set at | |
28 | mfc0 t0, CP0_CAUSE | |
29 | mfc0 t2, CP0_STATUS | |
30 | ||
31 | and t0, t2 | |
32 | ||
33 | andi t1, t0, STATUSF_IP2 /* int0 hardware line */ | |
34 | bnez t1, ll_pri_enet_irq | |
35 | andi t1, t0, STATUSF_IP3 /* int1 hardware line */ | |
36 | bnez t1, ll_sec_enet_irq | |
37 | andi t1, t0, STATUSF_IP4 /* int2 hardware line */ | |
38 | bnez t1, ll_uart1_irq | |
39 | andi t1, t0, STATUSF_IP5 /* int3 hardware line */ | |
40 | bnez t1, ll_cpci_irq | |
41 | andi t1, t0, STATUSF_IP6 /* int4 hardware line */ | |
42 | bnez t1, ll_galileo_irq | |
43 | andi t1, t0, STATUSF_IP7 /* cpu timer */ | |
44 | bnez t1, ll_cputimer_irq | |
45 | ||
46 | /* now look at the extended interrupts */ | |
47 | mfc0 t0, CP0_CAUSE | |
48 | cfc0 t1, CP0_S1_INTCONTROL | |
49 | ||
50 | /* shift the mask 8 bits left to line up the bits */ | |
51 | sll t2, t1, 8 | |
52 | ||
53 | and t0, t2 | |
54 | srl t0, t0, 16 | |
55 | ||
56 | andi t1, t0, STATUSF_IP8 /* int6 hardware line */ | |
57 | bnez t1, ll_pmc1_irq | |
58 | andi t1, t0, STATUSF_IP9 /* int7 hardware line */ | |
59 | bnez t1, ll_pmc2_irq | |
60 | andi t1, t0, STATUSF_IP10 /* int8 hardware line */ | |
61 | bnez t1, ll_cpci_abcd_irq | |
62 | andi t1, t0, STATUSF_IP11 /* int9 hardware line */ | |
63 | bnez t1, ll_uart2_irq | |
64 | ||
65 | .set reorder | |
66 | ||
67 | /* wrong alarm or masked ... */ | |
68 | j spurious_interrupt | |
69 | nop | |
70 | END(ocelot_handle_int) | |
71 | ||
72 | .align 5 | |
73 | ll_pri_enet_irq: | |
74 | li a0, 2 | |
75 | move a1, sp | |
76 | jal do_IRQ | |
77 | j ret_from_irq | |
78 | ||
79 | ll_sec_enet_irq: | |
80 | li a0, 3 | |
81 | move a1, sp | |
82 | jal do_IRQ | |
83 | j ret_from_irq | |
84 | ||
85 | ll_uart1_irq: | |
86 | li a0, 4 | |
87 | move a1, sp | |
88 | jal do_IRQ | |
89 | j ret_from_irq | |
90 | ||
91 | ll_cpci_irq: | |
92 | li a0, 5 | |
93 | move a1, sp | |
94 | jal do_IRQ | |
95 | j ret_from_irq | |
96 | ||
97 | ll_galileo_irq: | |
98 | li a0, 6 | |
99 | move a1, sp | |
100 | jal do_IRQ | |
101 | j ret_from_irq | |
102 | ||
103 | ll_cputimer_irq: | |
104 | li a0, 7 | |
105 | move a1, sp | |
106 | jal do_IRQ | |
107 | j ret_from_irq | |
108 | ||
109 | ll_pmc1_irq: | |
110 | li a0, 8 | |
111 | move a1, sp | |
112 | jal do_IRQ | |
113 | j ret_from_irq | |
114 | ||
115 | ll_pmc2_irq: | |
116 | li a0, 9 | |
117 | move a1, sp | |
118 | jal do_IRQ | |
119 | j ret_from_irq | |
120 | ||
121 | ll_cpci_abcd_irq: | |
122 | li a0, 10 | |
123 | move a1, sp | |
124 | jal do_IRQ | |
125 | j ret_from_irq | |
126 | ||
127 | ll_uart2_irq: | |
128 | li a0, 11 | |
129 | move a1, sp | |
130 | jal do_IRQ | |
131 | j ret_from_irq |