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1da177e4 LT |
1 | #ifndef __ASM_TLB_H |
2 | #define __ASM_TLB_H | |
3 | ||
10313980 PB |
4 | #include <asm/cpu-features.h> |
5 | #include <asm/mipsregs.h> | |
6 | ||
1da177e4 LT |
7 | /* |
8 | * MIPS doesn't need any special per-pte or per-vma handling, except | |
9 | * we need to flush cache for area to be unmapped. | |
10 | */ | |
70342287 | 11 | #define tlb_start_vma(tlb, vma) \ |
1da177e4 LT |
12 | do { \ |
13 | if (!tlb->fullmm) \ | |
14 | flush_cache_range(vma, vma->vm_start, vma->vm_end); \ | |
15 | } while (0) | |
16 | #define tlb_end_vma(tlb, vma) do { } while (0) | |
17 | #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) | |
18 | ||
19 | /* | |
20 | * .. because we flush the whole mm when it fills up. | |
21 | */ | |
22 | #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) | |
23 | ||
a6c09b9f JH |
24 | #define _UNIQUE_ENTRYHI(base, idx) \ |
25 | (((base) + ((idx) << (PAGE_SHIFT + 1))) | \ | |
6e7f8b8e | 26 | (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0)) |
a6c09b9f JH |
27 | #define UNIQUE_ENTRYHI(idx) _UNIQUE_ENTRYHI(CKSEG0, idx) |
28 | #define UNIQUE_GUEST_ENTRYHI(idx) _UNIQUE_ENTRYHI(CKSEG1, idx) | |
c01905ee | 29 | |
10313980 PB |
30 | static inline unsigned int num_wired_entries(void) |
31 | { | |
32 | unsigned int wired = read_c0_wired(); | |
33 | ||
34 | if (cpu_has_mips_r6) | |
35 | wired &= MIPSR6_WIRED_WIRED; | |
36 | ||
37 | return wired; | |
38 | } | |
39 | ||
1da177e4 LT |
40 | #include <asm-generic/tlb.h> |
41 | ||
42 | #endif /* __ASM_TLB_H */ |