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MIPS: Add cpu_vpe_id macro
[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
654f57bf 26#include <asm/watch.h>
06372a63 27#include <asm/elf.h>
a074f0e8 28#include <asm/spram.h>
949e51be
DD		 29#include <asm/uaccess.h>
30
078a55fc 31static int mips_fpu_disabled;
0103d23f
KC		 32
33static int __init fpu_disable(char *s)
34{
35 cpu_data[0].options &= ~MIPS_CPU_FPU;
36 mips_fpu_disabled = 1;
37
38 return 1;
39}
40
41__setup("nofpu", fpu_disable);
42
078a55fc 43int mips_dsp_disabled;
0103d23f
KC		 44
45static int __init dsp_disable(char *s)
46{
ee80f7c7 47 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 48 mips_dsp_disabled = 1;
49
50 return 1;
51}
52
53__setup("nodsp", dsp_disable);
54
9267a30d
MSJ		 55static inline void check_errata(void)
56{
57 struct cpuinfo_mips *c = &current_cpu_data;
58
69f24d17 59 switch (current_cpu_type()) {
9267a30d
MSJ		 60 case CPU_34K:
61 /*
62 * Erratum "RPS May Cause Incorrect Instruction Execution"
63 * This code only handles VPE0, any SMP/SMTC/RTOS code
64 * making use of VPE1 will be responsable for that VPE.
65 */
66 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
67 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
68 break;
69 default:
70 break;
71 }
72}
73
1da177e4
LT		 74void __init check_bugs32(void)
75{
9267a30d 76 check_errata();
1da177e4
LT		 77}
78
79/*
80 * Probe whether cpu has config register by trying to play with
81 * alternate cache bit and see whether it matters.
82 * It's used by cpu_probe to distinguish between R3000A and R3081.
83 */
84static inline int cpu_has_confreg(void)
85{
86#ifdef CONFIG_CPU_R3000
87 extern unsigned long r3k_cache_size(unsigned long);
88 unsigned long size1, size2;
89 unsigned long cfg = read_c0_conf();
90
91 size1 = r3k_cache_size(ST0_ISC);
92 write_c0_conf(cfg ^ R30XX_CONF_AC);
93 size2 = r3k_cache_size(ST0_ISC);
94 write_c0_conf(cfg);
95 return size1 != size2;
96#else
97 return 0;
98#endif
99}
100
c094c99e
RM		 101static inline void set_elf_platform(int cpu, const char *plat)
102{
103 if (cpu == 0)
104 __elf_platform = plat;
105}
106
1da177e4
LT		 107/*
108 * Get the FPU Implementation/Revision.
109 */
110static inline unsigned long cpu_get_fpu_id(void)
111{
112 unsigned long tmp, fpu_id;
113
114 tmp = read_c0_status();
597ce172 115 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 116 fpu_id = read_32bit_cp1_register(CP1_REVISION);
117 write_c0_status(tmp);
118 return fpu_id;
119}
120
121/*
122 * Check the CPU has an FPU the official way.
123 */
124static inline int __cpu_has_fpu(void)
125{
8ff374b9 126 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
1da177e4
LT		 127}
128
91dfc423
GR		 129static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
130{
131#ifdef __NEED_VMBITS_PROBE
5b7efa89 132 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 133 back_to_back_c0_hazard();
5b7efa89 134 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 135#endif
136}
137
078a55fc 138static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 139{
140 switch (isa) {
141 case MIPS_CPU_ISA_M64R2:
142 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
143 case MIPS_CPU_ISA_M64R1:
144 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
145 case MIPS_CPU_ISA_V:
146 c->isa_level |= MIPS_CPU_ISA_V;
147 case MIPS_CPU_ISA_IV:
148 c->isa_level |= MIPS_CPU_ISA_IV;
149 case MIPS_CPU_ISA_III:
1990e542 150 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 151 break;
152
153 case MIPS_CPU_ISA_M32R2:
154 c->isa_level |= MIPS_CPU_ISA_M32R2;
155 case MIPS_CPU_ISA_M32R1:
156 c->isa_level |= MIPS_CPU_ISA_M32R1;
157 case MIPS_CPU_ISA_II:
158 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 159 break;
160 }
161}
162
078a55fc 163static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 164 "Unsupported ISA type, c0.config0: %d.";
165
75b5b5e0
LY		 166static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
167{
168 unsigned int config6;
169 /*
170 * Config6 is implementation dependent and it's currently only
171 * used by proAptiv
172 */
173 if (c->cputype == CPU_PROAPTIV) {
174 config6 = read_c0_config6();
175 if (enable)
176 /* Enable FTLB */
177 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
178 else
179 /* Disable FTLB */
180 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
181 back_to_back_c0_hazard();
182 }
183}
184
2fa36399
KC		 185static inline unsigned int decode_config0(struct cpuinfo_mips *c)
186{
187 unsigned int config0;
188 int isa;
189
190 config0 = read_c0_config();
191
75b5b5e0
LY		 192 /*
193 * Look for Standard TLB or Dual VTLB and FTLB
194 */
195 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
196 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 197 c->options |= MIPS_CPU_TLB;
75b5b5e0 198
2fa36399
KC		 199 isa = (config0 & MIPS_CONF_AT) >> 13;
200 switch (isa) {
201 case 0:
202 switch ((config0 & MIPS_CONF_AR) >> 10) {
203 case 0:
a96102be 204 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 205 break;
206 case 1:
a96102be 207 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 208 break;
209 default:
210 goto unknown;
211 }
212 break;
213 case 2:
214 switch ((config0 & MIPS_CONF_AR) >> 10) {
215 case 0:
a96102be 216 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 217 break;
218 case 1:
a96102be 219 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 220 break;
221 default:
222 goto unknown;
223 }
224 break;
225 default:
226 goto unknown;
227 }
228
229 return config0 & MIPS_CONF_M;
230
231unknown:
232 panic(unknown_isa, config0);
233}
234
235static inline unsigned int decode_config1(struct cpuinfo_mips *c)
236{
237 unsigned int config1;
238
239 config1 = read_c0_config1();
240
241 if (config1 & MIPS_CONF1_MD)
242 c->ases |= MIPS_ASE_MDMX;
243 if (config1 & MIPS_CONF1_WR)
244 c->options |= MIPS_CPU_WATCH;
245 if (config1 & MIPS_CONF1_CA)
246 c->ases |= MIPS_ASE_MIPS16;
247 if (config1 & MIPS_CONF1_EP)
248 c->options |= MIPS_CPU_EJTAG;
249 if (config1 & MIPS_CONF1_FP) {
250 c->options |= MIPS_CPU_FPU;
251 c->options |= MIPS_CPU_32FPR;
252 }
75b5b5e0 253 if (cpu_has_tlb) {
2fa36399 254 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 255 c->tlbsizevtlb = c->tlbsize;
256 c->tlbsizeftlbsets = 0;
257 }
2fa36399
KC		 258
259 return config1 & MIPS_CONF_M;
260}
261
262static inline unsigned int decode_config2(struct cpuinfo_mips *c)
263{
264 unsigned int config2;
265
266 config2 = read_c0_config2();
267
268 if (config2 & MIPS_CONF2_SL)
269 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
270
271 return config2 & MIPS_CONF_M;
272}
273
274static inline unsigned int decode_config3(struct cpuinfo_mips *c)
275{
276 unsigned int config3;
277
278 config3 = read_c0_config3();
279
b2ab4f08 280 if (config3 & MIPS_CONF3_SM) {
2fa36399 281 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 282 c->options |= MIPS_CPU_RIXI;
283 }
284 if (config3 & MIPS_CONF3_RXI)
285 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 286 if (config3 & MIPS_CONF3_DSP)
287 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 288 if (config3 & MIPS_CONF3_DSP2P)
289 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 290 if (config3 & MIPS_CONF3_VINT)
291 c->options |= MIPS_CPU_VINT;
292 if (config3 & MIPS_CONF3_VEIC)
293 c->options |= MIPS_CPU_VEIC;
294 if (config3 & MIPS_CONF3_MT)
295 c->ases |= MIPS_ASE_MIPSMT;
296 if (config3 & MIPS_CONF3_ULRI)
297 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 298 if (config3 & MIPS_CONF3_ISA)
299 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 300 if (config3 & MIPS_CONF3_VZ)
301 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 302 if (config3 & MIPS_CONF3_SC)
303 c->options |= MIPS_CPU_SEGMENTS;
2fa36399
KC		 304
305 return config3 & MIPS_CONF_M;
306}
307
308static inline unsigned int decode_config4(struct cpuinfo_mips *c)
309{
310 unsigned int config4;
75b5b5e0
LY		 311 unsigned int newcf4;
312 unsigned int mmuextdef;
313 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 314
315 config4 = read_c0_config4();
316
1745c1ef
LY		 317 if (cpu_has_tlb) {
318 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
319 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 320 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
321 switch (mmuextdef) {
322 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
323 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
324 c->tlbsizevtlb = c->tlbsize;
325 break;
326 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
327 c->tlbsizevtlb +=
328 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
329 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
330 c->tlbsize = c->tlbsizevtlb;
331 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
332 /* fall through */
333 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
334 newcf4 = (config4 & ~ftlb_page) |
335 (page_size_ftlb(mmuextdef) <<
336 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
337 write_c0_config4(newcf4);
338 back_to_back_c0_hazard();
339 config4 = read_c0_config4();
340 if (config4 != newcf4) {
341 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
342 PAGE_SIZE, config4);
343 /* Switch FTLB off */
344 set_ftlb_enable(c, 0);
345 break;
346 }
347 c->tlbsizeftlbsets = 1 <<
348 ((config4 & MIPS_CONF4_FTLBSETS) >>
349 MIPS_CONF4_FTLBSETS_SHIFT);
350 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
351 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
352 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
353 break;
354 }
1745c1ef
LY		 355 }
356
2fa36399
KC		 357 c->kscratch_mask = (config4 >> 16) & 0xff;
358
359 return config4 & MIPS_CONF_M;
360}
361
8b8a7634
RB		 362static inline unsigned int decode_config5(struct cpuinfo_mips *c)
363{
364 unsigned int config5;
365
366 config5 = read_c0_config5();
367 config5 &= ~MIPS_CONF5_UFR;
368 write_c0_config5(config5);
369
370 return config5 & MIPS_CONF_M;
371}
372
078a55fc 373static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 374{
375 int ok;
376
377 /* MIPS32 or MIPS64 compliant CPU. */
378 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
379 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
380
381 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
382
75b5b5e0
LY		 383 /* Enable FTLB if present */
384 set_ftlb_enable(c, 1);
385
2fa36399 386 ok = decode_config0(c); /* Read Config registers. */
70342287 387 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 388 if (ok)
389 ok = decode_config1(c);
390 if (ok)
391 ok = decode_config2(c);
392 if (ok)
393 ok = decode_config3(c);
394 if (ok)
395 ok = decode_config4(c);
8b8a7634
RB		 396 if (ok)
397 ok = decode_config5(c);
2fa36399
KC		 398
399 mips_probe_watch_registers(c);
400
401 if (cpu_has_mips_r2)
402 c->core = read_c0_ebase() & 0x3ff;
403}
404
02cf2119 405#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 406 | MIPS_CPU_COUNTER)
407
cea7e2df 408static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 409{
8ff374b9 410 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 411 case PRID_IMP_R2000:
412 c->cputype = CPU_R2000;
cea7e2df 413 __cpu_name[cpu] = "R2000";
02cf2119 414 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 415 MIPS_CPU_NOFPUEX;
1da177e4
LT		 416 if (__cpu_has_fpu())
417 c->options |= MIPS_CPU_FPU;
418 c->tlbsize = 64;
419 break;
420 case PRID_IMP_R3000:
8ff374b9 421 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 422 if (cpu_has_confreg()) {
1da177e4 423 c->cputype = CPU_R3081E;
cea7e2df
RB		 424 __cpu_name[cpu] = "R3081";
425 } else {
1da177e4 426 c->cputype = CPU_R3000A;
cea7e2df
RB		 427 __cpu_name[cpu] = "R3000A";
428 }
cea7e2df 429 } else {
1da177e4 430 c->cputype = CPU_R3000;
cea7e2df
RB		 431 __cpu_name[cpu] = "R3000";
432 }
02cf2119 433 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 434 MIPS_CPU_NOFPUEX;
1da177e4
LT		 435 if (__cpu_has_fpu())
436 c->options |= MIPS_CPU_FPU;
437 c->tlbsize = 64;
438 break;
439 case PRID_IMP_R4000:
440 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 441 if ((c->processor_id & PRID_REV_MASK) >=
442 PRID_REV_R4400) {
1da177e4 443 c->cputype = CPU_R4400PC;
cea7e2df
RB		 444 __cpu_name[cpu] = "R4400PC";
445 } else {
1da177e4 446 c->cputype = CPU_R4000PC;
cea7e2df
RB		 447 __cpu_name[cpu] = "R4000PC";
448 }
1da177e4 449 } else {
7f177a52
MR		 450 int cca = read_c0_config() & CONF_CM_CMASK;
451 int mc;
452
453 /*
454 * SC and MC versions can't be reliably told apart,
455 * but only the latter support coherent caching
456 * modes so assume the firmware has set the KSEG0
457 * coherency attribute reasonably (if uncached, we
458 * assume SC).
459 */
460 switch (cca) {
461 case CONF_CM_CACHABLE_CE:
462 case CONF_CM_CACHABLE_COW:
463 case CONF_CM_CACHABLE_CUW:
464 mc = 1;
465 break;
466 default:
467 mc = 0;
468 break;
469 }
8ff374b9
MR		 470 if ((c->processor_id & PRID_REV_MASK) >=
471 PRID_REV_R4400) {
7f177a52
MR		 472 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
473 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 474 } else {
7f177a52
MR		 475 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
476 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 477 }
1da177e4
LT		 478 }
479
a96102be 480 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 481 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 482 MIPS_CPU_WATCH | MIPS_CPU_VCE |
483 MIPS_CPU_LLSC;
1da177e4
LT		 484 c->tlbsize = 48;
485 break;
486 case PRID_IMP_VR41XX:
9f91e506
YY		 487 set_isa(c, MIPS_CPU_ISA_III);
488 c->options = R4K_OPTS;
489 c->tlbsize = 32;
1da177e4 490 switch (c->processor_id & 0xf0) {
1da177e4
LT		 491 case PRID_REV_VR4111:
492 c->cputype = CPU_VR4111;
cea7e2df 493 __cpu_name[cpu] = "NEC VR4111";
1da177e4 494 break;
1da177e4
LT		 495 case PRID_REV_VR4121:
496 c->cputype = CPU_VR4121;
cea7e2df 497 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 498 break;
499 case PRID_REV_VR4122:
cea7e2df 500 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 501 c->cputype = CPU_VR4122;
cea7e2df
RB		 502 __cpu_name[cpu] = "NEC VR4122";
503 } else {
1da177e4 504 c->cputype = CPU_VR4181A;
cea7e2df
RB		 505 __cpu_name[cpu] = "NEC VR4181A";
506 }
1da177e4
LT		 507 break;
508 case PRID_REV_VR4130:
cea7e2df 509 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 510 c->cputype = CPU_VR4131;
cea7e2df
RB		 511 __cpu_name[cpu] = "NEC VR4131";
512 } else {
1da177e4 513 c->cputype = CPU_VR4133;
9f91e506 514 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 515 __cpu_name[cpu] = "NEC VR4133";
516 }
1da177e4
LT		 517 break;
518 default:
519 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
520 c->cputype = CPU_VR41XX;
cea7e2df 521 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 522 break;
523 }
1da177e4
LT		 524 break;
525 case PRID_IMP_R4300:
526 c->cputype = CPU_R4300;
cea7e2df 527 __cpu_name[cpu] = "R4300";
a96102be 528 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 529 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 530 MIPS_CPU_LLSC;
1da177e4
LT		 531 c->tlbsize = 32;
532 break;
533 case PRID_IMP_R4600:
534 c->cputype = CPU_R4600;
cea7e2df 535 __cpu_name[cpu] = "R4600";
a96102be 536 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 537 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
538 MIPS_CPU_LLSC;
1da177e4
LT		 539 c->tlbsize = 48;
540 break;
541 #if 0
03751e79 542 case PRID_IMP_R4650:
1da177e4
LT		 543 /*
544 * This processor doesn't have an MMU, so it's not
545 * "real easy" to run Linux on it. It is left purely
546 * for documentation. Commented out because it shares
547 * it's c0_prid id number with the TX3900.
548 */
a3dddd56 549 c->cputype = CPU_R4650;
cea7e2df 550 __cpu_name[cpu] = "R4650";
a96102be 551 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 552 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 553 c->tlbsize = 48;
1da177e4
LT		 554 break;
555 #endif
556 case PRID_IMP_TX39:
02cf2119 557 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 558
559 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
560 c->cputype = CPU_TX3927;
cea7e2df 561 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 562 c->tlbsize = 64;
563 } else {
8ff374b9 564 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 565 case PRID_REV_TX3912:
566 c->cputype = CPU_TX3912;
cea7e2df 567 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 568 c->tlbsize = 32;
569 break;
570 case PRID_REV_TX3922:
571 c->cputype = CPU_TX3922;
cea7e2df 572 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 573 c->tlbsize = 64;
574 break;
1da177e4
LT		 575 }
576 }
577 break;
578 case PRID_IMP_R4700:
579 c->cputype = CPU_R4700;
cea7e2df 580 __cpu_name[cpu] = "R4700";
a96102be 581 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 582 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 583 MIPS_CPU_LLSC;
1da177e4
LT		 584 c->tlbsize = 48;
585 break;
586 case PRID_IMP_TX49:
587 c->cputype = CPU_TX49XX;
cea7e2df 588 __cpu_name[cpu] = "R49XX";
a96102be 589 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 590 c->options = R4K_OPTS | MIPS_CPU_LLSC;
591 if (!(c->processor_id & 0x08))
592 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
593 c->tlbsize = 48;
594 break;
595 case PRID_IMP_R5000:
596 c->cputype = CPU_R5000;
cea7e2df 597 __cpu_name[cpu] = "R5000";
a96102be 598 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 599 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 600 MIPS_CPU_LLSC;
1da177e4
LT		 601 c->tlbsize = 48;
602 break;
603 case PRID_IMP_R5432:
604 c->cputype = CPU_R5432;
cea7e2df 605 __cpu_name[cpu] = "R5432";
a96102be 606 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 607 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 608 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 609 c->tlbsize = 48;
610 break;
611 case PRID_IMP_R5500:
612 c->cputype = CPU_R5500;
cea7e2df 613 __cpu_name[cpu] = "R5500";
a96102be 614 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 615 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 616 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 617 c->tlbsize = 48;
618 break;
619 case PRID_IMP_NEVADA:
620 c->cputype = CPU_NEVADA;
cea7e2df 621 __cpu_name[cpu] = "Nevada";
a96102be 622 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 623 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 624 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 625 c->tlbsize = 48;
626 break;
627 case PRID_IMP_R6000:
628 c->cputype = CPU_R6000;
cea7e2df 629 __cpu_name[cpu] = "R6000";
a96102be 630 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 631 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 632 MIPS_CPU_LLSC;
1da177e4
LT		 633 c->tlbsize = 32;
634 break;
635 case PRID_IMP_R6000A:
636 c->cputype = CPU_R6000A;
cea7e2df 637 __cpu_name[cpu] = "R6000A";
a96102be 638 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 639 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 640 MIPS_CPU_LLSC;
1da177e4
LT		 641 c->tlbsize = 32;
642 break;
643 case PRID_IMP_RM7000:
644 c->cputype = CPU_RM7000;
cea7e2df 645 __cpu_name[cpu] = "RM7000";
a96102be 646 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 647 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 648 MIPS_CPU_LLSC;
1da177e4 649 /*
70342287 650 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 651 * the RM7000 v2.0 indicates if the TLB has 48 or 64
652 * entries.
653 *
70342287
RB		 654 * 29 1 => 64 entry JTLB
655 * 0 => 48 entry JTLB
1da177e4
LT		 656 */
657 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
658 break;
659 case PRID_IMP_RM9000:
660 c->cputype = CPU_RM9000;
cea7e2df 661 __cpu_name[cpu] = "RM9000";
a96102be 662 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 663 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 664 MIPS_CPU_LLSC;
1da177e4
LT		 665 /*
666 * Bit 29 in the info register of the RM9000
667 * indicates if the TLB has 48 or 64 entries.
668 *
70342287
RB		 669 * 29 1 => 64 entry JTLB
670 * 0 => 48 entry JTLB
1da177e4
LT		 671 */
672 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
673 break;
674 case PRID_IMP_R8000:
675 c->cputype = CPU_R8000;
cea7e2df 676 __cpu_name[cpu] = "RM8000";
a96102be 677 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 678 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 679 MIPS_CPU_FPU | MIPS_CPU_32FPR |
680 MIPS_CPU_LLSC;
1da177e4
LT		 681 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
682 break;
683 case PRID_IMP_R10000:
684 c->cputype = CPU_R10000;
cea7e2df 685 __cpu_name[cpu] = "R10000";
a96102be 686 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 687 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 688 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 689 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 690 MIPS_CPU_LLSC;
1da177e4
LT		 691 c->tlbsize = 64;
692 break;
693 case PRID_IMP_R12000:
694 c->cputype = CPU_R12000;
cea7e2df 695 __cpu_name[cpu] = "R12000";
a96102be 696 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 697 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 698 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 699 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 700 MIPS_CPU_LLSC;
1da177e4
LT		 701 c->tlbsize = 64;
702 break;
44d921b2
K		 703 case PRID_IMP_R14000:
704 c->cputype = CPU_R14000;
cea7e2df 705 __cpu_name[cpu] = "R14000";
a96102be 706 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 707 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 708 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 709 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 710 MIPS_CPU_LLSC;
44d921b2
K		 711 c->tlbsize = 64;
712 break;
2a21c730
FZ		 713 case PRID_IMP_LOONGSON2:
714 c->cputype = CPU_LOONGSON2;
cea7e2df 715 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 716
717 switch (c->processor_id & PRID_REV_MASK) {
718 case PRID_REV_LOONGSON2E:
719 set_elf_platform(cpu, "loongson2e");
720 break;
721 case PRID_REV_LOONGSON2F:
722 set_elf_platform(cpu, "loongson2f");
723 break;
724 }
725
a96102be 726 set_isa(c, MIPS_CPU_ISA_III);
2a21c730
FZ		 727 c->options = R4K_OPTS |
728 MIPS_CPU_FPU | MIPS_CPU_LLSC |
729 MIPS_CPU_32FPR;
730 c->tlbsize = 64;
731 break;
2fa36399
KC		 732 case PRID_IMP_LOONGSON1:
733 decode_configs(c);
b4672d37 734
2fa36399 735 c->cputype = CPU_LOONGSON1;
1da177e4 736
2fa36399
KC		 737 switch (c->processor_id & PRID_REV_MASK) {
738 case PRID_REV_LOONGSON1B:
739 __cpu_name[cpu] = "Loongson 1B";
b4672d37 740 break;
b4672d37 741 }
4194318c 742
2fa36399 743 break;
1da177e4 744 }
1da177e4
LT		 745}
746
cea7e2df 747static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 748{
8ff374b9 749 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 750 case PRID_IMP_4KC:
751 c->cputype = CPU_4KC;
cea7e2df 752 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 753 break;
754 case PRID_IMP_4KEC:
2b07bd02
RB		 755 case PRID_IMP_4KECR2:
756 c->cputype = CPU_4KEC;
cea7e2df 757 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 758 break;
1da177e4 759 case PRID_IMP_4KSC:
8afcb5d8 760 case PRID_IMP_4KSD:
1da177e4 761 c->cputype = CPU_4KSC;
cea7e2df 762 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 763 break;
764 case PRID_IMP_5KC:
765 c->cputype = CPU_5KC;
cea7e2df 766 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 767 break;
78d4803f
LY		 768 case PRID_IMP_5KE:
769 c->cputype = CPU_5KE;
770 __cpu_name[cpu] = "MIPS 5KE";
771 break;
1da177e4
LT		 772 case PRID_IMP_20KC:
773 c->cputype = CPU_20KC;
cea7e2df 774 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 775 break;
776 case PRID_IMP_24K:
777 c->cputype = CPU_24K;
cea7e2df 778 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 779 break;
42f3caef
JC		 780 case PRID_IMP_24KE:
781 c->cputype = CPU_24K;
782 __cpu_name[cpu] = "MIPS 24KEc";
783 break;
1da177e4
LT		 784 case PRID_IMP_25KF:
785 c->cputype = CPU_25KF;
cea7e2df 786 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 787 break;
bbc7f22f
RB		 788 case PRID_IMP_34K:
789 c->cputype = CPU_34K;
cea7e2df 790 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 791 break;
c620953c
CD		 792 case PRID_IMP_74K:
793 c->cputype = CPU_74K;
cea7e2df 794 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 795 break;
113c62d9
SH		 796 case PRID_IMP_M14KC:
797 c->cputype = CPU_M14KC;
798 __cpu_name[cpu] = "MIPS M14Kc";
799 break;
f8fa4811
SH		 800 case PRID_IMP_M14KEC:
801 c->cputype = CPU_M14KEC;
802 __cpu_name[cpu] = "MIPS M14KEc";
803 break;
39b8d525
RB		 804 case PRID_IMP_1004K:
805 c->cputype = CPU_1004K;
cea7e2df 806 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 807 break;
006a851b 808 case PRID_IMP_1074K:
442e14a2 809 c->cputype = CPU_1074K;
006a851b
SH		 810 __cpu_name[cpu] = "MIPS 1074Kc";
811 break;
b5f065e7
LY		 812 case PRID_IMP_INTERAPTIV_UP:
813 c->cputype = CPU_INTERAPTIV;
814 __cpu_name[cpu] = "MIPS interAptiv";
815 break;
816 case PRID_IMP_INTERAPTIV_MP:
817 c->cputype = CPU_INTERAPTIV;
818 __cpu_name[cpu] = "MIPS interAptiv (multi)";
819 break;
b0d4d300
LY		 820 case PRID_IMP_PROAPTIV_UP:
821 c->cputype = CPU_PROAPTIV;
822 __cpu_name[cpu] = "MIPS proAptiv";
823 break;
824 case PRID_IMP_PROAPTIV_MP:
825 c->cputype = CPU_PROAPTIV;
826 __cpu_name[cpu] = "MIPS proAptiv (multi)";
827 break;
1da177e4 828 }
0b6d497f 829
75b5b5e0
LY		 830 decode_configs(c);
831
0b6d497f 832 spram_config();
1da177e4
LT		 833}
834
cea7e2df 835static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 836{
4194318c 837 decode_configs(c);
8ff374b9 838 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 839 case PRID_IMP_AU1_REV1:
840 case PRID_IMP_AU1_REV2:
270717a8 841 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 842 switch ((c->processor_id >> 24) & 0xff) {
843 case 0:
cea7e2df 844 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 845 break;
846 case 1:
cea7e2df 847 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 848 break;
849 case 2:
cea7e2df 850 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 851 break;
852 case 3:
cea7e2df 853 __cpu_name[cpu] = "Au1550";
1da177e4 854 break;
e3ad1c23 855 case 4:
cea7e2df 856 __cpu_name[cpu] = "Au1200";
8ff374b9 857 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 858 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 859 break;
860 case 5:
cea7e2df 861 __cpu_name[cpu] = "Au1210";
e3ad1c23 862 break;
1da177e4 863 default:
270717a8 864 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 865 break;
866 }
1da177e4
LT		 867 break;
868 }
869}
870
cea7e2df 871static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 872{
4194318c 873 decode_configs(c);
02cf2119 874
8ff374b9 875 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 876 case PRID_IMP_SB1:
877 c->cputype = CPU_SB1;
cea7e2df 878 __cpu_name[cpu] = "SiByte SB1";
1da177e4 879 /* FPU in pass1 is known to have issues. */
8ff374b9 880 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 881 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 882 break;
93ce2f52
AI		 883 case PRID_IMP_SB1A:
884 c->cputype = CPU_SB1A;
cea7e2df 885 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 886 break;
1da177e4
LT		 887 }
888}
889
cea7e2df 890static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 891{
4194318c 892 decode_configs(c);
8ff374b9 893 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 894 case PRID_IMP_SR71000:
895 c->cputype = CPU_SR71000;
cea7e2df 896 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 897 c->scache.ways = 8;
898 c->tlbsize = 64;
899 break;
900 }
901}
902
cea7e2df 903static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 904{
905 decode_configs(c);
8ff374b9 906 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 907 case PRID_IMP_PR4450:
908 c->cputype = CPU_PR4450;
cea7e2df 909 __cpu_name[cpu] = "Philips PR4450";
a96102be 910 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 911 break;
bdf21b18
PP		 912 }
913}
914
cea7e2df 915static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 916{
917 decode_configs(c);
8ff374b9 918 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 919 case PRID_IMP_BMIPS32_REV4:
920 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 921 c->cputype = CPU_BMIPS32;
922 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 923 set_elf_platform(cpu, "bmips32");
602977b0
KC		 924 break;
925 case PRID_IMP_BMIPS3300:
926 case PRID_IMP_BMIPS3300_ALT:
927 case PRID_IMP_BMIPS3300_BUG:
928 c->cputype = CPU_BMIPS3300;
929 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 930 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 931 break;
932 case PRID_IMP_BMIPS43XX: {
8ff374b9 933 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 934
935 if (rev >= PRID_REV_BMIPS4380_LO &&
936 rev <= PRID_REV_BMIPS4380_HI) {
937 c->cputype = CPU_BMIPS4380;
938 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 939 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 940 } else {
941 c->cputype = CPU_BMIPS4350;
942 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 943 set_elf_platform(cpu, "bmips4350");
602977b0 944 }
0de663ef 945 break;
602977b0
KC		 946 }
947 case PRID_IMP_BMIPS5000:
948 c->cputype = CPU_BMIPS5000;
949 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 950 set_elf_platform(cpu, "bmips5000");
602977b0 951 c->options |= MIPS_CPU_ULRI;
0de663ef 952 break;
1c0c13eb
AJ		 953 }
954}
955
0dd4781b
DD		 956static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
957{
958 decode_configs(c);
8ff374b9 959 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 960 case PRID_IMP_CAVIUM_CN38XX:
961 case PRID_IMP_CAVIUM_CN31XX:
962 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 963 c->cputype = CPU_CAVIUM_OCTEON;
964 __cpu_name[cpu] = "Cavium Octeon";
965 goto platform;
0dd4781b
DD		 966 case PRID_IMP_CAVIUM_CN58XX:
967 case PRID_IMP_CAVIUM_CN56XX:
968 case PRID_IMP_CAVIUM_CN50XX:
969 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 970 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
971 __cpu_name[cpu] = "Cavium Octeon+";
972platform:
c094c99e 973 set_elf_platform(cpu, "octeon");
0dd4781b 974 break;
a1431b61 975 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 976 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 977 case PRID_IMP_CAVIUM_CN66XX:
978 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 979 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 980 c->cputype = CPU_CAVIUM_OCTEON2;
981 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 982 set_elf_platform(cpu, "octeon2");
0e56b385 983 break;
af04bb85
DD		 984 case PRID_IMP_CAVIUM_CN70XX:
985 case PRID_IMP_CAVIUM_CN78XX:
986 c->cputype = CPU_CAVIUM_OCTEON3;
987 __cpu_name[cpu] = "Cavium Octeon III";
988 set_elf_platform(cpu, "octeon3");
989 break;
0dd4781b
DD		 990 default:
991 printk(KERN_INFO "Unknown Octeon chip!\n");
992 c->cputype = CPU_UNKNOWN;
993 break;
994 }
995}
996
83ccf69d
LPC		 997static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
998{
999 decode_configs(c);
1000 /* JZRISC does not implement the CP0 counter. */
1001 c->options &= ~MIPS_CPU_COUNTER;
8ff374b9 1002 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1003 case PRID_IMP_JZRISC:
1004 c->cputype = CPU_JZRISC;
1005 __cpu_name[cpu] = "Ingenic JZRISC";
1006 break;
1007 default:
1008 panic("Unknown Ingenic Processor ID!");
1009 break;
1010 }
1011}
1012
a7117c6b
J		 1013static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1014{
1015 decode_configs(c);
1016
8ff374b9 1017 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1018 c->cputype = CPU_ALCHEMY;
1019 __cpu_name[cpu] = "Au1300";
1020 /* following stuff is not for Alchemy */
1021 return;
1022 }
1023
70342287
RB		 1024 c->options = (MIPS_CPU_TLB |
1025 MIPS_CPU_4KEX |
a7117c6b 1026 MIPS_CPU_COUNTER |
70342287
RB		 1027 MIPS_CPU_DIVEC |
1028 MIPS_CPU_WATCH |
1029 MIPS_CPU_EJTAG |
a7117c6b
J		 1030 MIPS_CPU_LLSC);
1031
8ff374b9 1032 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1033 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1034 case PRID_IMP_NETLOGIC_XLP9XX:
4ca86a2f
J		 1035 c->cputype = CPU_XLP;
1036 __cpu_name[cpu] = "Broadcom XLPII";
1037 break;
1038
2aa54b20
J		 1039 case PRID_IMP_NETLOGIC_XLP8XX:
1040 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1041 c->cputype = CPU_XLP;
1042 __cpu_name[cpu] = "Netlogic XLP";
1043 break;
1044
a7117c6b
J		 1045 case PRID_IMP_NETLOGIC_XLR732:
1046 case PRID_IMP_NETLOGIC_XLR716:
1047 case PRID_IMP_NETLOGIC_XLR532:
1048 case PRID_IMP_NETLOGIC_XLR308:
1049 case PRID_IMP_NETLOGIC_XLR532C:
1050 case PRID_IMP_NETLOGIC_XLR516C:
1051 case PRID_IMP_NETLOGIC_XLR508C:
1052 case PRID_IMP_NETLOGIC_XLR308C:
1053 c->cputype = CPU_XLR;
1054 __cpu_name[cpu] = "Netlogic XLR";
1055 break;
1056
1057 case PRID_IMP_NETLOGIC_XLS608:
1058 case PRID_IMP_NETLOGIC_XLS408:
1059 case PRID_IMP_NETLOGIC_XLS404:
1060 case PRID_IMP_NETLOGIC_XLS208:
1061 case PRID_IMP_NETLOGIC_XLS204:
1062 case PRID_IMP_NETLOGIC_XLS108:
1063 case PRID_IMP_NETLOGIC_XLS104:
1064 case PRID_IMP_NETLOGIC_XLS616B:
1065 case PRID_IMP_NETLOGIC_XLS608B:
1066 case PRID_IMP_NETLOGIC_XLS416B:
1067 case PRID_IMP_NETLOGIC_XLS412B:
1068 case PRID_IMP_NETLOGIC_XLS408B:
1069 case PRID_IMP_NETLOGIC_XLS404B:
1070 c->cputype = CPU_XLR;
1071 __cpu_name[cpu] = "Netlogic XLS";
1072 break;
1073
1074 default:
a3d4fb2d 1075 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1076 c->processor_id);
1077 c->cputype = CPU_XLR;
1078 break;
1079 }
1080
a3d4fb2d 1081 if (c->cputype == CPU_XLP) {
a96102be 1082 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1083 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1084 /* This will be updated again after all threads are woken up */
1085 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1086 } else {
a96102be 1087 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1088 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1089 }
7777b939 1090 c->kscratch_mask = 0xf;
a7117c6b
J		 1091}
1092
949e51be
DD		 1093#ifdef CONFIG_64BIT
1094/* For use by uaccess.h */
1095u64 __ua_limit;
1096EXPORT_SYMBOL(__ua_limit);
1097#endif
1098
9966db25 1099const char *__cpu_name[NR_CPUS];
874fd3b5 1100const char *__elf_platform;
9966db25 1101
078a55fc 1102void cpu_probe(void)
1da177e4
LT		 1103{
1104 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1105 unsigned int cpu = smp_processor_id();
1da177e4 1106
70342287 1107 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1108 c->fpu_id = FPIR_IMP_NONE;
1109 c->cputype = CPU_UNKNOWN;
1110
1111 c->processor_id = read_c0_prid();
8ff374b9 1112 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1113 case PRID_COMP_LEGACY:
cea7e2df 1114 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1115 break;
1116 case PRID_COMP_MIPS:
cea7e2df 1117 cpu_probe_mips(c, cpu);
1da177e4
LT		 1118 break;
1119 case PRID_COMP_ALCHEMY:
cea7e2df 1120 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1121 break;
1122 case PRID_COMP_SIBYTE:
cea7e2df 1123 cpu_probe_sibyte(c, cpu);
1da177e4 1124 break;
1c0c13eb 1125 case PRID_COMP_BROADCOM:
cea7e2df 1126 cpu_probe_broadcom(c, cpu);
1c0c13eb 1127 break;
1da177e4 1128 case PRID_COMP_SANDCRAFT:
cea7e2df 1129 cpu_probe_sandcraft(c, cpu);
1da177e4 1130 break;
a92b0588 1131 case PRID_COMP_NXP:
cea7e2df 1132 cpu_probe_nxp(c, cpu);
a3dddd56 1133 break;
0dd4781b
DD		 1134 case PRID_COMP_CAVIUM:
1135 cpu_probe_cavium(c, cpu);
1136 break;
83ccf69d
LPC		 1137 case PRID_COMP_INGENIC:
1138 cpu_probe_ingenic(c, cpu);
1139 break;
a7117c6b
J		 1140 case PRID_COMP_NETLOGIC:
1141 cpu_probe_netlogic(c, cpu);
1142 break;
1da177e4 1143 }
dec8b1ca 1144
cea7e2df
RB		 1145 BUG_ON(!__cpu_name[cpu]);
1146 BUG_ON(c->cputype == CPU_UNKNOWN);
1147
dec8b1ca
FBH		 1148 /*
1149 * Platform code can force the cpu type to optimize code
1150 * generation. In that case be sure the cpu type is correctly
1151 * manually setup otherwise it could trigger some nasty bugs.
1152 */
1153 BUG_ON(current_cpu_type() != c->cputype);
1154
0103d23f
KC		 1155 if (mips_fpu_disabled)
1156 c->options &= ~MIPS_CPU_FPU;
1157
1158 if (mips_dsp_disabled)
ee80f7c7 1159 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1160
4194318c 1161 if (c->options & MIPS_CPU_FPU) {
1da177e4 1162 c->fpu_id = cpu_get_fpu_id();
4194318c 1163
adb37892
DCZ		 1164 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1165 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1166 if (c->fpu_id & MIPS_FPIR_3D)
1167 c->ases |= MIPS_ASE_MIPS3D;
1168 }
1169 }
9966db25 1170
da4b62cd 1171 if (cpu_has_mips_r2) {
f6771dbb 1172 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1173 /* R2 has Performance Counter Interrupt indicator */
1174 c->options |= MIPS_CPU_PCI;
1175 }
f6771dbb
RB		 1176 else
1177 c->srsets = 1;
91dfc423
GR		 1178
1179 cpu_probe_vmbits(c);
949e51be
DD		 1180
1181#ifdef CONFIG_64BIT
1182 if (cpu == 0)
1183 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1184#endif
1da177e4
LT		 1185}
1186
078a55fc 1187void cpu_report(void)
1da177e4
LT		 1188{
1189 struct cpuinfo_mips *c = &current_cpu_data;
1190
d9f897c9
LY		 1191 pr_info("CPU%d revision is: %08x (%s)\n",
1192 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1193 if (c->options & MIPS_CPU_FPU)
9966db25 1194 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1195}
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