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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
d9d54177 | 28 | #include <linux/export.h> |
1da177e4 LT |
29 | #include <linux/time.h> |
30 | #include <linux/timex.h> | |
589ee628 | 31 | #include <linux/sched/mm.h> |
1da177e4 | 32 | #include <linux/cpumask.h> |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
8f99a162 | 35 | #include <linux/ftrace.h> |
fbde2d7d QY |
36 | #include <linux/irqdomain.h> |
37 | #include <linux/of.h> | |
38 | #include <linux/of_irq.h> | |
1da177e4 | 39 | |
60063497 | 40 | #include <linux/atomic.h> |
1da177e4 LT |
41 | #include <asm/cpu.h> |
42 | #include <asm/processor.h> | |
bdc92d74 | 43 | #include <asm/idle.h> |
39b8d525 | 44 | #include <asm/r4k-timer.h> |
fbde2d7d | 45 | #include <asm/mips-cpc.h> |
1da177e4 | 46 | #include <asm/mmu_context.h> |
7bcf7717 | 47 | #include <asm/time.h> |
b81947c6 | 48 | #include <asm/setup.h> |
e060f6ed | 49 | #include <asm/maar.h> |
1da177e4 | 50 | |
1da177e4 | 51 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
2dc2ae34 DD |
52 | EXPORT_SYMBOL(__cpu_number_map); |
53 | ||
1da177e4 | 54 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
2dc2ae34 | 55 | EXPORT_SYMBOL(__cpu_logical_map); |
1da177e4 | 56 | |
0ab7aefc RB |
57 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
58 | int smp_num_siblings = 1; | |
59 | EXPORT_SYMBOL(smp_num_siblings); | |
60 | ||
61 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
62 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
63 | EXPORT_SYMBOL(cpu_sibling_map); | |
64 | ||
bda4584c HC |
65 | /* representing the core map of multi-core chips of each logical CPU */ |
66 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; | |
67 | EXPORT_SYMBOL(cpu_core_map); | |
68 | ||
8a9a5823 | 69 | static DECLARE_COMPLETION(cpu_starting); |
a00eeede MR |
70 | static DECLARE_COMPLETION(cpu_running); |
71 | ||
cccf34e9 MC |
72 | /* |
73 | * A logcal cpu mask containing only one VPE per core to | |
74 | * reduce the number of IPIs on large MT systems. | |
75 | */ | |
640511ae | 76 | cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly; |
cccf34e9 MC |
77 | EXPORT_SYMBOL(cpu_foreign_map); |
78 | ||
0ab7aefc RB |
79 | /* representing cpus for which sibling maps can be computed */ |
80 | static cpumask_t cpu_sibling_setup_map; | |
81 | ||
bda4584c HC |
82 | /* representing cpus for which core maps can be computed */ |
83 | static cpumask_t cpu_core_setup_map; | |
84 | ||
76306f42 PB |
85 | cpumask_t cpu_coherent_mask; |
86 | ||
fbde2d7d QY |
87 | #ifdef CONFIG_GENERIC_IRQ_IPI |
88 | static struct irq_desc *call_desc; | |
89 | static struct irq_desc *sched_desc; | |
90 | #endif | |
91 | ||
0ab7aefc RB |
92 | static inline void set_cpu_sibling_map(int cpu) |
93 | { | |
94 | int i; | |
95 | ||
8dd92891 | 96 | cpumask_set_cpu(cpu, &cpu_sibling_setup_map); |
0ab7aefc RB |
97 | |
98 | if (smp_num_siblings > 1) { | |
8dd92891 | 99 | for_each_cpu(i, &cpu_sibling_setup_map) { |
bda4584c HC |
100 | if (cpu_data[cpu].package == cpu_data[i].package && |
101 | cpu_data[cpu].core == cpu_data[i].core) { | |
8dd92891 RR |
102 | cpumask_set_cpu(i, &cpu_sibling_map[cpu]); |
103 | cpumask_set_cpu(cpu, &cpu_sibling_map[i]); | |
0ab7aefc RB |
104 | } |
105 | } | |
106 | } else | |
8dd92891 | 107 | cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]); |
0ab7aefc RB |
108 | } |
109 | ||
bda4584c HC |
110 | static inline void set_cpu_core_map(int cpu) |
111 | { | |
112 | int i; | |
113 | ||
8dd92891 | 114 | cpumask_set_cpu(cpu, &cpu_core_setup_map); |
bda4584c | 115 | |
8dd92891 | 116 | for_each_cpu(i, &cpu_core_setup_map) { |
bda4584c | 117 | if (cpu_data[cpu].package == cpu_data[i].package) { |
8dd92891 RR |
118 | cpumask_set_cpu(i, &cpu_core_map[cpu]); |
119 | cpumask_set_cpu(cpu, &cpu_core_map[i]); | |
bda4584c HC |
120 | } |
121 | } | |
122 | } | |
123 | ||
cccf34e9 MC |
124 | /* |
125 | * Calculate a new cpu_foreign_map mask whenever a | |
126 | * new cpu appears or disappears. | |
127 | */ | |
826e99be | 128 | void calculate_cpu_foreign_map(void) |
cccf34e9 MC |
129 | { |
130 | int i, k, core_present; | |
131 | cpumask_t temp_foreign_map; | |
132 | ||
133 | /* Re-calculate the mask */ | |
d825c06b | 134 | cpumask_clear(&temp_foreign_map); |
cccf34e9 MC |
135 | for_each_online_cpu(i) { |
136 | core_present = 0; | |
137 | for_each_cpu(k, &temp_foreign_map) | |
138 | if (cpu_data[i].package == cpu_data[k].package && | |
139 | cpu_data[i].core == cpu_data[k].core) | |
140 | core_present = 1; | |
141 | if (!core_present) | |
142 | cpumask_set_cpu(i, &temp_foreign_map); | |
143 | } | |
144 | ||
640511ae JH |
145 | for_each_online_cpu(i) |
146 | cpumask_andnot(&cpu_foreign_map[i], | |
147 | &temp_foreign_map, &cpu_sibling_map[i]); | |
cccf34e9 MC |
148 | } |
149 | ||
87353d8a | 150 | struct plat_smp_ops *mp_ops; |
82d45de6 | 151 | EXPORT_SYMBOL(mp_ops); |
87353d8a | 152 | |
078a55fc | 153 | void register_smp_ops(struct plat_smp_ops *ops) |
87353d8a | 154 | { |
83738e30 TS |
155 | if (mp_ops) |
156 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
157 | |
158 | mp_ops = ops; | |
159 | } | |
160 | ||
fbde2d7d QY |
161 | #ifdef CONFIG_GENERIC_IRQ_IPI |
162 | void mips_smp_send_ipi_single(int cpu, unsigned int action) | |
163 | { | |
164 | mips_smp_send_ipi_mask(cpumask_of(cpu), action); | |
165 | } | |
166 | ||
167 | void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action) | |
168 | { | |
169 | unsigned long flags; | |
170 | unsigned int core; | |
171 | int cpu; | |
172 | ||
173 | local_irq_save(flags); | |
174 | ||
175 | switch (action) { | |
176 | case SMP_CALL_FUNCTION: | |
177 | __ipi_send_mask(call_desc, mask); | |
178 | break; | |
179 | ||
180 | case SMP_RESCHEDULE_YOURSELF: | |
181 | __ipi_send_mask(sched_desc, mask); | |
182 | break; | |
183 | ||
184 | default: | |
185 | BUG(); | |
186 | } | |
187 | ||
188 | if (mips_cpc_present()) { | |
189 | for_each_cpu(cpu, mask) { | |
190 | core = cpu_data[cpu].core; | |
191 | ||
192 | if (core == current_cpu_data.core) | |
193 | continue; | |
194 | ||
195 | while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) { | |
4b640136 | 196 | mips_cm_lock_other(core, 0); |
fbde2d7d QY |
197 | mips_cpc_lock_other(core); |
198 | write_cpc_co_cmd(CPC_Cx_CMD_PWRUP); | |
199 | mips_cpc_unlock_other(); | |
4b640136 | 200 | mips_cm_unlock_other(); |
fbde2d7d QY |
201 | } |
202 | } | |
203 | } | |
204 | ||
205 | local_irq_restore(flags); | |
206 | } | |
207 | ||
208 | ||
209 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) | |
210 | { | |
211 | scheduler_ipi(); | |
212 | ||
213 | return IRQ_HANDLED; | |
214 | } | |
215 | ||
216 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
217 | { | |
218 | generic_smp_call_function_interrupt(); | |
219 | ||
220 | return IRQ_HANDLED; | |
221 | } | |
222 | ||
223 | static struct irqaction irq_resched = { | |
224 | .handler = ipi_resched_interrupt, | |
225 | .flags = IRQF_PERCPU, | |
226 | .name = "IPI resched" | |
227 | }; | |
228 | ||
229 | static struct irqaction irq_call = { | |
230 | .handler = ipi_call_interrupt, | |
231 | .flags = IRQF_PERCPU, | |
232 | .name = "IPI call" | |
233 | }; | |
234 | ||
7688c539 | 235 | static void smp_ipi_init_one(unsigned int virq, |
fbde2d7d QY |
236 | struct irqaction *action) |
237 | { | |
238 | int ret; | |
239 | ||
240 | irq_set_handler(virq, handle_percpu_irq); | |
241 | ret = setup_irq(virq, action); | |
242 | BUG_ON(ret); | |
243 | } | |
244 | ||
7688c539 MR |
245 | static unsigned int call_virq, sched_virq; |
246 | ||
247 | int mips_smp_ipi_allocate(const struct cpumask *mask) | |
fbde2d7d | 248 | { |
7688c539 | 249 | int virq; |
fbde2d7d QY |
250 | struct irq_domain *ipidomain; |
251 | struct device_node *node; | |
252 | ||
253 | node = of_irq_find_parent(of_root); | |
254 | ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI); | |
255 | ||
256 | /* | |
257 | * Some platforms have half DT setup. So if we found irq node but | |
258 | * didn't find an ipidomain, try to search for one that is not in the | |
259 | * DT. | |
260 | */ | |
261 | if (node && !ipidomain) | |
262 | ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI); | |
263 | ||
578bffc8 | 264 | /* |
e6488982 PB |
265 | * There are systems which use IPI IRQ domains, but only have one |
266 | * registered when some runtime condition is met. For example a Malta | |
267 | * kernel may include support for GIC & CPU interrupt controller IPI | |
268 | * IRQ domains, but if run on a system with no GIC & no MT ASE then | |
269 | * neither will be supported or registered. | |
270 | * | |
271 | * We only have a problem if we're actually using multiple CPUs so fail | |
272 | * loudly if that is the case. Otherwise simply return, skipping IPI | |
273 | * setup, if we're running with only a single CPU. | |
578bffc8 | 274 | */ |
e6488982 PB |
275 | if (!ipidomain) { |
276 | BUG_ON(num_present_cpus() > 1); | |
578bffc8 | 277 | return 0; |
e6488982 | 278 | } |
fbde2d7d | 279 | |
7688c539 MR |
280 | virq = irq_reserve_ipi(ipidomain, mask); |
281 | BUG_ON(!virq); | |
282 | if (!call_virq) | |
283 | call_virq = virq; | |
fbde2d7d | 284 | |
7688c539 MR |
285 | virq = irq_reserve_ipi(ipidomain, mask); |
286 | BUG_ON(!virq); | |
287 | if (!sched_virq) | |
288 | sched_virq = virq; | |
fbde2d7d QY |
289 | |
290 | if (irq_domain_is_ipi_per_cpu(ipidomain)) { | |
291 | int cpu; | |
292 | ||
7688c539 | 293 | for_each_cpu(cpu, mask) { |
fbde2d7d QY |
294 | smp_ipi_init_one(call_virq + cpu, &irq_call); |
295 | smp_ipi_init_one(sched_virq + cpu, &irq_resched); | |
296 | } | |
297 | } else { | |
298 | smp_ipi_init_one(call_virq, &irq_call); | |
299 | smp_ipi_init_one(sched_virq, &irq_resched); | |
300 | } | |
301 | ||
7688c539 MR |
302 | return 0; |
303 | } | |
304 | ||
305 | int mips_smp_ipi_free(const struct cpumask *mask) | |
306 | { | |
307 | struct irq_domain *ipidomain; | |
308 | struct device_node *node; | |
309 | ||
310 | node = of_irq_find_parent(of_root); | |
311 | ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI); | |
312 | ||
313 | /* | |
314 | * Some platforms have half DT setup. So if we found irq node but | |
315 | * didn't find an ipidomain, try to search for one that is not in the | |
316 | * DT. | |
317 | */ | |
318 | if (node && !ipidomain) | |
319 | ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI); | |
320 | ||
321 | BUG_ON(!ipidomain); | |
322 | ||
323 | if (irq_domain_is_ipi_per_cpu(ipidomain)) { | |
324 | int cpu; | |
325 | ||
326 | for_each_cpu(cpu, mask) { | |
327 | remove_irq(call_virq + cpu, &irq_call); | |
328 | remove_irq(sched_virq + cpu, &irq_resched); | |
329 | } | |
330 | } | |
331 | irq_destroy_ipi(call_virq, mask); | |
332 | irq_destroy_ipi(sched_virq, mask); | |
333 | return 0; | |
334 | } | |
335 | ||
336 | ||
337 | static int __init mips_smp_ipi_init(void) | |
338 | { | |
9b03d8ab PB |
339 | if (num_possible_cpus() == 1) |
340 | return 0; | |
341 | ||
7688c539 MR |
342 | mips_smp_ipi_allocate(cpu_possible_mask); |
343 | ||
fbde2d7d QY |
344 | call_desc = irq_to_desc(call_virq); |
345 | sched_desc = irq_to_desc(sched_virq); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | early_initcall(mips_smp_ipi_init); | |
350 | #endif | |
351 | ||
1da177e4 LT |
352 | /* |
353 | * First C code run on the secondary CPUs after being started up by | |
354 | * the master. | |
355 | */ | |
078a55fc | 356 | asmlinkage void start_secondary(void) |
1da177e4 | 357 | { |
5bfb5d69 | 358 | unsigned int cpu; |
1da177e4 LT |
359 | |
360 | cpu_probe(); | |
6650df3c | 361 | per_cpu_trap_init(false); |
7bcf7717 | 362 | mips_clockevent_init(); |
87353d8a | 363 | mp_ops->init_secondary(); |
c7754e75 | 364 | cpu_report(); |
e060f6ed | 365 | maar_init(); |
1da177e4 LT |
366 | |
367 | /* | |
368 | * XXX parity protection should be folded in here when it's converted | |
369 | * to an option instead of something based on .cputype | |
370 | */ | |
371 | ||
372 | calibrate_delay(); | |
5bfb5d69 NP |
373 | preempt_disable(); |
374 | cpu = smp_processor_id(); | |
1da177e4 LT |
375 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
376 | ||
8dd92891 | 377 | cpumask_set_cpu(cpu, &cpu_coherent_mask); |
e545a614 MS |
378 | notify_cpu_starting(cpu); |
379 | ||
8a9a5823 MR |
380 | /* Notify boot CPU that we're starting & ready to sync counters */ |
381 | complete(&cpu_starting); | |
382 | ||
383 | synchronise_count_slave(cpu); | |
384 | ||
385 | /* The CPU is running and counters synchronised, now mark it online */ | |
b9a09a06 YZ |
386 | set_cpu_online(cpu, true); |
387 | ||
0ab7aefc | 388 | set_cpu_sibling_map(cpu); |
bda4584c | 389 | set_cpu_core_map(cpu); |
1da177e4 | 390 | |
cccf34e9 MC |
391 | calculate_cpu_foreign_map(); |
392 | ||
8a9a5823 MR |
393 | /* |
394 | * Notify boot CPU that we're up & online and it can safely return | |
395 | * from __cpu_up | |
396 | */ | |
6f542ebe | 397 | complete(&cpu_running); |
6f542ebe | 398 | |
b789ad63 YZ |
399 | /* |
400 | * irq will be enabled in ->smp_finish(), enabling it too early | |
401 | * is dangerous. | |
402 | */ | |
403 | WARN_ON_ONCE(!irqs_disabled()); | |
5309bdac YZ |
404 | mp_ops->smp_finish(); |
405 | ||
fc6d73d6 | 406 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
1da177e4 LT |
407 | } |
408 | ||
1da177e4 LT |
409 | static void stop_this_cpu(void *dummy) |
410 | { | |
411 | /* | |
92696316 | 412 | * Remove this CPU: |
1da177e4 | 413 | */ |
cccf34e9 | 414 | |
0b5f9c00 | 415 | set_cpu_online(smp_processor_id(), false); |
cccf34e9 | 416 | calculate_cpu_foreign_map(); |
ea925a72 AB |
417 | local_irq_disable(); |
418 | while (1); | |
1da177e4 LT |
419 | } |
420 | ||
421 | void smp_send_stop(void) | |
422 | { | |
8691e5a8 | 423 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
424 | } |
425 | ||
426 | void __init smp_cpus_done(unsigned int max_cpus) | |
427 | { | |
1da177e4 LT |
428 | } |
429 | ||
430 | /* called from main before smp_init() */ | |
431 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
432 | { | |
1da177e4 LT |
433 | init_new_context(current, &init_mm); |
434 | current_thread_info()->cpu = 0; | |
87353d8a | 435 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 436 | set_cpu_sibling_map(0); |
bda4584c | 437 | set_cpu_core_map(0); |
cccf34e9 | 438 | calculate_cpu_foreign_map(); |
320e6aba | 439 | #ifndef CONFIG_HOTPLUG_CPU |
0b5f9c00 | 440 | init_cpu_present(cpu_possible_mask); |
320e6aba | 441 | #endif |
76306f42 | 442 | cpumask_copy(&cpu_coherent_mask, cpu_possible_mask); |
1da177e4 LT |
443 | } |
444 | ||
445 | /* preload SMP state for boot cpu */ | |
28eb0e46 | 446 | void smp_prepare_boot_cpu(void) |
1da177e4 | 447 | { |
4037ac6e RR |
448 | set_cpu_possible(0, true); |
449 | set_cpu_online(0, true); | |
1da177e4 LT |
450 | } |
451 | ||
078a55fc | 452 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 453 | { |
360014a3 | 454 | mp_ops->boot_secondary(cpu, tidle); |
1da177e4 | 455 | |
8a9a5823 MR |
456 | /* Wait for CPU to start and be ready to sync counters */ |
457 | if (!wait_for_completion_timeout(&cpu_starting, | |
a00eeede MR |
458 | msecs_to_jiffies(1000))) { |
459 | pr_crit("CPU%u: failed to start\n", cpu); | |
460 | return -EIO; | |
cafb45b2 | 461 | } |
1da177e4 | 462 | |
cf9bfe55 | 463 | synchronise_count_master(cpu); |
8a9a5823 MR |
464 | |
465 | /* Wait for CPU to finish startup & mark itself online before return */ | |
466 | wait_for_completion(&cpu_running); | |
1da177e4 LT |
467 | return 0; |
468 | } | |
469 | ||
1da177e4 LT |
470 | /* Not really SMP stuff ... */ |
471 | int setup_profiling_timer(unsigned int multiplier) | |
472 | { | |
473 | return 0; | |
474 | } | |
475 | ||
476 | static void flush_tlb_all_ipi(void *info) | |
477 | { | |
478 | local_flush_tlb_all(); | |
479 | } | |
480 | ||
481 | void flush_tlb_all(void) | |
482 | { | |
15c8b6c1 | 483 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
484 | } |
485 | ||
486 | static void flush_tlb_mm_ipi(void *mm) | |
487 | { | |
488 | local_flush_tlb_mm((struct mm_struct *)mm); | |
489 | } | |
490 | ||
25969354 RB |
491 | /* |
492 | * Special Variant of smp_call_function for use by TLB functions: | |
493 | * | |
494 | * o No return value | |
495 | * o collapses to normal function call on UP kernels | |
496 | * o collapses to normal function call on systems with a single shared | |
497 | * primary cache. | |
25969354 RB |
498 | */ |
499 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
500 | { | |
8691e5a8 | 501 | smp_call_function(func, info, 1); |
25969354 RB |
502 | } |
503 | ||
504 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
505 | { | |
506 | preempt_disable(); | |
507 | ||
508 | smp_on_other_tlbs(func, info); | |
509 | func(info); | |
510 | ||
511 | preempt_enable(); | |
512 | } | |
513 | ||
1da177e4 LT |
514 | /* |
515 | * The following tlb flush calls are invoked when old translations are | |
516 | * being torn down, or pte attributes are changing. For single threaded | |
517 | * address spaces, a new context is obtained on the current cpu, and tlb | |
518 | * context on other cpus are invalidated to force a new context allocation | |
519 | * at switch_mm time, should the mm ever be used on other cpus. For | |
520 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
521 | * Another case where intercpu interrupts are required is when the target | |
522 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
523 | * behalf of debugees, kswapd stealing pages from another process etc). | |
524 | * Kanoj 07/00. | |
525 | */ | |
526 | ||
527 | void flush_tlb_mm(struct mm_struct *mm) | |
528 | { | |
529 | preempt_disable(); | |
530 | ||
531 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 532 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 533 | } else { |
b5eb5511 RB |
534 | unsigned int cpu; |
535 | ||
0b5f9c00 RR |
536 | for_each_online_cpu(cpu) { |
537 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 538 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 539 | } |
1da177e4 LT |
540 | } |
541 | local_flush_tlb_mm(mm); | |
542 | ||
543 | preempt_enable(); | |
544 | } | |
545 | ||
546 | struct flush_tlb_data { | |
547 | struct vm_area_struct *vma; | |
548 | unsigned long addr1; | |
549 | unsigned long addr2; | |
550 | }; | |
551 | ||
552 | static void flush_tlb_range_ipi(void *info) | |
553 | { | |
c50cade9 | 554 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
555 | |
556 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
557 | } | |
558 | ||
559 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
560 | { | |
561 | struct mm_struct *mm = vma->vm_mm; | |
562 | ||
563 | preempt_disable(); | |
564 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
565 | struct flush_tlb_data fd = { |
566 | .vma = vma, | |
567 | .addr1 = start, | |
568 | .addr2 = end, | |
569 | }; | |
1da177e4 | 570 | |
c50cade9 | 571 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 572 | } else { |
b5eb5511 | 573 | unsigned int cpu; |
a05c3920 | 574 | int exec = vma->vm_flags & VM_EXEC; |
b5eb5511 | 575 | |
0b5f9c00 | 576 | for_each_online_cpu(cpu) { |
a05c3920 JH |
577 | /* |
578 | * flush_cache_range() will only fully flush icache if | |
579 | * the VMA is executable, otherwise we must invalidate | |
580 | * ASID without it appearing to has_valid_asid() as if | |
581 | * mm has been completely unused by that CPU. | |
582 | */ | |
0b5f9c00 | 583 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) |
a05c3920 | 584 | cpu_context(cpu, mm) = !exec; |
0b5f9c00 | 585 | } |
1da177e4 LT |
586 | } |
587 | local_flush_tlb_range(vma, start, end); | |
588 | preempt_enable(); | |
589 | } | |
590 | ||
591 | static void flush_tlb_kernel_range_ipi(void *info) | |
592 | { | |
c50cade9 | 593 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
594 | |
595 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
596 | } | |
597 | ||
598 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
599 | { | |
89a8a5a6 RB |
600 | struct flush_tlb_data fd = { |
601 | .addr1 = start, | |
602 | .addr2 = end, | |
603 | }; | |
1da177e4 | 604 | |
15c8b6c1 | 605 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
606 | } |
607 | ||
608 | static void flush_tlb_page_ipi(void *info) | |
609 | { | |
c50cade9 | 610 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
611 | |
612 | local_flush_tlb_page(fd->vma, fd->addr1); | |
613 | } | |
614 | ||
615 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
616 | { | |
617 | preempt_disable(); | |
618 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
619 | struct flush_tlb_data fd = { |
620 | .vma = vma, | |
621 | .addr1 = page, | |
622 | }; | |
1da177e4 | 623 | |
c50cade9 | 624 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 625 | } else { |
b5eb5511 RB |
626 | unsigned int cpu; |
627 | ||
0b5f9c00 | 628 | for_each_online_cpu(cpu) { |
a05c3920 JH |
629 | /* |
630 | * flush_cache_page() only does partial flushes, so | |
631 | * invalidate ASID without it appearing to | |
632 | * has_valid_asid() as if mm has been completely unused | |
633 | * by that CPU. | |
634 | */ | |
0b5f9c00 | 635 | if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) |
a05c3920 | 636 | cpu_context(cpu, vma->vm_mm) = 1; |
0b5f9c00 | 637 | } |
1da177e4 LT |
638 | } |
639 | local_flush_tlb_page(vma, page); | |
640 | preempt_enable(); | |
641 | } | |
642 | ||
643 | static void flush_tlb_one_ipi(void *info) | |
644 | { | |
645 | unsigned long vaddr = (unsigned long) info; | |
646 | ||
647 | local_flush_tlb_one(vaddr); | |
648 | } | |
649 | ||
650 | void flush_tlb_one(unsigned long vaddr) | |
651 | { | |
25969354 | 652 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
653 | } |
654 | ||
655 | EXPORT_SYMBOL(flush_tlb_page); | |
656 | EXPORT_SYMBOL(flush_tlb_one); | |
7aa1c8f4 | 657 | |
cc7964af PB |
658 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
659 | ||
660 | static DEFINE_PER_CPU(atomic_t, tick_broadcast_count); | |
661 | static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd); | |
662 | ||
663 | void tick_broadcast(const struct cpumask *mask) | |
664 | { | |
665 | atomic_t *count; | |
666 | struct call_single_data *csd; | |
667 | int cpu; | |
668 | ||
669 | for_each_cpu(cpu, mask) { | |
670 | count = &per_cpu(tick_broadcast_count, cpu); | |
671 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
672 | ||
673 | if (atomic_inc_return(count) == 1) | |
674 | smp_call_function_single_async(cpu, csd); | |
675 | } | |
676 | } | |
677 | ||
678 | static void tick_broadcast_callee(void *info) | |
679 | { | |
680 | int cpu = smp_processor_id(); | |
681 | tick_receive_broadcast(); | |
682 | atomic_set(&per_cpu(tick_broadcast_count, cpu), 0); | |
683 | } | |
684 | ||
685 | static int __init tick_broadcast_init(void) | |
686 | { | |
687 | struct call_single_data *csd; | |
688 | int cpu; | |
689 | ||
690 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | |
691 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
692 | csd->func = tick_broadcast_callee; | |
693 | } | |
694 | ||
695 | return 0; | |
696 | } | |
697 | early_initcall(tick_broadcast_init); | |
698 | ||
699 | #endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */ |