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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/timex.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/cpumask.h> | |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
8f99a162 | 35 | #include <linux/ftrace.h> |
1da177e4 | 36 | |
60063497 | 37 | #include <linux/atomic.h> |
1da177e4 LT |
38 | #include <asm/cpu.h> |
39 | #include <asm/processor.h> | |
bdc92d74 | 40 | #include <asm/idle.h> |
39b8d525 | 41 | #include <asm/r4k-timer.h> |
1da177e4 | 42 | #include <asm/mmu_context.h> |
7bcf7717 | 43 | #include <asm/time.h> |
b81947c6 | 44 | #include <asm/setup.h> |
1da177e4 | 45 | |
cafb45b2 | 46 | cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
2dc2ae34 | 47 | |
1da177e4 | 48 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
2dc2ae34 DD |
49 | EXPORT_SYMBOL(__cpu_number_map); |
50 | ||
1da177e4 | 51 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
2dc2ae34 | 52 | EXPORT_SYMBOL(__cpu_logical_map); |
1da177e4 | 53 | |
0ab7aefc RB |
54 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
55 | int smp_num_siblings = 1; | |
56 | EXPORT_SYMBOL(smp_num_siblings); | |
57 | ||
58 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
59 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
60 | EXPORT_SYMBOL(cpu_sibling_map); | |
61 | ||
bda4584c HC |
62 | /* representing the core map of multi-core chips of each logical CPU */ |
63 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; | |
64 | EXPORT_SYMBOL(cpu_core_map); | |
65 | ||
cccf34e9 MC |
66 | /* |
67 | * A logcal cpu mask containing only one VPE per core to | |
68 | * reduce the number of IPIs on large MT systems. | |
69 | */ | |
70 | cpumask_t cpu_foreign_map __read_mostly; | |
71 | EXPORT_SYMBOL(cpu_foreign_map); | |
72 | ||
0ab7aefc RB |
73 | /* representing cpus for which sibling maps can be computed */ |
74 | static cpumask_t cpu_sibling_setup_map; | |
75 | ||
bda4584c HC |
76 | /* representing cpus for which core maps can be computed */ |
77 | static cpumask_t cpu_core_setup_map; | |
78 | ||
76306f42 PB |
79 | cpumask_t cpu_coherent_mask; |
80 | ||
0ab7aefc RB |
81 | static inline void set_cpu_sibling_map(int cpu) |
82 | { | |
83 | int i; | |
84 | ||
8dd92891 | 85 | cpumask_set_cpu(cpu, &cpu_sibling_setup_map); |
0ab7aefc RB |
86 | |
87 | if (smp_num_siblings > 1) { | |
8dd92891 | 88 | for_each_cpu(i, &cpu_sibling_setup_map) { |
bda4584c HC |
89 | if (cpu_data[cpu].package == cpu_data[i].package && |
90 | cpu_data[cpu].core == cpu_data[i].core) { | |
8dd92891 RR |
91 | cpumask_set_cpu(i, &cpu_sibling_map[cpu]); |
92 | cpumask_set_cpu(cpu, &cpu_sibling_map[i]); | |
0ab7aefc RB |
93 | } |
94 | } | |
95 | } else | |
8dd92891 | 96 | cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]); |
0ab7aefc RB |
97 | } |
98 | ||
bda4584c HC |
99 | static inline void set_cpu_core_map(int cpu) |
100 | { | |
101 | int i; | |
102 | ||
8dd92891 | 103 | cpumask_set_cpu(cpu, &cpu_core_setup_map); |
bda4584c | 104 | |
8dd92891 | 105 | for_each_cpu(i, &cpu_core_setup_map) { |
bda4584c | 106 | if (cpu_data[cpu].package == cpu_data[i].package) { |
8dd92891 RR |
107 | cpumask_set_cpu(i, &cpu_core_map[cpu]); |
108 | cpumask_set_cpu(cpu, &cpu_core_map[i]); | |
bda4584c HC |
109 | } |
110 | } | |
111 | } | |
112 | ||
cccf34e9 MC |
113 | /* |
114 | * Calculate a new cpu_foreign_map mask whenever a | |
115 | * new cpu appears or disappears. | |
116 | */ | |
117 | static inline void calculate_cpu_foreign_map(void) | |
118 | { | |
119 | int i, k, core_present; | |
120 | cpumask_t temp_foreign_map; | |
121 | ||
122 | /* Re-calculate the mask */ | |
123 | for_each_online_cpu(i) { | |
124 | core_present = 0; | |
125 | for_each_cpu(k, &temp_foreign_map) | |
126 | if (cpu_data[i].package == cpu_data[k].package && | |
127 | cpu_data[i].core == cpu_data[k].core) | |
128 | core_present = 1; | |
129 | if (!core_present) | |
130 | cpumask_set_cpu(i, &temp_foreign_map); | |
131 | } | |
132 | ||
133 | cpumask_copy(&cpu_foreign_map, &temp_foreign_map); | |
134 | } | |
135 | ||
87353d8a | 136 | struct plat_smp_ops *mp_ops; |
82d45de6 | 137 | EXPORT_SYMBOL(mp_ops); |
87353d8a | 138 | |
078a55fc | 139 | void register_smp_ops(struct plat_smp_ops *ops) |
87353d8a | 140 | { |
83738e30 TS |
141 | if (mp_ops) |
142 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
143 | |
144 | mp_ops = ops; | |
145 | } | |
146 | ||
1da177e4 LT |
147 | /* |
148 | * First C code run on the secondary CPUs after being started up by | |
149 | * the master. | |
150 | */ | |
078a55fc | 151 | asmlinkage void start_secondary(void) |
1da177e4 | 152 | { |
5bfb5d69 | 153 | unsigned int cpu; |
1da177e4 LT |
154 | |
155 | cpu_probe(); | |
6650df3c | 156 | per_cpu_trap_init(false); |
7bcf7717 | 157 | mips_clockevent_init(); |
87353d8a | 158 | mp_ops->init_secondary(); |
c7754e75 | 159 | cpu_report(); |
1da177e4 LT |
160 | |
161 | /* | |
162 | * XXX parity protection should be folded in here when it's converted | |
163 | * to an option instead of something based on .cputype | |
164 | */ | |
165 | ||
166 | calibrate_delay(); | |
5bfb5d69 NP |
167 | preempt_disable(); |
168 | cpu = smp_processor_id(); | |
1da177e4 LT |
169 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
170 | ||
8dd92891 | 171 | cpumask_set_cpu(cpu, &cpu_coherent_mask); |
e545a614 MS |
172 | notify_cpu_starting(cpu); |
173 | ||
b9a09a06 YZ |
174 | set_cpu_online(cpu, true); |
175 | ||
0ab7aefc | 176 | set_cpu_sibling_map(cpu); |
bda4584c | 177 | set_cpu_core_map(cpu); |
1da177e4 | 178 | |
cccf34e9 MC |
179 | calculate_cpu_foreign_map(); |
180 | ||
8dd92891 | 181 | cpumask_set_cpu(cpu, &cpu_callin_map); |
1da177e4 | 182 | |
cf9bfe55 | 183 | synchronise_count_slave(cpu); |
39b8d525 | 184 | |
b789ad63 YZ |
185 | /* |
186 | * irq will be enabled in ->smp_finish(), enabling it too early | |
187 | * is dangerous. | |
188 | */ | |
189 | WARN_ON_ONCE(!irqs_disabled()); | |
5309bdac YZ |
190 | mp_ops->smp_finish(); |
191 | ||
cdbedc61 | 192 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
193 | } |
194 | ||
1da177e4 LT |
195 | static void stop_this_cpu(void *dummy) |
196 | { | |
197 | /* | |
cccf34e9 MC |
198 | * Remove this CPU. Be a bit slow here and |
199 | * set the bits for every online CPU so we don't miss | |
200 | * any IPI whilst taking this VPE down. | |
1da177e4 | 201 | */ |
cccf34e9 MC |
202 | |
203 | cpumask_copy(&cpu_foreign_map, cpu_online_mask); | |
204 | ||
205 | /* Make it visible to every other CPU */ | |
206 | smp_mb(); | |
207 | ||
0b5f9c00 | 208 | set_cpu_online(smp_processor_id(), false); |
cccf34e9 | 209 | calculate_cpu_foreign_map(); |
ea925a72 AB |
210 | local_irq_disable(); |
211 | while (1); | |
1da177e4 LT |
212 | } |
213 | ||
214 | void smp_send_stop(void) | |
215 | { | |
8691e5a8 | 216 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
217 | } |
218 | ||
219 | void __init smp_cpus_done(unsigned int max_cpus) | |
220 | { | |
1da177e4 LT |
221 | } |
222 | ||
223 | /* called from main before smp_init() */ | |
224 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
225 | { | |
1da177e4 LT |
226 | init_new_context(current, &init_mm); |
227 | current_thread_info()->cpu = 0; | |
87353d8a | 228 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 229 | set_cpu_sibling_map(0); |
bda4584c | 230 | set_cpu_core_map(0); |
cccf34e9 | 231 | calculate_cpu_foreign_map(); |
320e6aba | 232 | #ifndef CONFIG_HOTPLUG_CPU |
0b5f9c00 | 233 | init_cpu_present(cpu_possible_mask); |
320e6aba | 234 | #endif |
76306f42 | 235 | cpumask_copy(&cpu_coherent_mask, cpu_possible_mask); |
1da177e4 LT |
236 | } |
237 | ||
238 | /* preload SMP state for boot cpu */ | |
28eb0e46 | 239 | void smp_prepare_boot_cpu(void) |
1da177e4 | 240 | { |
4037ac6e RR |
241 | set_cpu_possible(0, true); |
242 | set_cpu_online(0, true); | |
8dd92891 | 243 | cpumask_set_cpu(0, &cpu_callin_map); |
1da177e4 LT |
244 | } |
245 | ||
078a55fc | 246 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 247 | { |
360014a3 | 248 | mp_ops->boot_secondary(cpu, tidle); |
1da177e4 | 249 | |
b727a602 RB |
250 | /* |
251 | * Trust is futile. We should really have timeouts ... | |
252 | */ | |
cafb45b2 | 253 | while (!cpumask_test_cpu(cpu, &cpu_callin_map)) { |
1da177e4 | 254 | udelay(100); |
cafb45b2 RB |
255 | schedule(); |
256 | } | |
1da177e4 | 257 | |
cf9bfe55 | 258 | synchronise_count_master(cpu); |
1da177e4 LT |
259 | return 0; |
260 | } | |
261 | ||
1da177e4 LT |
262 | /* Not really SMP stuff ... */ |
263 | int setup_profiling_timer(unsigned int multiplier) | |
264 | { | |
265 | return 0; | |
266 | } | |
267 | ||
268 | static void flush_tlb_all_ipi(void *info) | |
269 | { | |
270 | local_flush_tlb_all(); | |
271 | } | |
272 | ||
273 | void flush_tlb_all(void) | |
274 | { | |
15c8b6c1 | 275 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
276 | } |
277 | ||
278 | static void flush_tlb_mm_ipi(void *mm) | |
279 | { | |
280 | local_flush_tlb_mm((struct mm_struct *)mm); | |
281 | } | |
282 | ||
25969354 RB |
283 | /* |
284 | * Special Variant of smp_call_function for use by TLB functions: | |
285 | * | |
286 | * o No return value | |
287 | * o collapses to normal function call on UP kernels | |
288 | * o collapses to normal function call on systems with a single shared | |
289 | * primary cache. | |
25969354 RB |
290 | */ |
291 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
292 | { | |
8691e5a8 | 293 | smp_call_function(func, info, 1); |
25969354 RB |
294 | } |
295 | ||
296 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
297 | { | |
298 | preempt_disable(); | |
299 | ||
300 | smp_on_other_tlbs(func, info); | |
301 | func(info); | |
302 | ||
303 | preempt_enable(); | |
304 | } | |
305 | ||
1da177e4 LT |
306 | /* |
307 | * The following tlb flush calls are invoked when old translations are | |
308 | * being torn down, or pte attributes are changing. For single threaded | |
309 | * address spaces, a new context is obtained on the current cpu, and tlb | |
310 | * context on other cpus are invalidated to force a new context allocation | |
311 | * at switch_mm time, should the mm ever be used on other cpus. For | |
312 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
313 | * Another case where intercpu interrupts are required is when the target | |
314 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
315 | * behalf of debugees, kswapd stealing pages from another process etc). | |
316 | * Kanoj 07/00. | |
317 | */ | |
318 | ||
319 | void flush_tlb_mm(struct mm_struct *mm) | |
320 | { | |
321 | preempt_disable(); | |
322 | ||
323 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 324 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 325 | } else { |
b5eb5511 RB |
326 | unsigned int cpu; |
327 | ||
0b5f9c00 RR |
328 | for_each_online_cpu(cpu) { |
329 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 330 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 331 | } |
1da177e4 LT |
332 | } |
333 | local_flush_tlb_mm(mm); | |
334 | ||
335 | preempt_enable(); | |
336 | } | |
337 | ||
338 | struct flush_tlb_data { | |
339 | struct vm_area_struct *vma; | |
340 | unsigned long addr1; | |
341 | unsigned long addr2; | |
342 | }; | |
343 | ||
344 | static void flush_tlb_range_ipi(void *info) | |
345 | { | |
c50cade9 | 346 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
347 | |
348 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
349 | } | |
350 | ||
351 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
352 | { | |
353 | struct mm_struct *mm = vma->vm_mm; | |
354 | ||
355 | preempt_disable(); | |
356 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
357 | struct flush_tlb_data fd = { |
358 | .vma = vma, | |
359 | .addr1 = start, | |
360 | .addr2 = end, | |
361 | }; | |
1da177e4 | 362 | |
c50cade9 | 363 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 364 | } else { |
b5eb5511 RB |
365 | unsigned int cpu; |
366 | ||
0b5f9c00 RR |
367 | for_each_online_cpu(cpu) { |
368 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 369 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 370 | } |
1da177e4 LT |
371 | } |
372 | local_flush_tlb_range(vma, start, end); | |
373 | preempt_enable(); | |
374 | } | |
375 | ||
376 | static void flush_tlb_kernel_range_ipi(void *info) | |
377 | { | |
c50cade9 | 378 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
379 | |
380 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
381 | } | |
382 | ||
383 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
384 | { | |
89a8a5a6 RB |
385 | struct flush_tlb_data fd = { |
386 | .addr1 = start, | |
387 | .addr2 = end, | |
388 | }; | |
1da177e4 | 389 | |
15c8b6c1 | 390 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
391 | } |
392 | ||
393 | static void flush_tlb_page_ipi(void *info) | |
394 | { | |
c50cade9 | 395 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
396 | |
397 | local_flush_tlb_page(fd->vma, fd->addr1); | |
398 | } | |
399 | ||
400 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
401 | { | |
402 | preempt_disable(); | |
403 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
404 | struct flush_tlb_data fd = { |
405 | .vma = vma, | |
406 | .addr1 = page, | |
407 | }; | |
1da177e4 | 408 | |
c50cade9 | 409 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 410 | } else { |
b5eb5511 RB |
411 | unsigned int cpu; |
412 | ||
0b5f9c00 RR |
413 | for_each_online_cpu(cpu) { |
414 | if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) | |
b5eb5511 | 415 | cpu_context(cpu, vma->vm_mm) = 0; |
0b5f9c00 | 416 | } |
1da177e4 LT |
417 | } |
418 | local_flush_tlb_page(vma, page); | |
419 | preempt_enable(); | |
420 | } | |
421 | ||
422 | static void flush_tlb_one_ipi(void *info) | |
423 | { | |
424 | unsigned long vaddr = (unsigned long) info; | |
425 | ||
426 | local_flush_tlb_one(vaddr); | |
427 | } | |
428 | ||
429 | void flush_tlb_one(unsigned long vaddr) | |
430 | { | |
25969354 | 431 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
432 | } |
433 | ||
434 | EXPORT_SYMBOL(flush_tlb_page); | |
435 | EXPORT_SYMBOL(flush_tlb_one); | |
7aa1c8f4 RB |
436 | |
437 | #if defined(CONFIG_KEXEC) | |
438 | void (*dump_ipi_function_ptr)(void *) = NULL; | |
439 | void dump_send_ipi(void (*dump_ipi_callback)(void *)) | |
440 | { | |
441 | int i; | |
442 | int cpu = smp_processor_id(); | |
443 | ||
444 | dump_ipi_function_ptr = dump_ipi_callback; | |
445 | smp_mb(); | |
446 | for_each_online_cpu(i) | |
447 | if (i != cpu) | |
448 | mp_ops->send_ipi_single(i, SMP_DUMP); | |
449 | ||
450 | } | |
451 | EXPORT_SYMBOL(dump_send_ipi); | |
452 | #endif | |
cc7964af PB |
453 | |
454 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST | |
455 | ||
456 | static DEFINE_PER_CPU(atomic_t, tick_broadcast_count); | |
457 | static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd); | |
458 | ||
459 | void tick_broadcast(const struct cpumask *mask) | |
460 | { | |
461 | atomic_t *count; | |
462 | struct call_single_data *csd; | |
463 | int cpu; | |
464 | ||
465 | for_each_cpu(cpu, mask) { | |
466 | count = &per_cpu(tick_broadcast_count, cpu); | |
467 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
468 | ||
469 | if (atomic_inc_return(count) == 1) | |
470 | smp_call_function_single_async(cpu, csd); | |
471 | } | |
472 | } | |
473 | ||
474 | static void tick_broadcast_callee(void *info) | |
475 | { | |
476 | int cpu = smp_processor_id(); | |
477 | tick_receive_broadcast(); | |
478 | atomic_set(&per_cpu(tick_broadcast_count, cpu), 0); | |
479 | } | |
480 | ||
481 | static int __init tick_broadcast_init(void) | |
482 | { | |
483 | struct call_single_data *csd; | |
484 | int cpu; | |
485 | ||
486 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | |
487 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
488 | csd->func = tick_broadcast_callee; | |
489 | } | |
490 | ||
491 | return 0; | |
492 | } | |
493 | early_initcall(tick_broadcast_init); | |
494 | ||
495 | #endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */ |