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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/timex.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/cpumask.h> | |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
8f99a162 | 35 | #include <linux/ftrace.h> |
1da177e4 | 36 | |
60063497 | 37 | #include <linux/atomic.h> |
1da177e4 LT |
38 | #include <asm/cpu.h> |
39 | #include <asm/processor.h> | |
39b8d525 | 40 | #include <asm/r4k-timer.h> |
1da177e4 | 41 | #include <asm/mmu_context.h> |
7bcf7717 | 42 | #include <asm/time.h> |
b81947c6 | 43 | #include <asm/setup.h> |
1da177e4 | 44 | |
41c594ab RB |
45 | #ifdef CONFIG_MIPS_MT_SMTC |
46 | #include <asm/mipsmtregs.h> | |
47 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
48 | ||
1b2bc75c | 49 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
2dc2ae34 | 50 | |
1da177e4 | 51 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
2dc2ae34 DD |
52 | EXPORT_SYMBOL(__cpu_number_map); |
53 | ||
1da177e4 | 54 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
2dc2ae34 | 55 | EXPORT_SYMBOL(__cpu_logical_map); |
1da177e4 | 56 | |
0ab7aefc RB |
57 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
58 | int smp_num_siblings = 1; | |
59 | EXPORT_SYMBOL(smp_num_siblings); | |
60 | ||
61 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
62 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
63 | EXPORT_SYMBOL(cpu_sibling_map); | |
64 | ||
65 | /* representing cpus for which sibling maps can be computed */ | |
66 | static cpumask_t cpu_sibling_setup_map; | |
67 | ||
68 | static inline void set_cpu_sibling_map(int cpu) | |
69 | { | |
70 | int i; | |
71 | ||
72 | cpu_set(cpu, cpu_sibling_setup_map); | |
73 | ||
74 | if (smp_num_siblings > 1) { | |
75 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
76 | if (cpu_data[cpu].core == cpu_data[i].core) { | |
77 | cpu_set(i, cpu_sibling_map[cpu]); | |
78 | cpu_set(cpu, cpu_sibling_map[i]); | |
79 | } | |
80 | } | |
81 | } else | |
82 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
83 | } | |
84 | ||
87353d8a RB |
85 | struct plat_smp_ops *mp_ops; |
86 | ||
87 | __cpuinit void register_smp_ops(struct plat_smp_ops *ops) | |
88 | { | |
83738e30 TS |
89 | if (mp_ops) |
90 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
91 | |
92 | mp_ops = ops; | |
93 | } | |
94 | ||
1da177e4 LT |
95 | /* |
96 | * First C code run on the secondary CPUs after being started up by | |
97 | * the master. | |
98 | */ | |
4ebd5233 | 99 | asmlinkage __cpuinit void start_secondary(void) |
1da177e4 | 100 | { |
5bfb5d69 | 101 | unsigned int cpu; |
1da177e4 | 102 | |
41c594ab RB |
103 | #ifdef CONFIG_MIPS_MT_SMTC |
104 | /* Only do cpu_probe for first TC of CPU */ | |
889a4c7b SH |
105 | if ((read_c0_tcbind() & TCBIND_CURTC) != 0) |
106 | __cpu_name[smp_processor_id()] = __cpu_name[0]; | |
107 | else | |
41c594ab | 108 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 LT |
109 | cpu_probe(); |
110 | cpu_report(); | |
6650df3c | 111 | per_cpu_trap_init(false); |
7bcf7717 | 112 | mips_clockevent_init(); |
87353d8a | 113 | mp_ops->init_secondary(); |
1da177e4 LT |
114 | |
115 | /* | |
116 | * XXX parity protection should be folded in here when it's converted | |
117 | * to an option instead of something based on .cputype | |
118 | */ | |
119 | ||
120 | calibrate_delay(); | |
5bfb5d69 NP |
121 | preempt_disable(); |
122 | cpu = smp_processor_id(); | |
1da177e4 LT |
123 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
124 | ||
e545a614 MS |
125 | notify_cpu_starting(cpu); |
126 | ||
b9a09a06 YZ |
127 | set_cpu_online(cpu, true); |
128 | ||
0ab7aefc | 129 | set_cpu_sibling_map(cpu); |
1da177e4 LT |
130 | |
131 | cpu_set(cpu, cpu_callin_map); | |
132 | ||
cf9bfe55 | 133 | synchronise_count_slave(cpu); |
39b8d525 | 134 | |
b789ad63 YZ |
135 | /* |
136 | * irq will be enabled in ->smp_finish(), enabling it too early | |
137 | * is dangerous. | |
138 | */ | |
139 | WARN_ON_ONCE(!irqs_disabled()); | |
5309bdac YZ |
140 | mp_ops->smp_finish(); |
141 | ||
1da177e4 LT |
142 | cpu_idle(); |
143 | } | |
144 | ||
2f304c0a JA |
145 | /* |
146 | * Call into both interrupt handlers, as we share the IPI for them | |
147 | */ | |
8f99a162 | 148 | void __irq_entry smp_call_function_interrupt(void) |
1da177e4 | 149 | { |
1da177e4 | 150 | irq_enter(); |
2f304c0a JA |
151 | generic_smp_call_function_single_interrupt(); |
152 | generic_smp_call_function_interrupt(); | |
1da177e4 | 153 | irq_exit(); |
b4b2917c PW |
154 | } |
155 | ||
1da177e4 LT |
156 | static void stop_this_cpu(void *dummy) |
157 | { | |
158 | /* | |
159 | * Remove this CPU: | |
160 | */ | |
0b5f9c00 | 161 | set_cpu_online(smp_processor_id(), false); |
7920c4d6 RB |
162 | for (;;) { |
163 | if (cpu_wait) | |
164 | (*cpu_wait)(); /* Wait if available. */ | |
165 | } | |
1da177e4 LT |
166 | } |
167 | ||
168 | void smp_send_stop(void) | |
169 | { | |
8691e5a8 | 170 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
171 | } |
172 | ||
173 | void __init smp_cpus_done(unsigned int max_cpus) | |
174 | { | |
87353d8a | 175 | mp_ops->cpus_done(); |
1da177e4 LT |
176 | } |
177 | ||
178 | /* called from main before smp_init() */ | |
179 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
180 | { | |
1da177e4 LT |
181 | init_new_context(current, &init_mm); |
182 | current_thread_info()->cpu = 0; | |
87353d8a | 183 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 184 | set_cpu_sibling_map(0); |
320e6aba | 185 | #ifndef CONFIG_HOTPLUG_CPU |
0b5f9c00 | 186 | init_cpu_present(cpu_possible_mask); |
320e6aba | 187 | #endif |
1da177e4 LT |
188 | } |
189 | ||
190 | /* preload SMP state for boot cpu */ | |
191 | void __devinit smp_prepare_boot_cpu(void) | |
192 | { | |
4037ac6e RR |
193 | set_cpu_possible(0, true); |
194 | set_cpu_online(0, true); | |
1da177e4 LT |
195 | cpu_set(0, cpu_callin_map); |
196 | } | |
197 | ||
8239c25f | 198 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 199 | { |
360014a3 | 200 | mp_ops->boot_secondary(cpu, tidle); |
1da177e4 | 201 | |
b727a602 RB |
202 | /* |
203 | * Trust is futile. We should really have timeouts ... | |
204 | */ | |
1da177e4 LT |
205 | while (!cpu_isset(cpu, cpu_callin_map)) |
206 | udelay(100); | |
1da177e4 | 207 | |
cf9bfe55 | 208 | synchronise_count_master(cpu); |
1da177e4 LT |
209 | return 0; |
210 | } | |
211 | ||
1da177e4 LT |
212 | /* Not really SMP stuff ... */ |
213 | int setup_profiling_timer(unsigned int multiplier) | |
214 | { | |
215 | return 0; | |
216 | } | |
217 | ||
218 | static void flush_tlb_all_ipi(void *info) | |
219 | { | |
220 | local_flush_tlb_all(); | |
221 | } | |
222 | ||
223 | void flush_tlb_all(void) | |
224 | { | |
15c8b6c1 | 225 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
226 | } |
227 | ||
228 | static void flush_tlb_mm_ipi(void *mm) | |
229 | { | |
230 | local_flush_tlb_mm((struct mm_struct *)mm); | |
231 | } | |
232 | ||
25969354 RB |
233 | /* |
234 | * Special Variant of smp_call_function for use by TLB functions: | |
235 | * | |
236 | * o No return value | |
237 | * o collapses to normal function call on UP kernels | |
238 | * o collapses to normal function call on systems with a single shared | |
239 | * primary cache. | |
240 | * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core. | |
241 | */ | |
242 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
243 | { | |
244 | #ifndef CONFIG_MIPS_MT_SMTC | |
8691e5a8 | 245 | smp_call_function(func, info, 1); |
25969354 RB |
246 | #endif |
247 | } | |
248 | ||
249 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
250 | { | |
251 | preempt_disable(); | |
252 | ||
253 | smp_on_other_tlbs(func, info); | |
254 | func(info); | |
255 | ||
256 | preempt_enable(); | |
257 | } | |
258 | ||
1da177e4 LT |
259 | /* |
260 | * The following tlb flush calls are invoked when old translations are | |
261 | * being torn down, or pte attributes are changing. For single threaded | |
262 | * address spaces, a new context is obtained on the current cpu, and tlb | |
263 | * context on other cpus are invalidated to force a new context allocation | |
264 | * at switch_mm time, should the mm ever be used on other cpus. For | |
265 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
266 | * Another case where intercpu interrupts are required is when the target | |
267 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
268 | * behalf of debugees, kswapd stealing pages from another process etc). | |
269 | * Kanoj 07/00. | |
270 | */ | |
271 | ||
272 | void flush_tlb_mm(struct mm_struct *mm) | |
273 | { | |
274 | preempt_disable(); | |
275 | ||
276 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 277 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 278 | } else { |
b5eb5511 RB |
279 | unsigned int cpu; |
280 | ||
0b5f9c00 RR |
281 | for_each_online_cpu(cpu) { |
282 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 283 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 284 | } |
1da177e4 LT |
285 | } |
286 | local_flush_tlb_mm(mm); | |
287 | ||
288 | preempt_enable(); | |
289 | } | |
290 | ||
291 | struct flush_tlb_data { | |
292 | struct vm_area_struct *vma; | |
293 | unsigned long addr1; | |
294 | unsigned long addr2; | |
295 | }; | |
296 | ||
297 | static void flush_tlb_range_ipi(void *info) | |
298 | { | |
c50cade9 | 299 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
300 | |
301 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
302 | } | |
303 | ||
304 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
305 | { | |
306 | struct mm_struct *mm = vma->vm_mm; | |
307 | ||
308 | preempt_disable(); | |
309 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
310 | struct flush_tlb_data fd = { |
311 | .vma = vma, | |
312 | .addr1 = start, | |
313 | .addr2 = end, | |
314 | }; | |
1da177e4 | 315 | |
c50cade9 | 316 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 317 | } else { |
b5eb5511 RB |
318 | unsigned int cpu; |
319 | ||
0b5f9c00 RR |
320 | for_each_online_cpu(cpu) { |
321 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 322 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 323 | } |
1da177e4 LT |
324 | } |
325 | local_flush_tlb_range(vma, start, end); | |
326 | preempt_enable(); | |
327 | } | |
328 | ||
329 | static void flush_tlb_kernel_range_ipi(void *info) | |
330 | { | |
c50cade9 | 331 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
332 | |
333 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
334 | } | |
335 | ||
336 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
337 | { | |
89a8a5a6 RB |
338 | struct flush_tlb_data fd = { |
339 | .addr1 = start, | |
340 | .addr2 = end, | |
341 | }; | |
1da177e4 | 342 | |
15c8b6c1 | 343 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
344 | } |
345 | ||
346 | static void flush_tlb_page_ipi(void *info) | |
347 | { | |
c50cade9 | 348 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
349 | |
350 | local_flush_tlb_page(fd->vma, fd->addr1); | |
351 | } | |
352 | ||
353 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
354 | { | |
355 | preempt_disable(); | |
356 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
357 | struct flush_tlb_data fd = { |
358 | .vma = vma, | |
359 | .addr1 = page, | |
360 | }; | |
1da177e4 | 361 | |
c50cade9 | 362 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 363 | } else { |
b5eb5511 RB |
364 | unsigned int cpu; |
365 | ||
0b5f9c00 RR |
366 | for_each_online_cpu(cpu) { |
367 | if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) | |
b5eb5511 | 368 | cpu_context(cpu, vma->vm_mm) = 0; |
0b5f9c00 | 369 | } |
1da177e4 LT |
370 | } |
371 | local_flush_tlb_page(vma, page); | |
372 | preempt_enable(); | |
373 | } | |
374 | ||
375 | static void flush_tlb_one_ipi(void *info) | |
376 | { | |
377 | unsigned long vaddr = (unsigned long) info; | |
378 | ||
379 | local_flush_tlb_one(vaddr); | |
380 | } | |
381 | ||
382 | void flush_tlb_one(unsigned long vaddr) | |
383 | { | |
25969354 | 384 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
385 | } |
386 | ||
387 | EXPORT_SYMBOL(flush_tlb_page); | |
388 | EXPORT_SYMBOL(flush_tlb_one); | |
7aa1c8f4 RB |
389 | |
390 | #if defined(CONFIG_KEXEC) | |
391 | void (*dump_ipi_function_ptr)(void *) = NULL; | |
392 | void dump_send_ipi(void (*dump_ipi_callback)(void *)) | |
393 | { | |
394 | int i; | |
395 | int cpu = smp_processor_id(); | |
396 | ||
397 | dump_ipi_function_ptr = dump_ipi_callback; | |
398 | smp_mb(); | |
399 | for_each_online_cpu(i) | |
400 | if (i != cpu) | |
401 | mp_ops->send_ipi_single(i, SMP_DUMP); | |
402 | ||
403 | } | |
404 | EXPORT_SYMBOL(dump_send_ipi); | |
405 | #endif |