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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
3b2396d9 | 12 | * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki |
1da177e4 LT |
13 | */ |
14 | #include <linux/config.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/smp_lock.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/kallsyms.h> | |
e01402b1 | 23 | #include <linux/bootmem.h> |
1da177e4 LT |
24 | |
25 | #include <asm/bootinfo.h> | |
26 | #include <asm/branch.h> | |
27 | #include <asm/break.h> | |
28 | #include <asm/cpu.h> | |
e50c0a8f | 29 | #include <asm/dsp.h> |
1da177e4 | 30 | #include <asm/fpu.h> |
340ee4b9 RB |
31 | #include <asm/mipsregs.h> |
32 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
33 | #include <asm/module.h> |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/ptrace.h> | |
36 | #include <asm/sections.h> | |
37 | #include <asm/system.h> | |
38 | #include <asm/tlbdebug.h> | |
39 | #include <asm/traps.h> | |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/mmu_context.h> | |
42 | #include <asm/watch.h> | |
43 | #include <asm/types.h> | |
44 | ||
e4ac58af | 45 | extern asmlinkage void handle_int(void); |
1da177e4 LT |
46 | extern asmlinkage void handle_tlbm(void); |
47 | extern asmlinkage void handle_tlbl(void); | |
48 | extern asmlinkage void handle_tlbs(void); | |
49 | extern asmlinkage void handle_adel(void); | |
50 | extern asmlinkage void handle_ades(void); | |
51 | extern asmlinkage void handle_ibe(void); | |
52 | extern asmlinkage void handle_dbe(void); | |
53 | extern asmlinkage void handle_sys(void); | |
54 | extern asmlinkage void handle_bp(void); | |
55 | extern asmlinkage void handle_ri(void); | |
56 | extern asmlinkage void handle_cpu(void); | |
57 | extern asmlinkage void handle_ov(void); | |
58 | extern asmlinkage void handle_tr(void); | |
59 | extern asmlinkage void handle_fpe(void); | |
60 | extern asmlinkage void handle_mdmx(void); | |
61 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 62 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 63 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
64 | extern asmlinkage void handle_mcheck(void); |
65 | extern asmlinkage void handle_reserved(void); | |
66 | ||
12616ed2 | 67 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
eae89076 | 68 | struct mips_fpu_struct *ctx); |
1da177e4 LT |
69 | |
70 | void (*board_be_init)(void); | |
71 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
72 | void (*board_nmi_handler_setup)(void); |
73 | void (*board_ejtag_handler_setup)(void); | |
74 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
1da177e4 LT |
75 | |
76 | /* | |
77 | * These constant is for searching for possible module text segments. | |
78 | * MODULE_RANGE is a guess of how much space is likely to be vmalloced. | |
79 | */ | |
80 | #define MODULE_RANGE (8*1024*1024) | |
81 | ||
82 | /* | |
83 | * This routine abuses get_user()/put_user() to reference pointers | |
84 | * with at least a bit of error checking ... | |
85 | */ | |
86 | void show_stack(struct task_struct *task, unsigned long *sp) | |
87 | { | |
88 | const int field = 2 * sizeof(unsigned long); | |
89 | long stackdata; | |
90 | int i; | |
91 | ||
92 | if (!sp) { | |
93 | if (task && task != current) | |
94 | sp = (unsigned long *) task->thread.reg29; | |
95 | else | |
96 | sp = (unsigned long *) &sp; | |
97 | } | |
98 | ||
99 | printk("Stack :"); | |
100 | i = 0; | |
101 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
102 | if (i && ((i % (64 / field)) == 0)) | |
103 | printk("\n "); | |
104 | if (i > 39) { | |
105 | printk(" ..."); | |
106 | break; | |
107 | } | |
108 | ||
109 | if (__get_user(stackdata, sp++)) { | |
110 | printk(" (Bad stack address)"); | |
111 | break; | |
112 | } | |
113 | ||
114 | printk(" %0*lx", field, stackdata); | |
115 | i++; | |
116 | } | |
117 | printk("\n"); | |
118 | } | |
119 | ||
120 | void show_trace(struct task_struct *task, unsigned long *stack) | |
121 | { | |
122 | const int field = 2 * sizeof(unsigned long); | |
123 | unsigned long addr; | |
124 | ||
125 | if (!stack) { | |
126 | if (task && task != current) | |
127 | stack = (unsigned long *) task->thread.reg29; | |
128 | else | |
129 | stack = (unsigned long *) &stack; | |
130 | } | |
131 | ||
132 | printk("Call Trace:"); | |
133 | #ifdef CONFIG_KALLSYMS | |
134 | printk("\n"); | |
135 | #endif | |
136 | while (!kstack_end(stack)) { | |
137 | addr = *stack++; | |
138 | if (__kernel_text_address(addr)) { | |
139 | printk(" [<%0*lx>] ", field, addr); | |
140 | print_symbol("%s\n", addr); | |
141 | } | |
142 | } | |
143 | printk("\n"); | |
144 | } | |
145 | ||
146 | /* | |
147 | * The architecture-independent dump_stack generator | |
148 | */ | |
149 | void dump_stack(void) | |
150 | { | |
151 | unsigned long stack; | |
152 | ||
153 | show_trace(current, &stack); | |
154 | } | |
155 | ||
156 | EXPORT_SYMBOL(dump_stack); | |
157 | ||
158 | void show_code(unsigned int *pc) | |
159 | { | |
160 | long i; | |
161 | ||
162 | printk("\nCode:"); | |
163 | ||
164 | for(i = -3 ; i < 6 ; i++) { | |
165 | unsigned int insn; | |
166 | if (__get_user(insn, pc + i)) { | |
167 | printk(" (Bad address in epc)\n"); | |
168 | break; | |
169 | } | |
170 | printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); | |
171 | } | |
172 | } | |
173 | ||
174 | void show_regs(struct pt_regs *regs) | |
175 | { | |
176 | const int field = 2 * sizeof(unsigned long); | |
177 | unsigned int cause = regs->cp0_cause; | |
178 | int i; | |
179 | ||
180 | printk("Cpu %d\n", smp_processor_id()); | |
181 | ||
182 | /* | |
183 | * Saved main processor registers | |
184 | */ | |
185 | for (i = 0; i < 32; ) { | |
186 | if ((i % 4) == 0) | |
187 | printk("$%2d :", i); | |
188 | if (i == 0) | |
189 | printk(" %0*lx", field, 0UL); | |
190 | else if (i == 26 || i == 27) | |
191 | printk(" %*s", field, ""); | |
192 | else | |
193 | printk(" %0*lx", field, regs->regs[i]); | |
194 | ||
195 | i++; | |
196 | if ((i % 4) == 0) | |
197 | printk("\n"); | |
198 | } | |
199 | ||
200 | printk("Hi : %0*lx\n", field, regs->hi); | |
201 | printk("Lo : %0*lx\n", field, regs->lo); | |
202 | ||
203 | /* | |
204 | * Saved cp0 registers | |
205 | */ | |
206 | printk("epc : %0*lx ", field, regs->cp0_epc); | |
207 | print_symbol("%s ", regs->cp0_epc); | |
208 | printk(" %s\n", print_tainted()); | |
209 | printk("ra : %0*lx ", field, regs->regs[31]); | |
210 | print_symbol("%s\n", regs->regs[31]); | |
211 | ||
212 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
213 | ||
3b2396d9 MR |
214 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
215 | if (regs->cp0_status & ST0_KUO) | |
216 | printk("KUo "); | |
217 | if (regs->cp0_status & ST0_IEO) | |
218 | printk("IEo "); | |
219 | if (regs->cp0_status & ST0_KUP) | |
220 | printk("KUp "); | |
221 | if (regs->cp0_status & ST0_IEP) | |
222 | printk("IEp "); | |
223 | if (regs->cp0_status & ST0_KUC) | |
224 | printk("KUc "); | |
225 | if (regs->cp0_status & ST0_IEC) | |
226 | printk("IEc "); | |
227 | } else { | |
228 | if (regs->cp0_status & ST0_KX) | |
229 | printk("KX "); | |
230 | if (regs->cp0_status & ST0_SX) | |
231 | printk("SX "); | |
232 | if (regs->cp0_status & ST0_UX) | |
233 | printk("UX "); | |
234 | switch (regs->cp0_status & ST0_KSU) { | |
235 | case KSU_USER: | |
236 | printk("USER "); | |
237 | break; | |
238 | case KSU_SUPERVISOR: | |
239 | printk("SUPERVISOR "); | |
240 | break; | |
241 | case KSU_KERNEL: | |
242 | printk("KERNEL "); | |
243 | break; | |
244 | default: | |
245 | printk("BAD_MODE "); | |
246 | break; | |
247 | } | |
248 | if (regs->cp0_status & ST0_ERL) | |
249 | printk("ERL "); | |
250 | if (regs->cp0_status & ST0_EXL) | |
251 | printk("EXL "); | |
252 | if (regs->cp0_status & ST0_IE) | |
253 | printk("IE "); | |
1da177e4 | 254 | } |
1da177e4 LT |
255 | printk("\n"); |
256 | ||
257 | printk("Cause : %08x\n", cause); | |
258 | ||
259 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
260 | if (1 <= cause && cause <= 5) | |
261 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
262 | ||
263 | printk("PrId : %08x\n", read_c0_prid()); | |
264 | } | |
265 | ||
266 | void show_registers(struct pt_regs *regs) | |
267 | { | |
268 | show_regs(regs); | |
269 | print_modules(); | |
270 | printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", | |
271 | current->comm, current->pid, current_thread_info(), current); | |
272 | show_stack(current, (long *) regs->regs[29]); | |
273 | show_trace(current, (long *) regs->regs[29]); | |
274 | show_code((unsigned int *) regs->cp0_epc); | |
275 | printk("\n"); | |
276 | } | |
277 | ||
278 | static DEFINE_SPINLOCK(die_lock); | |
279 | ||
178086c8 | 280 | NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs) |
1da177e4 LT |
281 | { |
282 | static int die_counter; | |
41c594ab RB |
283 | #ifdef CONFIG_MIPS_MT_SMTC |
284 | unsigned long dvpret = dvpe(); | |
285 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
286 | |
287 | console_verbose(); | |
288 | spin_lock_irq(&die_lock); | |
41c594ab RB |
289 | bust_spinlocks(1); |
290 | #ifdef CONFIG_MIPS_MT_SMTC | |
291 | mips_mt_regdump(dvpret); | |
292 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
178086c8 | 293 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 LT |
294 | show_registers(regs); |
295 | spin_unlock_irq(&die_lock); | |
296 | do_exit(SIGSEGV); | |
297 | } | |
298 | ||
1da177e4 LT |
299 | extern const struct exception_table_entry __start___dbe_table[]; |
300 | extern const struct exception_table_entry __stop___dbe_table[]; | |
301 | ||
302 | void __declare_dbe_table(void) | |
303 | { | |
304 | __asm__ __volatile__( | |
305 | ".section\t__dbe_table,\"a\"\n\t" | |
306 | ".previous" | |
307 | ); | |
308 | } | |
309 | ||
310 | /* Given an address, look for it in the exception tables. */ | |
311 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
312 | { | |
313 | const struct exception_table_entry *e; | |
314 | ||
315 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
316 | if (!e) | |
317 | e = search_module_dbetables(addr); | |
318 | return e; | |
319 | } | |
320 | ||
321 | asmlinkage void do_be(struct pt_regs *regs) | |
322 | { | |
323 | const int field = 2 * sizeof(unsigned long); | |
324 | const struct exception_table_entry *fixup = NULL; | |
325 | int data = regs->cp0_cause & 4; | |
326 | int action = MIPS_BE_FATAL; | |
327 | ||
328 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
329 | if (data && !user_mode(regs)) | |
330 | fixup = search_dbe_tables(exception_epc(regs)); | |
331 | ||
332 | if (fixup) | |
333 | action = MIPS_BE_FIXUP; | |
334 | ||
335 | if (board_be_handler) | |
336 | action = board_be_handler(regs, fixup != 0); | |
337 | ||
338 | switch (action) { | |
339 | case MIPS_BE_DISCARD: | |
340 | return; | |
341 | case MIPS_BE_FIXUP: | |
342 | if (fixup) { | |
343 | regs->cp0_epc = fixup->nextinsn; | |
344 | return; | |
345 | } | |
346 | break; | |
347 | default: | |
348 | break; | |
349 | } | |
350 | ||
351 | /* | |
352 | * Assume it would be too dangerous to continue ... | |
353 | */ | |
354 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
355 | data ? "Data" : "Instruction", | |
356 | field, regs->cp0_epc, field, regs->regs[31]); | |
357 | die_if_kernel("Oops", regs); | |
358 | force_sig(SIGBUS, current); | |
359 | } | |
360 | ||
361 | static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) | |
362 | { | |
fe00f943 | 363 | unsigned int __user *epc; |
1da177e4 | 364 | |
fe00f943 | 365 | epc = (unsigned int __user *) regs->cp0_epc + |
1da177e4 LT |
366 | ((regs->cp0_cause & CAUSEF_BD) != 0); |
367 | if (!get_user(*opcode, epc)) | |
368 | return 0; | |
369 | ||
370 | force_sig(SIGSEGV, current); | |
371 | return 1; | |
372 | } | |
373 | ||
374 | /* | |
375 | * ll/sc emulation | |
376 | */ | |
377 | ||
378 | #define OPCODE 0xfc000000 | |
379 | #define BASE 0x03e00000 | |
380 | #define RT 0x001f0000 | |
381 | #define OFFSET 0x0000ffff | |
382 | #define LL 0xc0000000 | |
383 | #define SC 0xe0000000 | |
3c37026d RB |
384 | #define SPEC3 0x7c000000 |
385 | #define RD 0x0000f800 | |
386 | #define FUNC 0x0000003f | |
387 | #define RDHWR 0x0000003b | |
1da177e4 LT |
388 | |
389 | /* | |
390 | * The ll_bit is cleared by r*_switch.S | |
391 | */ | |
392 | ||
393 | unsigned long ll_bit; | |
394 | ||
395 | static struct task_struct *ll_task = NULL; | |
396 | ||
397 | static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) | |
398 | { | |
fe00f943 | 399 | unsigned long value, __user *vaddr; |
1da177e4 LT |
400 | long offset; |
401 | int signal = 0; | |
402 | ||
403 | /* | |
404 | * analyse the ll instruction that just caused a ri exception | |
405 | * and put the referenced address to addr. | |
406 | */ | |
407 | ||
408 | /* sign extend offset */ | |
409 | offset = opcode & OFFSET; | |
410 | offset <<= 16; | |
411 | offset >>= 16; | |
412 | ||
fe00f943 RB |
413 | vaddr = (unsigned long __user *) |
414 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
415 | |
416 | if ((unsigned long)vaddr & 3) { | |
417 | signal = SIGBUS; | |
418 | goto sig; | |
419 | } | |
420 | if (get_user(value, vaddr)) { | |
421 | signal = SIGSEGV; | |
422 | goto sig; | |
423 | } | |
424 | ||
425 | preempt_disable(); | |
426 | ||
427 | if (ll_task == NULL || ll_task == current) { | |
428 | ll_bit = 1; | |
429 | } else { | |
430 | ll_bit = 0; | |
431 | } | |
432 | ll_task = current; | |
433 | ||
434 | preempt_enable(); | |
435 | ||
6dd04688 RB |
436 | compute_return_epc(regs); |
437 | ||
1da177e4 LT |
438 | regs->regs[(opcode & RT) >> 16] = value; |
439 | ||
1da177e4 LT |
440 | return; |
441 | ||
442 | sig: | |
443 | force_sig(signal, current); | |
444 | } | |
445 | ||
446 | static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) | |
447 | { | |
fe00f943 RB |
448 | unsigned long __user *vaddr; |
449 | unsigned long reg; | |
1da177e4 LT |
450 | long offset; |
451 | int signal = 0; | |
452 | ||
453 | /* | |
454 | * analyse the sc instruction that just caused a ri exception | |
455 | * and put the referenced address to addr. | |
456 | */ | |
457 | ||
458 | /* sign extend offset */ | |
459 | offset = opcode & OFFSET; | |
460 | offset <<= 16; | |
461 | offset >>= 16; | |
462 | ||
fe00f943 RB |
463 | vaddr = (unsigned long __user *) |
464 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
465 | reg = (opcode & RT) >> 16; |
466 | ||
467 | if ((unsigned long)vaddr & 3) { | |
468 | signal = SIGBUS; | |
469 | goto sig; | |
470 | } | |
471 | ||
472 | preempt_disable(); | |
473 | ||
474 | if (ll_bit == 0 || ll_task != current) { | |
05b8042a | 475 | compute_return_epc(regs); |
1da177e4 LT |
476 | regs->regs[reg] = 0; |
477 | preempt_enable(); | |
1da177e4 LT |
478 | return; |
479 | } | |
480 | ||
481 | preempt_enable(); | |
482 | ||
483 | if (put_user(regs->regs[reg], vaddr)) { | |
484 | signal = SIGSEGV; | |
485 | goto sig; | |
486 | } | |
487 | ||
6dd04688 | 488 | compute_return_epc(regs); |
1da177e4 LT |
489 | regs->regs[reg] = 1; |
490 | ||
1da177e4 LT |
491 | return; |
492 | ||
493 | sig: | |
494 | force_sig(signal, current); | |
495 | } | |
496 | ||
497 | /* | |
498 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
499 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
500 | * executed on ll/sc-less processors. That's the theory. In practice a | |
501 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
502 | * instead, so we're doing the emulation thing in both exception handlers. | |
503 | */ | |
504 | static inline int simulate_llsc(struct pt_regs *regs) | |
505 | { | |
506 | unsigned int opcode; | |
507 | ||
508 | if (unlikely(get_insn_opcode(regs, &opcode))) | |
509 | return -EFAULT; | |
510 | ||
511 | if ((opcode & OPCODE) == LL) { | |
512 | simulate_ll(regs, opcode); | |
513 | return 0; | |
514 | } | |
515 | if ((opcode & OPCODE) == SC) { | |
516 | simulate_sc(regs, opcode); | |
517 | return 0; | |
518 | } | |
519 | ||
520 | return -EFAULT; /* Strange things going on ... */ | |
521 | } | |
522 | ||
3c37026d RB |
523 | /* |
524 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
525 | * registers not implemented in hardware. The only current use of this | |
526 | * is the thread area pointer. | |
527 | */ | |
528 | static inline int simulate_rdhwr(struct pt_regs *regs) | |
529 | { | |
dc8f6029 | 530 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
531 | unsigned int opcode; |
532 | ||
533 | if (unlikely(get_insn_opcode(regs, &opcode))) | |
534 | return -EFAULT; | |
535 | ||
536 | if (unlikely(compute_return_epc(regs))) | |
537 | return -EFAULT; | |
538 | ||
539 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
540 | int rd = (opcode & RD) >> 11; | |
541 | int rt = (opcode & RT) >> 16; | |
542 | switch (rd) { | |
543 | case 29: | |
544 | regs->regs[rt] = ti->tp_value; | |
56ebd51b | 545 | return 0; |
3c37026d RB |
546 | default: |
547 | return -EFAULT; | |
548 | } | |
549 | } | |
550 | ||
56ebd51b DJ |
551 | /* Not ours. */ |
552 | return -EFAULT; | |
3c37026d RB |
553 | } |
554 | ||
1da177e4 LT |
555 | asmlinkage void do_ov(struct pt_regs *regs) |
556 | { | |
557 | siginfo_t info; | |
558 | ||
36ccf1c0 RB |
559 | die_if_kernel("Integer overflow", regs); |
560 | ||
1da177e4 LT |
561 | info.si_code = FPE_INTOVF; |
562 | info.si_signo = SIGFPE; | |
563 | info.si_errno = 0; | |
fe00f943 | 564 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
565 | force_sig_info(SIGFPE, &info, current); |
566 | } | |
567 | ||
568 | /* | |
569 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
570 | */ | |
571 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
572 | { | |
573 | if (fcr31 & FPU_CSR_UNI_X) { | |
574 | int sig; | |
575 | ||
576 | preempt_disable(); | |
577 | ||
cd21dfcf RB |
578 | #ifdef CONFIG_PREEMPT |
579 | if (!is_fpu_owner()) { | |
580 | /* We might lose fpu before disabling preempt... */ | |
581 | own_fpu(); | |
582 | BUG_ON(!used_math()); | |
583 | restore_fp(current); | |
584 | } | |
585 | #endif | |
1da177e4 | 586 | /* |
a3dddd56 | 587 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
588 | * software emulator on-board, let's use it... |
589 | * | |
590 | * Force FPU to dump state into task/thread context. We're | |
591 | * moving a lot of data here for what is probably a single | |
592 | * instruction, but the alternative is to pre-decode the FP | |
593 | * register operands before invoking the emulator, which seems | |
594 | * a bit extreme for what should be an infrequent event. | |
595 | */ | |
596 | save_fp(current); | |
cd21dfcf RB |
597 | /* Ensure 'resume' not overwrite saved fp context again. */ |
598 | lose_fpu(); | |
599 | ||
600 | preempt_enable(); | |
1da177e4 LT |
601 | |
602 | /* Run the emulator */ | |
eae89076 | 603 | sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu); |
1da177e4 | 604 | |
cd21dfcf RB |
605 | preempt_disable(); |
606 | ||
607 | own_fpu(); /* Using the FPU again. */ | |
1da177e4 LT |
608 | /* |
609 | * We can't allow the emulated instruction to leave any of | |
610 | * the cause bit set in $fcr31. | |
611 | */ | |
eae89076 | 612 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
613 | |
614 | /* Restore the hardware register state */ | |
615 | restore_fp(current); | |
616 | ||
617 | preempt_enable(); | |
618 | ||
619 | /* If something went wrong, signal */ | |
620 | if (sig) | |
621 | force_sig(sig, current); | |
622 | ||
623 | return; | |
624 | } | |
625 | ||
626 | force_sig(SIGFPE, current); | |
627 | } | |
628 | ||
629 | asmlinkage void do_bp(struct pt_regs *regs) | |
630 | { | |
631 | unsigned int opcode, bcode; | |
632 | siginfo_t info; | |
633 | ||
634 | die_if_kernel("Break instruction in kernel code", regs); | |
635 | ||
636 | if (get_insn_opcode(regs, &opcode)) | |
637 | return; | |
638 | ||
639 | /* | |
640 | * There is the ancient bug in the MIPS assemblers that the break | |
641 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
642 | * Gas is bug-compatible, but not always, grrr... | |
643 | * We handle both cases with a simple heuristics. --macro | |
644 | */ | |
645 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
646 | if (bcode < (1 << 10)) | |
647 | bcode <<= 10; | |
648 | ||
649 | /* | |
650 | * (A short test says that IRIX 5.3 sends SIGTRAP for all break | |
651 | * insns, even for break codes that indicate arithmetic failures. | |
652 | * Weird ...) | |
653 | * But should we continue the brokenness??? --macro | |
654 | */ | |
655 | switch (bcode) { | |
656 | case BRK_OVERFLOW << 10: | |
657 | case BRK_DIVZERO << 10: | |
658 | if (bcode == (BRK_DIVZERO << 10)) | |
659 | info.si_code = FPE_INTDIV; | |
660 | else | |
661 | info.si_code = FPE_INTOVF; | |
662 | info.si_signo = SIGFPE; | |
663 | info.si_errno = 0; | |
fe00f943 | 664 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
665 | force_sig_info(SIGFPE, &info, current); |
666 | break; | |
667 | default: | |
668 | force_sig(SIGTRAP, current); | |
669 | } | |
670 | } | |
671 | ||
672 | asmlinkage void do_tr(struct pt_regs *regs) | |
673 | { | |
674 | unsigned int opcode, tcode = 0; | |
675 | siginfo_t info; | |
676 | ||
677 | die_if_kernel("Trap instruction in kernel code", regs); | |
678 | ||
679 | if (get_insn_opcode(regs, &opcode)) | |
680 | return; | |
681 | ||
682 | /* Immediate versions don't provide a code. */ | |
683 | if (!(opcode & OPCODE)) | |
684 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
685 | ||
686 | /* | |
687 | * (A short test says that IRIX 5.3 sends SIGTRAP for all trap | |
688 | * insns, even for trap codes that indicate arithmetic failures. | |
689 | * Weird ...) | |
690 | * But should we continue the brokenness??? --macro | |
691 | */ | |
692 | switch (tcode) { | |
693 | case BRK_OVERFLOW: | |
694 | case BRK_DIVZERO: | |
695 | if (tcode == BRK_DIVZERO) | |
696 | info.si_code = FPE_INTDIV; | |
697 | else | |
698 | info.si_code = FPE_INTOVF; | |
699 | info.si_signo = SIGFPE; | |
700 | info.si_errno = 0; | |
fe00f943 | 701 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
702 | force_sig_info(SIGFPE, &info, current); |
703 | break; | |
704 | default: | |
705 | force_sig(SIGTRAP, current); | |
706 | } | |
707 | } | |
708 | ||
709 | asmlinkage void do_ri(struct pt_regs *regs) | |
710 | { | |
711 | die_if_kernel("Reserved instruction in kernel code", regs); | |
712 | ||
713 | if (!cpu_has_llsc) | |
714 | if (!simulate_llsc(regs)) | |
715 | return; | |
716 | ||
3c37026d RB |
717 | if (!simulate_rdhwr(regs)) |
718 | return; | |
719 | ||
1da177e4 LT |
720 | force_sig(SIGILL, current); |
721 | } | |
722 | ||
723 | asmlinkage void do_cpu(struct pt_regs *regs) | |
724 | { | |
725 | unsigned int cpid; | |
726 | ||
727 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
728 | ||
729 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; | |
730 | ||
731 | switch (cpid) { | |
732 | case 0: | |
3c37026d RB |
733 | if (!cpu_has_llsc) |
734 | if (!simulate_llsc(regs)) | |
735 | return; | |
1da177e4 | 736 | |
3c37026d | 737 | if (!simulate_rdhwr(regs)) |
1da177e4 | 738 | return; |
3c37026d | 739 | |
1da177e4 LT |
740 | break; |
741 | ||
742 | case 1: | |
743 | preempt_disable(); | |
744 | ||
745 | own_fpu(); | |
746 | if (used_math()) { /* Using the FPU again. */ | |
747 | restore_fp(current); | |
748 | } else { /* First time FPU user. */ | |
749 | init_fpu(); | |
750 | set_used_math(); | |
751 | } | |
752 | ||
cd21dfcf RB |
753 | preempt_enable(); |
754 | ||
1da177e4 | 755 | if (!cpu_has_fpu) { |
12616ed2 | 756 | int sig = fpu_emulator_cop1Handler(regs, |
eae89076 | 757 | ¤t->thread.fpu); |
1da177e4 LT |
758 | if (sig) |
759 | force_sig(sig, current); | |
f088fc84 RB |
760 | #ifdef CONFIG_MIPS_MT_FPAFF |
761 | else { | |
762 | /* | |
763 | * MIPS MT processors may have fewer FPU contexts | |
764 | * than CPU threads. If we've emulated more than | |
765 | * some threshold number of instructions, force | |
766 | * migration to a "CPU" that has FP support. | |
767 | */ | |
768 | if(mt_fpemul_threshold > 0 | |
769 | && ((current->thread.emulated_fp++ | |
770 | > mt_fpemul_threshold))) { | |
771 | /* | |
772 | * If there's no FPU present, or if the | |
773 | * application has already restricted | |
774 | * the allowed set to exclude any CPUs | |
775 | * with FPUs, we'll skip the procedure. | |
776 | */ | |
777 | if (cpus_intersects(current->cpus_allowed, | |
778 | mt_fpu_cpumask)) { | |
779 | cpumask_t tmask; | |
780 | ||
781 | cpus_and(tmask, | |
782 | current->thread.user_cpus_allowed, | |
783 | mt_fpu_cpumask); | |
784 | set_cpus_allowed(current, tmask); | |
785 | current->thread.mflags |= MF_FPUBOUND; | |
786 | } | |
787 | } | |
788 | } | |
789 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
1da177e4 LT |
790 | } |
791 | ||
1da177e4 LT |
792 | return; |
793 | ||
794 | case 2: | |
795 | case 3: | |
41c594ab | 796 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
1da177e4 LT |
797 | break; |
798 | } | |
799 | ||
800 | force_sig(SIGILL, current); | |
801 | } | |
802 | ||
803 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
804 | { | |
805 | force_sig(SIGILL, current); | |
806 | } | |
807 | ||
808 | asmlinkage void do_watch(struct pt_regs *regs) | |
809 | { | |
810 | /* | |
811 | * We use the watch exception where available to detect stack | |
812 | * overflows. | |
813 | */ | |
814 | dump_tlb_all(); | |
815 | show_regs(regs); | |
816 | panic("Caught WATCH exception - probably caused by stack overflow."); | |
817 | } | |
818 | ||
819 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
820 | { | |
cac4bcbc RB |
821 | const int field = 2 * sizeof(unsigned long); |
822 | int multi_match = regs->cp0_status & ST0_TS; | |
823 | ||
1da177e4 | 824 | show_regs(regs); |
cac4bcbc RB |
825 | |
826 | if (multi_match) { | |
827 | printk("Index : %0x\n", read_c0_index()); | |
828 | printk("Pagemask: %0x\n", read_c0_pagemask()); | |
829 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
830 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
831 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
832 | printk("\n"); | |
833 | dump_tlb_all(); | |
834 | } | |
835 | ||
836 | show_code((unsigned int *) regs->cp0_epc); | |
837 | ||
1da177e4 LT |
838 | /* |
839 | * Some chips may have other causes of machine check (e.g. SB1 | |
840 | * graduation timer) | |
841 | */ | |
842 | panic("Caught Machine Check exception - %scaused by multiple " | |
843 | "matching entries in the TLB.", | |
cac4bcbc | 844 | (multi_match) ? "" : "not "); |
1da177e4 LT |
845 | } |
846 | ||
340ee4b9 RB |
847 | asmlinkage void do_mt(struct pt_regs *regs) |
848 | { | |
41c594ab RB |
849 | int subcode; |
850 | ||
851 | die_if_kernel("MIPS MT Thread exception in kernel", regs); | |
852 | ||
853 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) | |
854 | >> VPECONTROL_EXCPT_SHIFT; | |
855 | switch (subcode) { | |
856 | case 0: | |
857 | printk(KERN_ERR "Thread Underflow\n"); | |
858 | break; | |
859 | case 1: | |
860 | printk(KERN_ERR "Thread Overflow\n"); | |
861 | break; | |
862 | case 2: | |
863 | printk(KERN_ERR "Invalid YIELD Qualifier\n"); | |
864 | break; | |
865 | case 3: | |
866 | printk(KERN_ERR "Gating Storage Exception\n"); | |
867 | break; | |
868 | case 4: | |
869 | printk(KERN_ERR "YIELD Scheduler Exception\n"); | |
870 | break; | |
871 | case 5: | |
872 | printk(KERN_ERR "Gating Storage Schedulier Exception\n"); | |
873 | break; | |
874 | default: | |
875 | printk(KERN_ERR "*** UNKNOWN THREAD EXCEPTION %d ***\n", | |
876 | subcode); | |
877 | break; | |
878 | } | |
340ee4b9 RB |
879 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
880 | ||
881 | force_sig(SIGILL, current); | |
882 | } | |
883 | ||
884 | ||
e50c0a8f RB |
885 | asmlinkage void do_dsp(struct pt_regs *regs) |
886 | { | |
887 | if (cpu_has_dsp) | |
888 | panic("Unexpected DSP exception\n"); | |
889 | ||
890 | force_sig(SIGILL, current); | |
891 | } | |
892 | ||
1da177e4 LT |
893 | asmlinkage void do_reserved(struct pt_regs *regs) |
894 | { | |
895 | /* | |
896 | * Game over - no way to handle this if it ever occurs. Most probably | |
897 | * caused by a new unknown cpu type or after another deadly | |
898 | * hard/software error. | |
899 | */ | |
900 | show_regs(regs); | |
901 | panic("Caught reserved exception %ld - should not happen.", | |
902 | (regs->cp0_cause & 0x7f) >> 2); | |
903 | } | |
904 | ||
e01402b1 RB |
905 | asmlinkage void do_default_vi(struct pt_regs *regs) |
906 | { | |
907 | show_regs(regs); | |
908 | panic("Caught unexpected vectored interrupt."); | |
909 | } | |
910 | ||
1da177e4 LT |
911 | /* |
912 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
913 | * it different ways. | |
914 | */ | |
915 | static inline void parity_protection_init(void) | |
916 | { | |
917 | switch (current_cpu_data.cputype) { | |
918 | case CPU_24K: | |
98a41de9 | 919 | case CPU_34K: |
1da177e4 | 920 | case CPU_5KC: |
14f18b7f RB |
921 | write_c0_ecc(0x80000000); |
922 | back_to_back_c0_hazard(); | |
923 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
924 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
925 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
926 | break; |
927 | case CPU_20KC: | |
928 | case CPU_25KF: | |
929 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
930 | printk(KERN_INFO "Enable cache parity protection for " | |
931 | "MIPS 20KC/25KF CPUs.\n"); | |
932 | clear_c0_status(ST0_DE); | |
933 | break; | |
934 | default: | |
935 | break; | |
936 | } | |
937 | } | |
938 | ||
939 | asmlinkage void cache_parity_error(void) | |
940 | { | |
941 | const int field = 2 * sizeof(unsigned long); | |
942 | unsigned int reg_val; | |
943 | ||
944 | /* For the moment, report the problem and hang. */ | |
945 | printk("Cache error exception:\n"); | |
946 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
947 | reg_val = read_c0_cacheerr(); | |
948 | printk("c0_cacheerr == %08x\n", reg_val); | |
949 | ||
950 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
951 | reg_val & (1<<30) ? "secondary" : "primary", | |
952 | reg_val & (1<<31) ? "data" : "insn"); | |
953 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
954 | reg_val & (1<<29) ? "ED " : "", | |
955 | reg_val & (1<<28) ? "ET " : "", | |
956 | reg_val & (1<<26) ? "EE " : "", | |
957 | reg_val & (1<<25) ? "EB " : "", | |
958 | reg_val & (1<<24) ? "EI " : "", | |
959 | reg_val & (1<<23) ? "E1 " : "", | |
960 | reg_val & (1<<22) ? "E0 " : ""); | |
961 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
962 | ||
ec917c2c | 963 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
964 | if (reg_val & (1<<22)) |
965 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
966 | ||
967 | if (reg_val & (1<<23)) | |
968 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
969 | #endif | |
970 | ||
971 | panic("Can't handle the cache error!"); | |
972 | } | |
973 | ||
974 | /* | |
975 | * SDBBP EJTAG debug exception handler. | |
976 | * We skip the instruction and return to the next instruction. | |
977 | */ | |
978 | void ejtag_exception_handler(struct pt_regs *regs) | |
979 | { | |
980 | const int field = 2 * sizeof(unsigned long); | |
981 | unsigned long depc, old_epc; | |
982 | unsigned int debug; | |
983 | ||
984 | printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); | |
985 | depc = read_c0_depc(); | |
986 | debug = read_c0_debug(); | |
987 | printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); | |
988 | if (debug & 0x80000000) { | |
989 | /* | |
990 | * In branch delay slot. | |
991 | * We cheat a little bit here and use EPC to calculate the | |
992 | * debug return address (DEPC). EPC is restored after the | |
993 | * calculation. | |
994 | */ | |
995 | old_epc = regs->cp0_epc; | |
996 | regs->cp0_epc = depc; | |
997 | __compute_return_epc(regs); | |
998 | depc = regs->cp0_epc; | |
999 | regs->cp0_epc = old_epc; | |
1000 | } else | |
1001 | depc += 4; | |
1002 | write_c0_depc(depc); | |
1003 | ||
1004 | #if 0 | |
1005 | printk("\n\n----- Enable EJTAG single stepping ----\n\n"); | |
1006 | write_c0_debug(debug | 0x100); | |
1007 | #endif | |
1008 | } | |
1009 | ||
1010 | /* | |
1011 | * NMI exception handler. | |
1012 | */ | |
1013 | void nmi_exception_handler(struct pt_regs *regs) | |
1014 | { | |
41c594ab RB |
1015 | #ifdef CONFIG_MIPS_MT_SMTC |
1016 | unsigned long dvpret = dvpe(); | |
1017 | bust_spinlocks(1); | |
1018 | printk("NMI taken!!!!\n"); | |
1019 | mips_mt_regdump(dvpret); | |
1020 | #else | |
1021 | bust_spinlocks(1); | |
1da177e4 | 1022 | printk("NMI taken!!!!\n"); |
41c594ab | 1023 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 LT |
1024 | die("NMI", regs); |
1025 | while(1) ; | |
1026 | } | |
1027 | ||
e01402b1 RB |
1028 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1029 | ||
1030 | unsigned long ebase; | |
1da177e4 | 1031 | unsigned long exception_handlers[32]; |
e01402b1 | 1032 | unsigned long vi_handlers[64]; |
1da177e4 LT |
1033 | |
1034 | /* | |
1035 | * As a side effect of the way this is implemented we're limited | |
1036 | * to interrupt handlers in the address range from | |
1037 | * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... | |
1038 | */ | |
1039 | void *set_except_vector(int n, void *addr) | |
1040 | { | |
1041 | unsigned long handler = (unsigned long) addr; | |
1042 | unsigned long old_handler = exception_handlers[n]; | |
1043 | ||
1044 | exception_handlers[n] = handler; | |
1045 | if (n == 0 && cpu_has_divec) { | |
e01402b1 | 1046 | *(volatile u32 *)(ebase + 0x200) = 0x08000000 | |
1da177e4 | 1047 | (0x03ffffff & (handler >> 2)); |
e01402b1 RB |
1048 | flush_icache_range(ebase + 0x200, ebase + 0x204); |
1049 | } | |
1050 | return (void *)old_handler; | |
1051 | } | |
1052 | ||
1053 | #ifdef CONFIG_CPU_MIPSR2 | |
1054 | /* | |
193dd2ce | 1055 | * MIPSR2 shadow register set allocation |
e01402b1 RB |
1056 | * FIXME: SMP... |
1057 | */ | |
1058 | ||
193dd2ce RB |
1059 | static struct shadow_registers { |
1060 | /* | |
1061 | * Number of shadow register sets supported | |
1062 | */ | |
1063 | unsigned long sr_supported; | |
1064 | /* | |
1065 | * Bitmap of allocated shadow registers | |
1066 | */ | |
1067 | unsigned long sr_allocated; | |
e01402b1 RB |
1068 | } shadow_registers; |
1069 | ||
bb12d612 | 1070 | static void mips_srs_init(void) |
e01402b1 RB |
1071 | { |
1072 | #ifdef CONFIG_CPU_MIPSR2_SRS | |
1073 | shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; | |
7acb783e RB |
1074 | printk(KERN_INFO "%d MIPSR2 register sets available\n", |
1075 | shadow_registers.sr_supported); | |
e01402b1 RB |
1076 | #endif |
1077 | shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ | |
e01402b1 RB |
1078 | } |
1079 | ||
1080 | int mips_srs_max(void) | |
1081 | { | |
1082 | return shadow_registers.sr_supported; | |
1083 | } | |
1084 | ||
ff3eab2a | 1085 | int mips_srs_alloc(void) |
e01402b1 RB |
1086 | { |
1087 | struct shadow_registers *sr = &shadow_registers; | |
e01402b1 RB |
1088 | int set; |
1089 | ||
193dd2ce RB |
1090 | again: |
1091 | set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported); | |
1092 | if (set >= sr->sr_supported) | |
1093 | return -1; | |
e01402b1 | 1094 | |
193dd2ce RB |
1095 | if (test_and_set_bit(set, &sr->sr_allocated)) |
1096 | goto again; | |
e01402b1 | 1097 | |
193dd2ce | 1098 | return set; |
e01402b1 RB |
1099 | } |
1100 | ||
41c594ab | 1101 | void mips_srs_free(int set) |
e01402b1 RB |
1102 | { |
1103 | struct shadow_registers *sr = &shadow_registers; | |
e01402b1 | 1104 | |
193dd2ce | 1105 | clear_bit(set, &sr->sr_allocated); |
e01402b1 RB |
1106 | } |
1107 | ||
b4d05cb9 | 1108 | static void *set_vi_srs_handler(int n, void *addr, int srs) |
e01402b1 RB |
1109 | { |
1110 | unsigned long handler; | |
1111 | unsigned long old_handler = vi_handlers[n]; | |
1112 | u32 *w; | |
1113 | unsigned char *b; | |
1114 | ||
1115 | if (!cpu_has_veic && !cpu_has_vint) | |
1116 | BUG(); | |
1117 | ||
1118 | if (addr == NULL) { | |
1119 | handler = (unsigned long) do_default_vi; | |
1120 | srs = 0; | |
41c594ab | 1121 | } else |
e01402b1 RB |
1122 | handler = (unsigned long) addr; |
1123 | vi_handlers[n] = (unsigned long) addr; | |
1124 | ||
1125 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1126 | ||
1127 | if (srs >= mips_srs_max()) | |
1128 | panic("Shadow register set %d not supported", srs); | |
1129 | ||
1130 | if (cpu_has_veic) { | |
1131 | if (board_bind_eic_interrupt) | |
1132 | board_bind_eic_interrupt (n, srs); | |
41c594ab | 1133 | } else if (cpu_has_vint) { |
e01402b1 RB |
1134 | /* SRSMap is only defined if shadow sets are implemented */ |
1135 | if (mips_srs_max() > 1) | |
1136 | change_c0_srsmap (0xf << n*4, srs << n*4); | |
1137 | } | |
1138 | ||
1139 | if (srs == 0) { | |
1140 | /* | |
1141 | * If no shadow set is selected then use the default handler | |
1142 | * that does normal register saving and a standard interrupt exit | |
1143 | */ | |
1144 | ||
1145 | extern char except_vec_vi, except_vec_vi_lui; | |
1146 | extern char except_vec_vi_ori, except_vec_vi_end; | |
41c594ab RB |
1147 | #ifdef CONFIG_MIPS_MT_SMTC |
1148 | /* | |
1149 | * We need to provide the SMTC vectored interrupt handler | |
1150 | * not only with the address of the handler, but with the | |
1151 | * Status.IM bit to be masked before going there. | |
1152 | */ | |
1153 | extern char except_vec_vi_mori; | |
1154 | const int mori_offset = &except_vec_vi_mori - &except_vec_vi; | |
1155 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1156 | const int handler_len = &except_vec_vi_end - &except_vec_vi; |
1157 | const int lui_offset = &except_vec_vi_lui - &except_vec_vi; | |
1158 | const int ori_offset = &except_vec_vi_ori - &except_vec_vi; | |
1159 | ||
1160 | if (handler_len > VECTORSPACING) { | |
1161 | /* | |
1162 | * Sigh... panicing won't help as the console | |
1163 | * is probably not configured :( | |
1164 | */ | |
1165 | panic ("VECTORSPACING too small"); | |
1166 | } | |
1167 | ||
1168 | memcpy (b, &except_vec_vi, handler_len); | |
41c594ab RB |
1169 | #ifdef CONFIG_MIPS_MT_SMTC |
1170 | if (n > 7) | |
1171 | printk("Vector index %d exceeds SMTC maximum\n", n); | |
1172 | w = (u32 *)(b + mori_offset); | |
1173 | *w = (*w & 0xffff0000) | (0x100 << n); | |
1174 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1175 | w = (u32 *)(b + lui_offset); |
1176 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1177 | w = (u32 *)(b + ori_offset); | |
1178 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
1179 | flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); | |
1180 | } | |
1181 | else { | |
1182 | /* | |
1183 | * In other cases jump directly to the interrupt handler | |
1184 | * | |
1185 | * It is the handlers responsibility to save registers if required | |
1186 | * (eg hi/lo) and return from the exception using "eret" | |
1187 | */ | |
1188 | w = (u32 *)b; | |
1189 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1190 | *w = 0; | |
1191 | flush_icache_range((unsigned long)b, (unsigned long)(b+8)); | |
1da177e4 | 1192 | } |
e01402b1 | 1193 | |
1da177e4 LT |
1194 | return (void *)old_handler; |
1195 | } | |
1196 | ||
41c594ab | 1197 | void *set_vi_handler(int n, void *addr) |
e01402b1 | 1198 | { |
ff3eab2a | 1199 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 RB |
1200 | } |
1201 | #endif | |
1202 | ||
1da177e4 LT |
1203 | /* |
1204 | * This is used by native signal handling | |
1205 | */ | |
1206 | asmlinkage int (*save_fp_context)(struct sigcontext *sc); | |
1207 | asmlinkage int (*restore_fp_context)(struct sigcontext *sc); | |
1208 | ||
1209 | extern asmlinkage int _save_fp_context(struct sigcontext *sc); | |
1210 | extern asmlinkage int _restore_fp_context(struct sigcontext *sc); | |
1211 | ||
1212 | extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc); | |
1213 | extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc); | |
1214 | ||
41c594ab RB |
1215 | #ifdef CONFIG_SMP |
1216 | static int smp_save_fp_context(struct sigcontext *sc) | |
1217 | { | |
1218 | return cpu_has_fpu | |
1219 | ? _save_fp_context(sc) | |
1220 | : fpu_emulator_save_context(sc); | |
1221 | } | |
1222 | ||
1223 | static int smp_restore_fp_context(struct sigcontext *sc) | |
1224 | { | |
1225 | return cpu_has_fpu | |
1226 | ? _restore_fp_context(sc) | |
1227 | : fpu_emulator_restore_context(sc); | |
1228 | } | |
1229 | #endif | |
1230 | ||
1da177e4 LT |
1231 | static inline void signal_init(void) |
1232 | { | |
41c594ab RB |
1233 | #ifdef CONFIG_SMP |
1234 | /* For now just do the cpu_has_fpu check when the functions are invoked */ | |
1235 | save_fp_context = smp_save_fp_context; | |
1236 | restore_fp_context = smp_restore_fp_context; | |
1237 | #else | |
1da177e4 LT |
1238 | if (cpu_has_fpu) { |
1239 | save_fp_context = _save_fp_context; | |
1240 | restore_fp_context = _restore_fp_context; | |
1241 | } else { | |
1242 | save_fp_context = fpu_emulator_save_context; | |
1243 | restore_fp_context = fpu_emulator_restore_context; | |
1244 | } | |
41c594ab | 1245 | #endif |
1da177e4 LT |
1246 | } |
1247 | ||
1248 | #ifdef CONFIG_MIPS32_COMPAT | |
1249 | ||
1250 | /* | |
1251 | * This is used by 32-bit signal stuff on the 64-bit kernel | |
1252 | */ | |
1253 | asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc); | |
1254 | asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc); | |
1255 | ||
1256 | extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc); | |
1257 | extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc); | |
1258 | ||
1259 | extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc); | |
1260 | extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc); | |
1261 | ||
1262 | static inline void signal32_init(void) | |
1263 | { | |
1264 | if (cpu_has_fpu) { | |
1265 | save_fp_context32 = _save_fp_context32; | |
1266 | restore_fp_context32 = _restore_fp_context32; | |
1267 | } else { | |
1268 | save_fp_context32 = fpu_emulator_save_context32; | |
1269 | restore_fp_context32 = fpu_emulator_restore_context32; | |
1270 | } | |
1271 | } | |
1272 | #endif | |
1273 | ||
1274 | extern void cpu_cache_init(void); | |
1275 | extern void tlb_init(void); | |
1d40cfcd | 1276 | extern void flush_tlb_handlers(void); |
1da177e4 LT |
1277 | |
1278 | void __init per_cpu_trap_init(void) | |
1279 | { | |
1280 | unsigned int cpu = smp_processor_id(); | |
1281 | unsigned int status_set = ST0_CU0; | |
41c594ab RB |
1282 | #ifdef CONFIG_MIPS_MT_SMTC |
1283 | int secondaryTC = 0; | |
1284 | int bootTC = (cpu == 0); | |
1285 | ||
1286 | /* | |
1287 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1288 | * Note that this hack assumes that the SMTC init code | |
1289 | * assigns TCs consecutively and in ascending order. | |
1290 | */ | |
1291 | ||
1292 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1293 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1294 | secondaryTC = 1; | |
1295 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1296 | |
1297 | /* | |
1298 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1299 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1300 | * flag that some firmware may have left set and the TS bit (for | |
1301 | * IP27). Set XX for ISA IV code to work. | |
1302 | */ | |
875d43e7 | 1303 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1304 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1305 | #endif | |
1306 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
1307 | status_set |= ST0_XX; | |
b38c7399 | 1308 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1309 | status_set); |
1310 | ||
e50c0a8f RB |
1311 | if (cpu_has_dsp) |
1312 | set_c0_status(ST0_MX); | |
1313 | ||
e01402b1 RB |
1314 | #ifdef CONFIG_CPU_MIPSR2 |
1315 | write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ | |
1316 | #endif | |
1317 | ||
41c594ab RB |
1318 | #ifdef CONFIG_MIPS_MT_SMTC |
1319 | if (!secondaryTC) { | |
1320 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1321 | ||
1da177e4 | 1322 | /* |
e01402b1 | 1323 | * Interrupt handling. |
1da177e4 | 1324 | */ |
e01402b1 RB |
1325 | if (cpu_has_veic || cpu_has_vint) { |
1326 | write_c0_ebase (ebase); | |
1327 | /* Setting vector spacing enables EI/VI mode */ | |
1328 | change_c0_intctl (0x3e0, VECTORSPACING); | |
1329 | } | |
d03d0a57 RB |
1330 | if (cpu_has_divec) { |
1331 | if (cpu_has_mipsmt) { | |
1332 | unsigned int vpflags = dvpe(); | |
1333 | set_c0_cause(CAUSEF_IV); | |
1334 | evpe(vpflags); | |
1335 | } else | |
1336 | set_c0_cause(CAUSEF_IV); | |
1337 | } | |
41c594ab RB |
1338 | #ifdef CONFIG_MIPS_MT_SMTC |
1339 | } | |
1340 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1341 | |
1342 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1343 | TLBMISS_HANDLER_SETUP(); | |
1344 | ||
1345 | atomic_inc(&init_mm.mm_count); | |
1346 | current->active_mm = &init_mm; | |
1347 | BUG_ON(current->mm); | |
1348 | enter_lazy_tlb(&init_mm, current); | |
1349 | ||
41c594ab RB |
1350 | #ifdef CONFIG_MIPS_MT_SMTC |
1351 | if (bootTC) { | |
1352 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1353 | cpu_cache_init(); | |
1354 | tlb_init(); | |
1355 | #ifdef CONFIG_MIPS_MT_SMTC | |
1356 | } | |
1357 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1358 | } |
1359 | ||
e01402b1 RB |
1360 | /* Install CPU exception handler */ |
1361 | void __init set_handler (unsigned long offset, void *addr, unsigned long size) | |
1362 | { | |
1363 | memcpy((void *)(ebase + offset), addr, size); | |
1364 | flush_icache_range(ebase + offset, ebase + offset + size); | |
1365 | } | |
1366 | ||
1367 | /* Install uncached CPU exception handler */ | |
1368 | void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) | |
1369 | { | |
1370 | #ifdef CONFIG_32BIT | |
1371 | unsigned long uncached_ebase = KSEG1ADDR(ebase); | |
1372 | #endif | |
1373 | #ifdef CONFIG_64BIT | |
1374 | unsigned long uncached_ebase = TO_UNCAC(ebase); | |
1375 | #endif | |
1376 | ||
1377 | memcpy((void *)(uncached_ebase + offset), addr, size); | |
1378 | } | |
1379 | ||
1da177e4 LT |
1380 | void __init trap_init(void) |
1381 | { | |
1382 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1383 | extern char except_vec4; |
1384 | unsigned long i; | |
1385 | ||
e01402b1 RB |
1386 | if (cpu_has_veic || cpu_has_vint) |
1387 | ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); | |
1388 | else | |
1389 | ebase = CAC_BASE; | |
1390 | ||
1391 | #ifdef CONFIG_CPU_MIPSR2 | |
1392 | mips_srs_init(); | |
1393 | #endif | |
1394 | ||
1da177e4 LT |
1395 | per_cpu_trap_init(); |
1396 | ||
1397 | /* | |
1398 | * Copy the generic exception handlers to their final destination. | |
1399 | * This will be overriden later as suitable for a particular | |
1400 | * configuration. | |
1401 | */ | |
e01402b1 | 1402 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1403 | |
1404 | /* | |
1405 | * Setup default vectors | |
1406 | */ | |
1407 | for (i = 0; i <= 31; i++) | |
1408 | set_except_vector(i, handle_reserved); | |
1409 | ||
1410 | /* | |
1411 | * Copy the EJTAG debug exception vector handler code to it's final | |
1412 | * destination. | |
1413 | */ | |
e01402b1 RB |
1414 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
1415 | board_ejtag_handler_setup (); | |
1da177e4 LT |
1416 | |
1417 | /* | |
1418 | * Only some CPUs have the watch exceptions. | |
1419 | */ | |
1420 | if (cpu_has_watch) | |
1421 | set_except_vector(23, handle_watch); | |
1422 | ||
1423 | /* | |
e01402b1 | 1424 | * Initialise interrupt handlers |
1da177e4 | 1425 | */ |
e01402b1 RB |
1426 | if (cpu_has_veic || cpu_has_vint) { |
1427 | int nvec = cpu_has_veic ? 64 : 8; | |
1428 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1429 | set_vi_handler(i, NULL); |
e01402b1 RB |
1430 | } |
1431 | else if (cpu_has_divec) | |
1432 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1433 | |
1434 | /* | |
1435 | * Some CPUs can enable/disable for cache parity detection, but does | |
1436 | * it different ways. | |
1437 | */ | |
1438 | parity_protection_init(); | |
1439 | ||
1440 | /* | |
1441 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1442 | * by external hardware. Therefore these two exceptions | |
1443 | * may have board specific handlers. | |
1444 | */ | |
1445 | if (board_be_init) | |
1446 | board_be_init(); | |
1447 | ||
e4ac58af | 1448 | set_except_vector(0, handle_int); |
1da177e4 LT |
1449 | set_except_vector(1, handle_tlbm); |
1450 | set_except_vector(2, handle_tlbl); | |
1451 | set_except_vector(3, handle_tlbs); | |
1452 | ||
1453 | set_except_vector(4, handle_adel); | |
1454 | set_except_vector(5, handle_ades); | |
1455 | ||
1456 | set_except_vector(6, handle_ibe); | |
1457 | set_except_vector(7, handle_dbe); | |
1458 | ||
1459 | set_except_vector(8, handle_sys); | |
1460 | set_except_vector(9, handle_bp); | |
1461 | set_except_vector(10, handle_ri); | |
1462 | set_except_vector(11, handle_cpu); | |
1463 | set_except_vector(12, handle_ov); | |
1464 | set_except_vector(13, handle_tr); | |
1da177e4 LT |
1465 | |
1466 | if (current_cpu_data.cputype == CPU_R6000 || | |
1467 | current_cpu_data.cputype == CPU_R6000A) { | |
1468 | /* | |
1469 | * The R6000 is the only R-series CPU that features a machine | |
1470 | * check exception (similar to the R4000 cache error) and | |
1471 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1472 | * written yet. Well, anyway there is no R6000 machine on the | |
1473 | * current list of targets for Linux/MIPS. | |
1474 | * (Duh, crap, there is someone with a triple R6k machine) | |
1475 | */ | |
1476 | //set_except_vector(14, handle_mc); | |
1477 | //set_except_vector(15, handle_ndc); | |
1478 | } | |
1479 | ||
e01402b1 RB |
1480 | |
1481 | if (board_nmi_handler_setup) | |
1482 | board_nmi_handler_setup(); | |
1483 | ||
e50c0a8f RB |
1484 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1485 | set_except_vector(15, handle_fpe); | |
1486 | ||
1487 | set_except_vector(22, handle_mdmx); | |
1488 | ||
1489 | if (cpu_has_mcheck) | |
1490 | set_except_vector(24, handle_mcheck); | |
1491 | ||
340ee4b9 RB |
1492 | if (cpu_has_mipsmt) |
1493 | set_except_vector(25, handle_mt); | |
1494 | ||
e50c0a8f RB |
1495 | if (cpu_has_dsp) |
1496 | set_except_vector(26, handle_dsp); | |
1497 | ||
1498 | if (cpu_has_vce) | |
1499 | /* Special exception: R4[04]00 uses also the divec space. */ | |
1500 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); | |
1501 | else if (cpu_has_4kex) | |
1502 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); | |
1503 | else | |
1504 | memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); | |
1505 | ||
1da177e4 LT |
1506 | signal_init(); |
1507 | #ifdef CONFIG_MIPS32_COMPAT | |
1508 | signal32_init(); | |
1509 | #endif | |
1510 | ||
e01402b1 | 1511 | flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1512 | flush_tlb_handlers(); |
1da177e4 | 1513 | } |