[mirror_ubuntu-bionic-kernel.git] / arch / mips / lantiq / irq.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 * Copyright (C) 2010 John Crispin <john@phrozen.org>
 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
 */

#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/irqdomain.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>

#include <lantiq_soc.h>
#include <irq.h>

/* register definitions - internal irqs */
#define LTQ_ICU_IM0_ISR		0x0000
#define LTQ_ICU_IM0_IER		0x0008
#define LTQ_ICU_IM0_IOSR	0x0010
#define LTQ_ICU_IM0_IRSR	0x0018
#define LTQ_ICU_IM0_IMR		0x0020
#define LTQ_ICU_IM1_ISR		0x0028
#define LTQ_ICU_OFFSET		(LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)

/* register definitions - external irqs */
#define LTQ_EIU_EXIN_C		0x0000
#define LTQ_EIU_EXIN_INIC	0x0004
#define LTQ_EIU_EXIN_INC	0x0008
#define LTQ_EIU_EXIN_INEN	0x000C

/* number of external interrupts */
#define MAX_EIU			6

/* the performance counter */
#define LTQ_PERF_IRQ		(INT_NUM_IM4_IRL0 + 31)

/*
 * irqs generated by devices attached to the EBU need to be acked in
 * a special manner
 */
#define LTQ_ICU_EBU_IRQ		22

#define ltq_icu_w32(m, x, y)	ltq_w32((x), ltq_icu_membase[m] + (y))
#define ltq_icu_r32(m, x)	ltq_r32(ltq_icu_membase[m] + (x))

#define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
#define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))

/* our 2 ipi interrupts for VSMP */
#define MIPS_CPU_IPI_RESCHED_IRQ	0
#define MIPS_CPU_IPI_CALL_IRQ		1

/* we have a cascade of 8 irqs */
#define MIPS_CPU_IRQ_CASCADE		8

static int exin_avail;
static u32 ltq_eiu_irq[MAX_EIU];
static void __iomem *ltq_icu_membase[MAX_IM];
static void __iomem *ltq_eiu_membase;
static struct irq_domain *ltq_domain;
static int ltq_perfcount_irq;

int ltq_eiu_get_irq(int exin)
{
	if (exin < exin_avail)
		return ltq_eiu_irq[exin];
	return -1;
}

void ltq_disable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
}

void ltq_mask_and_ack_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
	ltq_icu_w32(im, BIT(offset), isr);
}

static void ltq_ack_irq(struct irq_data *d)
{
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, BIT(offset), isr);
}

void ltq_enable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
}

static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
{
	int i;

	for (i = 0; i < exin_avail; i++) {
		if (d->hwirq == ltq_eiu_irq[i]) {
			int val = 0;
			int edge = 0;

			switch (type) {
			case IRQF_TRIGGER_NONE:
				break;
			case IRQF_TRIGGER_RISING:
				val = 1;
				edge = 1;
				break;
			case IRQF_TRIGGER_FALLING:
				val = 2;
				edge = 1;
				break;
			case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
				val = 3;
				edge = 1;
				break;
			case IRQF_TRIGGER_HIGH:
				val = 5;
				break;
			case IRQF_TRIGGER_LOW:
				val = 6;
				break;
			default:
				pr_err("invalid type %d for irq %ld\n",
					type, d->hwirq);
				return -EINVAL;
			}

			if (edge)
				irq_set_handler(d->hwirq, handle_edge_irq);

			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
				(val << (i * 4)), LTQ_EIU_EXIN_C);
		}
	}

	return 0;
}

static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_enable_irq(d);
	for (i = 0; i < exin_avail; i++) {
		if (d->hwirq == ltq_eiu_irq[i]) {
			/* by default we are low level triggered */
			ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
			/* clear all pending */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
				LTQ_EIU_EXIN_INC);
			/* enable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}

	return 0;
}

static void ltq_shutdown_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_disable_irq(d);
	for (i = 0; i < exin_avail; i++) {
		if (d->hwirq == ltq_eiu_irq[i]) {
			/* disable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}
}

static struct irq_chip ltq_irq_type = {
	.name = "icu",
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
};

static struct irq_chip ltq_eiu_type = {
	.name = "eiu",
	.irq_startup = ltq_startup_eiu_irq,
	.irq_shutdown = ltq_shutdown_eiu_irq,
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
	.irq_set_type = ltq_eiu_settype,
};

static void ltq_hw_irqdispatch(int module)
{
	u32 irq;

	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
	if (irq == 0)
		return;

	/*
	 * silicon bug causes only the msb set to 1 to be valid. all
	 * other bits might be bogus
	 */
	irq = __fls(irq);
	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));

	/* if this is a EBU irq, we need to ack it or get a deadlock */
	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
			LTQ_EBU_PCC_ISTAT);
}

#define DEFINE_HWx_IRQDISPATCH(x)					\
	static void ltq_hw ## x ## _irqdispatch(void)			\
	{								\
		ltq_hw_irqdispatch(x);					\
	}
DEFINE_HWx_IRQDISPATCH(0)
DEFINE_HWx_IRQDISPATCH(1)
DEFINE_HWx_IRQDISPATCH(2)
DEFINE_HWx_IRQDISPATCH(3)
DEFINE_HWx_IRQDISPATCH(4)

#if MIPS_CPU_TIMER_IRQ == 7
static void ltq_hw5_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_TIMER_IRQ);
}
#else
DEFINE_HWx_IRQDISPATCH(5)
#endif

static void ltq_hw_irq_handler(struct irq_desc *desc)
{
	ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
	int irq;

	if (!pending) {
		spurious_interrupt();
		return;
	}

	pending >>= CAUSEB_IP;
	while (pending) {
		irq = fls(pending) - 1;
		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
		pending &= ~BIT(irq);
	}
}

static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
	struct irq_chip *chip = &ltq_irq_type;
	int i;

	if (hw < MIPS_CPU_IRQ_CASCADE)
		return 0;

	for (i = 0; i < exin_avail; i++)
		if (hw == ltq_eiu_irq[i])
			chip = &ltq_eiu_type;

	irq_set_chip_and_handler(irq, chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops irq_domain_ops = {
	.xlate = irq_domain_xlate_onetwocell,
	.map = icu_map,
};

int __init icu_of_init(struct device_node *node, struct device_node *parent)
{
	struct device_node *eiu_node;
	struct resource res;
	int i, ret;

	for (i = 0; i < MAX_IM; i++) {
		if (of_address_to_resource(node, i, &res))
			panic("Failed to get icu memory range");

		if (!request_mem_region(res.start, resource_size(&res),
					res.name))
			pr_err("Failed to request icu memory");

		ltq_icu_membase[i] = ioremap_nocache(res.start,
					resource_size(&res));
		if (!ltq_icu_membase[i])
			panic("Failed to remap icu memory");
	}

	/* turn off all irqs by default */
	for (i = 0; i < MAX_IM; i++) {
		/* make sure all irqs are turned off by default */
		ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
		/* clear all possibly pending interrupts */
		ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
	}

	mips_cpu_irq_init();

	for (i = 0; i < MAX_IM; i++)
		irq_set_chained_handler(i + 2, ltq_hw_irq_handler);

	if (cpu_has_vint) {
		pr_info("Setting up vectored interrupts\n");
		set_vi_handler(2, ltq_hw0_irqdispatch);
		set_vi_handler(3, ltq_hw1_irqdispatch);
		set_vi_handler(4, ltq_hw2_irqdispatch);
		set_vi_handler(5, ltq_hw3_irqdispatch);
		set_vi_handler(6, ltq_hw4_irqdispatch);
		set_vi_handler(7, ltq_hw5_irqdispatch);
	}

	ltq_domain = irq_domain_add_linear(node,
		(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
		&irq_domain_ops, 0);

#ifndef CONFIG_MIPS_MT_SMP
	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#else
	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif

	/* tell oprofile which irq to use */
	ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);

	/*
	 * if the timer irq is not one of the mips irqs we need to
	 * create a mapping
	 */
	if (MIPS_CPU_TIMER_IRQ != 7)
		irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);

	/* the external interrupts are optional and xway only */
	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
		/* find out how many external irq sources we have */
		exin_avail = of_property_count_u32_elems(eiu_node,
							 "lantiq,eiu-irqs");

		if (exin_avail > MAX_EIU)
			exin_avail = MAX_EIU;

		ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
						ltq_eiu_irq, exin_avail);
		if (ret)
			panic("failed to load external irq resources");

		if (!request_mem_region(res.start, resource_size(&res),
							res.name))
			pr_err("Failed to request eiu memory");

		ltq_eiu_membase = ioremap_nocache(res.start,
							resource_size(&res));
		if (!ltq_eiu_membase)
			panic("Failed to remap eiu memory");
	}

	return 0;
}

int get_c0_perfcount_int(void)
{
	return ltq_perfcount_irq;
}
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);

unsigned int get_c0_compare_int(void)
{
	return MIPS_CPU_TIMER_IRQ;
}

static struct of_device_id __initdata of_irq_ids[] = {
	{ .compatible = "lantiq,icu", .data = icu_of_init },
	{},
};

void __init arch_init_irq(void)
{
	of_irq_init(of_irq_ids);
}
Commit	Line	Data
171bb2f1 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
97b92108	6	* Copyright (C) 2010 John Crispin <john@phrozen.org>
171bb2f1 JC	7	* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
	8	*/
	9
	10	#include <linux/interrupt.h>
	11	#include <linux/ioport.h>
3645da02 JC	12	#include <linux/sched.h>
	13	#include <linux/irqdomain.h>
	14	#include <linux/of_platform.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_irq.h>
171bb2f1 JC	17
	18	#include <asm/bootinfo.h>
	19	#include <asm/irq_cpu.h>
	20
	21	#include <lantiq_soc.h>
	22	#include <irq.h>
	23
3645da02	24	/* register definitions - internal irqs */
171bb2f1 JC	25	#define LTQ_ICU_IM0_ISR 0x0000
	26	#define LTQ_ICU_IM0_IER 0x0008
	27	#define LTQ_ICU_IM0_IOSR 0x0010
	28	#define LTQ_ICU_IM0_IRSR 0x0018
	29	#define LTQ_ICU_IM0_IMR 0x0020
	30	#define LTQ_ICU_IM1_ISR 0x0028
	31	#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
	32
3645da02	33	/* register definitions - external irqs */
171bb2f1 JC	34	#define LTQ_EIU_EXIN_C 0x0000
171bb2f1 JC	35	#define LTQ_EIU_EXIN_INIC 0x0004
26365625	36	#define LTQ_EIU_EXIN_INC 0x0008
171bb2f1 JC	37	#define LTQ_EIU_EXIN_INEN 0x000C
171bb2f1 JC	38
26365625	39	/* number of external interrupts */
171bb2f1 JC	40	#define MAX_EIU 6
171bb2f1 JC	41
59c11579 JC	42	/* the performance counter */
	43	#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
	44
3645da02 JC	45	/*
3645da02 JC	46	* irqs generated by devices attached to the EBU need to be acked in
171bb2f1 JC	47	* a special manner
	48	*/
	49	#define LTQ_ICU_EBU_IRQ 22
	50
61fa969f JC	51	#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
61fa969f JC	52	#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
171bb2f1 JC	53
	54	#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
	55	#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
	56
a8d096ef JC	57	/* our 2 ipi interrupts for VSMP */
	58	#define MIPS_CPU_IPI_RESCHED_IRQ 0
	59	#define MIPS_CPU_IPI_CALL_IRQ 1
	60
3645da02 JC	61	/* we have a cascade of 8 irqs */
	62	#define MIPS_CPU_IRQ_CASCADE 8
	63
3645da02	64	static int exin_avail;
fe46e503	65	static u32 ltq_eiu_irq[MAX_EIU];
61fa969f	66	static void __iomem *ltq_icu_membase[MAX_IM];
171bb2f1	67	static void __iomem *ltq_eiu_membase;
c2c9c788	68	static struct irq_domain *ltq_domain;
a669efc4	69	static int ltq_perfcount_irq;
171bb2f1	70
26365625 JC	71	int ltq_eiu_get_irq(int exin)
	72	{
	73	if (exin < exin_avail)
fe46e503	74	return ltq_eiu_irq[exin];
26365625 JC	75	return -1;
	76	}
	77
171bb2f1 JC	78	void ltq_disable_irq(struct irq_data *d)
	79	{
	80	u32 ier = LTQ_ICU_IM0_IER;
3645da02	81	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	82	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	83
3645da02	84	offset %= INT_NUM_IM_OFFSET;
61fa969f	85	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
171bb2f1 JC	86	}
	87
	88	void ltq_mask_and_ack_irq(struct irq_data *d)
	89	{
	90	u32 ier = LTQ_ICU_IM0_IER;
	91	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	92	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	93	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	94
3645da02	95	offset %= INT_NUM_IM_OFFSET;
61fa969f JC	96	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
61fa969f JC	97	ltq_icu_w32(im, BIT(offset), isr);
171bb2f1 JC	98	}
	99
	100	static void ltq_ack_irq(struct irq_data *d)
	101	{
	102	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	103	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	104	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	105
3645da02	106	offset %= INT_NUM_IM_OFFSET;
61fa969f	107	ltq_icu_w32(im, BIT(offset), isr);
171bb2f1 JC	108	}
	109
	110	void ltq_enable_irq(struct irq_data *d)
	111	{
	112	u32 ier = LTQ_ICU_IM0_IER;
3645da02	113	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	114	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	115
3645da02	116	offset %= INT_NUM_IM_OFFSET;
61fa969f	117	ltq_icu_w32(im, ltq_icu_r32(im, ier) \| BIT(offset), ier);
171bb2f1 JC	118	}
171bb2f1 JC	119
26365625 JC	120	static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
	121	{
	122	int i;
	123
f97e5e8e	124	for (i = 0; i < exin_avail; i++) {
fe46e503	125	if (d->hwirq == ltq_eiu_irq[i]) {
26365625 JC	126	int val = 0;
	127	int edge = 0;
	128
	129	switch (type) {
	130	case IRQF_TRIGGER_NONE:
	131	break;
	132	case IRQF_TRIGGER_RISING:
	133	val = 1;
	134	edge = 1;
	135	break;
	136	case IRQF_TRIGGER_FALLING:
	137	val = 2;
	138	edge = 1;
	139	break;
	140	case IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING:
	141	val = 3;
	142	edge = 1;
	143	break;
	144	case IRQF_TRIGGER_HIGH:
	145	val = 5;
	146	break;
	147	case IRQF_TRIGGER_LOW:
	148	val = 6;
	149	break;
	150	default:
	151	pr_err("invalid type %d for irq %ld\n",
	152	type, d->hwirq);
	153	return -EINVAL;
	154	}
	155
	156	if (edge)
	157	irq_set_handler(d->hwirq, handle_edge_irq);
	158
	159	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) \|
	160	(val << (i * 4)), LTQ_EIU_EXIN_C);
	161	}
	162	}
	163
	164	return 0;
	165	}
	166
171bb2f1 JC	167	static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
	168	{
	169	int i;
171bb2f1 JC	170
171bb2f1 JC	171	ltq_enable_irq(d);
f97e5e8e	172	for (i = 0; i < exin_avail; i++) {
fe46e503	173	if (d->hwirq == ltq_eiu_irq[i]) {
26365625 JC	174	/* by default we are low level triggered */
26365625 JC	175	ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
171bb2f1	176	/* clear all pending */
26365625 JC	177	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
26365625 JC	178	LTQ_EIU_EXIN_INC);
171bb2f1	179	/* enable */
3645da02	180	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) \| BIT(i),
171bb2f1 JC	181	LTQ_EIU_EXIN_INEN);
	182	break;
	183	}
	184	}
	185
	186	return 0;
	187	}
	188
	189	static void ltq_shutdown_eiu_irq(struct irq_data *d)
	190	{
	191	int i;
171bb2f1 JC	192
171bb2f1 JC	193	ltq_disable_irq(d);
f97e5e8e	194	for (i = 0; i < exin_avail; i++) {
fe46e503	195	if (d->hwirq == ltq_eiu_irq[i]) {
171bb2f1	196	/* disable */
3645da02	197	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
171bb2f1 JC	198	LTQ_EIU_EXIN_INEN);
	199	break;
	200	}
	201	}
	202	}
	203
	204	static struct irq_chip ltq_irq_type = {
891ab064	205	.name = "icu",
171bb2f1 JC	206	.irq_enable = ltq_enable_irq,
	207	.irq_disable = ltq_disable_irq,
	208	.irq_unmask = ltq_enable_irq,
	209	.irq_ack = ltq_ack_irq,
	210	.irq_mask = ltq_disable_irq,
	211	.irq_mask_ack = ltq_mask_and_ack_irq,
	212	};
	213
	214	static struct irq_chip ltq_eiu_type = {
891ab064	215	.name = "eiu",
171bb2f1 JC	216	.irq_startup = ltq_startup_eiu_irq,
	217	.irq_shutdown = ltq_shutdown_eiu_irq,
	218	.irq_enable = ltq_enable_irq,
	219	.irq_disable = ltq_disable_irq,
	220	.irq_unmask = ltq_enable_irq,
	221	.irq_ack = ltq_ack_irq,
	222	.irq_mask = ltq_disable_irq,
	223	.irq_mask_ack = ltq_mask_and_ack_irq,
26365625	224	.irq_set_type = ltq_eiu_settype,
171bb2f1 JC	225	};
	226
	227	static void ltq_hw_irqdispatch(int module)
	228	{
	229	u32 irq;
	230
61fa969f	231	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
171bb2f1 JC	232	if (irq == 0)
	233	return;
	234
3645da02 JC	235	/*
3645da02 JC	236	* silicon bug causes only the msb set to 1 to be valid. all
171bb2f1 JC	237	* other bits might be bogus
	238	*/
	239	irq = __fls(irq);
3645da02	240	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
171bb2f1 JC	241
171bb2f1 JC	242	/* if this is a EBU irq, we need to ack it or get a deadlock */
3645da02	243	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
171bb2f1 JC	244	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) \| 0x10,
	245	LTQ_EBU_PCC_ISTAT);
	246	}
	247
	248	#define DEFINE_HWx_IRQDISPATCH(x) \
	249	static void ltq_hw ## x ## _irqdispatch(void) \
	250	{ \
	251	ltq_hw_irqdispatch(x); \
	252	}
	253	DEFINE_HWx_IRQDISPATCH(0)
	254	DEFINE_HWx_IRQDISPATCH(1)
	255	DEFINE_HWx_IRQDISPATCH(2)
	256	DEFINE_HWx_IRQDISPATCH(3)
	257	DEFINE_HWx_IRQDISPATCH(4)
	258
c2c9c788	259	#if MIPS_CPU_TIMER_IRQ == 7
171bb2f1 JC	260	static void ltq_hw5_irqdispatch(void)
	261	{
	262	do_IRQ(MIPS_CPU_TIMER_IRQ);
	263	}
c2c9c788 JC	264	#else
	265	DEFINE_HWx_IRQDISPATCH(5)
	266	#endif
171bb2f1	267
6c356eda FF	268	static void ltq_hw_irq_handler(struct irq_desc *desc)
	269	{
	270	ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
	271	}
	272
171bb2f1 JC	273	asmlinkage void plat_irq_dispatch(void)
	274	{
	275	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
6c356eda FF	276	int irq;
	277
	278	if (!pending) {
	279	spurious_interrupt();
	280	return;
171bb2f1	281	}
171bb2f1	282
6c356eda FF	283	pending >>= CAUSEB_IP;
	284	while (pending) {
	285	irq = fls(pending) - 1;
	286	do_IRQ(MIPS_CPU_IRQ_BASE + irq);
	287	pending &= ~BIT(irq);
	288	}
171bb2f1 JC	289	}
171bb2f1 JC	290
3645da02 JC	291	static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
	292	{
	293	struct irq_chip *chip = &ltq_irq_type;
	294	int i;
	295
9c1628b6 JC	296	if (hw < MIPS_CPU_IRQ_CASCADE)
	297	return 0;
	298
3645da02	299	for (i = 0; i < exin_avail; i++)
fe46e503	300	if (hw == ltq_eiu_irq[i])
3645da02 JC	301	chip = &ltq_eiu_type;
3645da02 JC	302
7bf0d5e8	303	irq_set_chip_and_handler(irq, chip, handle_level_irq);
3645da02 JC	304
	305	return 0;
	306	}
	307
	308	static const struct irq_domain_ops irq_domain_ops = {
	309	.xlate = irq_domain_xlate_onetwocell,
	310	.map = icu_map,
	311	};
	312
3645da02	313	int __init icu_of_init(struct device_node node, struct device_node parent)
171bb2f1	314	{
3645da02 JC	315	struct device_node *eiu_node;
3645da02 JC	316	struct resource res;
26365625	317	int i, ret;
171bb2f1	318
61fa969f JC	319	for (i = 0; i < MAX_IM; i++) {
	320	if (of_address_to_resource(node, i, &res))
	321	panic("Failed to get icu memory range");
171bb2f1	322
6e807852 HM	323	if (!request_mem_region(res.start, resource_size(&res),
6e807852 HM	324	res.name))
61fa969f	325	pr_err("Failed to request icu memory");
171bb2f1	326
61fa969f JC	327	ltq_icu_membase[i] = ioremap_nocache(res.start,
	328	resource_size(&res));
	329	if (!ltq_icu_membase[i])
	330	panic("Failed to remap icu memory");
	331	}
171bb2f1	332
16f70b56	333	/* turn off all irqs by default */
61fa969f	334	for (i = 0; i < MAX_IM; i++) {
16f70b56	335	/* make sure all irqs are turned off by default */
61fa969f	336	ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
16f70b56	337	/* clear all possibly pending interrupts */
61fa969f	338	ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
16f70b56	339	}
171bb2f1 JC	340
	341	mips_cpu_irq_init();
	342
61fa969f	343	for (i = 0; i < MAX_IM; i++)
6c356eda	344	irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
171bb2f1 JC	345
	346	if (cpu_has_vint) {
	347	pr_info("Setting up vectored interrupts\n");
	348	set_vi_handler(2, ltq_hw0_irqdispatch);
	349	set_vi_handler(3, ltq_hw1_irqdispatch);
	350	set_vi_handler(4, ltq_hw2_irqdispatch);
	351	set_vi_handler(5, ltq_hw3_irqdispatch);
	352	set_vi_handler(6, ltq_hw4_irqdispatch);
	353	set_vi_handler(7, ltq_hw5_irqdispatch);
	354	}
	355
c2c9c788	356	ltq_domain = irq_domain_add_linear(node,
61fa969f	357	(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
3645da02	358	&irq_domain_ops, 0);
171bb2f1	359
b633648c	360	#ifndef CONFIG_MIPS_MT_SMP
171bb2f1 JC	361	set_c0_status(IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \|
	362	IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	363	#else
	364	set_c0_status(IE_SW0 \| IE_SW1 \| IE_IRQ0 \| IE_IRQ1 \|
	365	IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	366	#endif
59c11579 JC	367
59c11579 JC	368	/* tell oprofile which irq to use */
a669efc4	369	ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
c2c9c788 JC	370
	371	/*
	372	* if the timer irq is not one of the mips irqs we need to
	373	* create a mapping
	374	*/
	375	if (MIPS_CPU_TIMER_IRQ != 7)
	376	irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
	377
d32caf94 JC	378	/* the external interrupts are optional and xway only */
	379	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
	380	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
	381	/* find out how many external irq sources we have */
fe46e503 JC	382	exin_avail = of_property_count_u32_elems(eiu_node,
fe46e503 JC	383	"lantiq,eiu-irqs");
d32caf94 JC	384
	385	if (exin_avail > MAX_EIU)
	386	exin_avail = MAX_EIU;
	387
fe46e503	388	ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
d32caf94	389	ltq_eiu_irq, exin_avail);
fe46e503	390	if (ret)
d32caf94 JC	391	panic("failed to load external irq resources");
d32caf94 JC	392
6e807852 HM	393	if (!request_mem_region(res.start, resource_size(&res),
6e807852 HM	394	res.name))
d32caf94 JC	395	pr_err("Failed to request eiu memory");
	396
	397	ltq_eiu_membase = ioremap_nocache(res.start,
	398	resource_size(&res));
	399	if (!ltq_eiu_membase)
	400	panic("Failed to remap eiu memory");
	401	}
	402
3645da02	403	return 0;
171bb2f1 JC	404	}
171bb2f1 JC	405
a669efc4 AB	406	int get_c0_perfcount_int(void)
	407	{
	408	return ltq_perfcount_irq;
	409	}
0cb0985f	410	EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
a669efc4	411
078a55fc	412	unsigned int get_c0_compare_int(void)
171bb2f1	413	{
c2c9c788	414	return MIPS_CPU_TIMER_IRQ;
171bb2f1	415	}
3645da02 JC	416
	417	static struct of_device_id __initdata of_irq_ids[] = {
	418	{ .compatible = "lantiq,icu", .data = icu_of_init },
	419	{},
	420	};
	421
	422	void __init arch_init_irq(void)
	423	{
	424	of_irq_init(of_irq_ids);
	425	}