]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com> | |
70342287 | 7 | * Copyright (C) 2000, 2001, 06 Ralf Baechle <ralf@linux-mips.org> |
1da177e4 LT |
8 | * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. |
9 | */ | |
9a88cbb5 | 10 | |
1da177e4 | 11 | #include <linux/types.h> |
9a88cbb5 | 12 | #include <linux/dma-mapping.h> |
1da177e4 | 13 | #include <linux/mm.h> |
d9ba5778 | 14 | #include <linux/export.h> |
4fcc47a0 | 15 | #include <linux/scatterlist.h> |
6e86b0bf | 16 | #include <linux/string.h> |
5a0e3ad6 | 17 | #include <linux/gfp.h> |
e36863a5 | 18 | #include <linux/highmem.h> |
f4649382 | 19 | #include <linux/dma-contiguous.h> |
1da177e4 LT |
20 | |
21 | #include <asm/cache.h> | |
69f24d17 | 22 | #include <asm/cpu-type.h> |
1da177e4 LT |
23 | #include <asm/io.h> |
24 | ||
9a88cbb5 RB |
25 | #include <dma-coherence.h> |
26 | ||
20d33064 | 27 | #if defined(CONFIG_DMA_MAYBE_COHERENT) && !defined(CONFIG_DMA_PERDEV_COHERENT) |
f2302023 PB |
28 | /* User defined DMA coherency from command line. */ |
29 | enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT; | |
b6d92b4a SH |
30 | EXPORT_SYMBOL_GPL(coherentio); |
31 | int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ | |
32 | ||
33 | static int __init setcoherentio(char *str) | |
34 | { | |
f2302023 | 35 | coherentio = IO_COHERENCE_ENABLED; |
b6d92b4a SH |
36 | pr_info("Hardware DMA cache coherency (command line)\n"); |
37 | return 0; | |
38 | } | |
39 | early_param("coherentio", setcoherentio); | |
40 | ||
41 | static int __init setnocoherentio(char *str) | |
42 | { | |
f2302023 | 43 | coherentio = IO_COHERENCE_DISABLED; |
b6d92b4a SH |
44 | pr_info("Software DMA cache coherency (command line)\n"); |
45 | return 0; | |
46 | } | |
47 | early_param("nocoherentio", setnocoherentio); | |
885014bc | 48 | #endif |
b6d92b4a | 49 | |
e36863a5 | 50 | static inline struct page *dma_addr_to_page(struct device *dev, |
3807ef3f | 51 | dma_addr_t dma_addr) |
c9d06962 | 52 | { |
e36863a5 DD |
53 | return pfn_to_page( |
54 | plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); | |
c9d06962 FBH |
55 | } |
56 | ||
1da177e4 | 57 | /* |
f86f55d3 JQ |
58 | * The affected CPUs below in 'cpu_needs_post_dma_flush()' can |
59 | * speculatively fill random cachelines with stale data at any time, | |
60 | * requiring an extra flush post-DMA. | |
61 | * | |
1da177e4 LT |
62 | * Warning on the terminology - Linux calls an uncached area coherent; |
63 | * MIPS terminology calls memory areas with hardware maintained coherency | |
64 | * coherent. | |
0dc294c0 RB |
65 | * |
66 | * Note that the R14000 and R16000 should also be checked for in this | |
67 | * condition. However this function is only called on non-I/O-coherent | |
68 | * systems and only the R10000 and R12000 are used in such systems, the | |
69 | * SGI IP28 Indigo² rsp. SGI IP32 aka O2. | |
1da177e4 | 70 | */ |
f86f55d3 | 71 | static inline int cpu_needs_post_dma_flush(struct device *dev) |
9a88cbb5 RB |
72 | { |
73 | return !plat_device_is_coherent(dev) && | |
d451e734 | 74 | (boot_cpu_type() == CPU_R10000 || |
eb37e6dd RB |
75 | boot_cpu_type() == CPU_R12000 || |
76 | boot_cpu_type() == CPU_BMIPS5000); | |
9a88cbb5 RB |
77 | } |
78 | ||
cce335ae RB |
79 | static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) |
80 | { | |
a2e715a8 RB |
81 | gfp_t dma_flag; |
82 | ||
cce335ae RB |
83 | /* ignore region specifiers */ |
84 | gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); | |
85 | ||
a2e715a8 | 86 | #ifdef CONFIG_ISA |
cce335ae | 87 | if (dev == NULL) |
a2e715a8 | 88 | dma_flag = __GFP_DMA; |
cce335ae RB |
89 | else |
90 | #endif | |
a2e715a8 | 91 | #if defined(CONFIG_ZONE_DMA32) && defined(CONFIG_ZONE_DMA) |
8d4925e9 | 92 | if (dev == NULL || dev->coherent_dma_mask < DMA_BIT_MASK(32)) |
a2e715a8 RB |
93 | dma_flag = __GFP_DMA; |
94 | else if (dev->coherent_dma_mask < DMA_BIT_MASK(64)) | |
95 | dma_flag = __GFP_DMA32; | |
96 | else | |
97 | #endif | |
98 | #if defined(CONFIG_ZONE_DMA32) && !defined(CONFIG_ZONE_DMA) | |
8d4925e9 | 99 | if (dev == NULL || dev->coherent_dma_mask < DMA_BIT_MASK(64)) |
a2e715a8 RB |
100 | dma_flag = __GFP_DMA32; |
101 | else | |
102 | #endif | |
103 | #if defined(CONFIG_ZONE_DMA) && !defined(CONFIG_ZONE_DMA32) | |
8d4925e9 MR |
104 | if (dev == NULL || |
105 | dev->coherent_dma_mask < DMA_BIT_MASK(sizeof(phys_addr_t) * 8)) | |
a2e715a8 | 106 | dma_flag = __GFP_DMA; |
cce335ae RB |
107 | else |
108 | #endif | |
a2e715a8 | 109 | dma_flag = 0; |
cce335ae RB |
110 | |
111 | /* Don't invoke OOM killer */ | |
112 | gfp |= __GFP_NORETRY; | |
113 | ||
a2e715a8 | 114 | return gfp | dma_flag; |
cce335ae RB |
115 | } |
116 | ||
1e893752 | 117 | static void *mips_dma_alloc_noncoherent(struct device *dev, size_t size, |
185a8ff5 | 118 | dma_addr_t * dma_handle, gfp_t gfp) |
1da177e4 LT |
119 | { |
120 | void *ret; | |
9a88cbb5 | 121 | |
cce335ae | 122 | gfp = massage_gfp_flags(dev, gfp); |
1da177e4 | 123 | |
1da177e4 LT |
124 | ret = (void *) __get_free_pages(gfp, get_order(size)); |
125 | ||
126 | if (ret != NULL) { | |
127 | memset(ret, 0, size); | |
9a88cbb5 | 128 | *dma_handle = plat_map_dma_mem(dev, ret, size); |
1da177e4 LT |
129 | } |
130 | ||
131 | return ret; | |
132 | } | |
1da177e4 | 133 | |
48e1fd5a | 134 | static void *mips_dma_alloc_coherent(struct device *dev, size_t size, |
00085f1e | 135 | dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) |
1da177e4 LT |
136 | { |
137 | void *ret; | |
f4649382 ZLK |
138 | struct page *page = NULL; |
139 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1da177e4 | 140 | |
1e893752 CH |
141 | /* |
142 | * XXX: seems like the coherent and non-coherent implementations could | |
143 | * be consolidated. | |
144 | */ | |
00085f1e | 145 | if (attrs & DMA_ATTR_NON_CONSISTENT) |
1e893752 CH |
146 | return mips_dma_alloc_noncoherent(dev, size, dma_handle, gfp); |
147 | ||
cce335ae | 148 | gfp = massage_gfp_flags(dev, gfp); |
9a88cbb5 | 149 | |
9530d0fe | 150 | if (IS_ENABLED(CONFIG_DMA_CMA) && gfpflags_allow_blocking(gfp)) |
f4649382 ZLK |
151 | page = dma_alloc_from_contiguous(dev, |
152 | count, get_order(size)); | |
153 | if (!page) | |
154 | page = alloc_pages(gfp, get_order(size)); | |
155 | ||
156 | if (!page) | |
157 | return NULL; | |
158 | ||
159 | ret = page_address(page); | |
160 | memset(ret, 0, size); | |
161 | *dma_handle = plat_map_dma_mem(dev, ret, size); | |
162 | if (!plat_device_is_coherent(dev)) { | |
163 | dma_cache_wback_inv((unsigned long) ret, size); | |
cfa93fb9 | 164 | ret = UNCAC_ADDR(ret); |
1da177e4 LT |
165 | } |
166 | ||
167 | return ret; | |
168 | } | |
169 | ||
1da177e4 | 170 | |
1e893752 CH |
171 | static void mips_dma_free_noncoherent(struct device *dev, size_t size, |
172 | void *vaddr, dma_addr_t dma_handle) | |
1da177e4 | 173 | { |
d3f634b9 | 174 | plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); |
1da177e4 LT |
175 | free_pages((unsigned long) vaddr, get_order(size)); |
176 | } | |
1da177e4 | 177 | |
48e1fd5a | 178 | static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, |
00085f1e | 179 | dma_addr_t dma_handle, unsigned long attrs) |
1da177e4 LT |
180 | { |
181 | unsigned long addr = (unsigned long) vaddr; | |
f4649382 ZLK |
182 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
183 | struct page *page = NULL; | |
f8ac0425 | 184 | |
00085f1e | 185 | if (attrs & DMA_ATTR_NON_CONSISTENT) { |
1e893752 CH |
186 | mips_dma_free_noncoherent(dev, size, vaddr, dma_handle); |
187 | return; | |
188 | } | |
189 | ||
d3f634b9 | 190 | plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); |
11531ac2 | 191 | |
cfa93fb9 | 192 | if (!plat_device_is_coherent(dev)) |
9a88cbb5 RB |
193 | addr = CAC_ADDR(addr); |
194 | ||
f4649382 ZLK |
195 | page = virt_to_page((void *) addr); |
196 | ||
197 | if (!dma_release_from_contiguous(dev, page, count)) | |
198 | __free_pages(page, get_order(size)); | |
1da177e4 LT |
199 | } |
200 | ||
8c172467 AS |
201 | static int mips_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
202 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 203 | unsigned long attrs) |
8c172467 AS |
204 | { |
205 | unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; | |
206 | unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
207 | unsigned long addr = (unsigned long)cpu_addr; | |
208 | unsigned long off = vma->vm_pgoff; | |
209 | unsigned long pfn; | |
210 | int ret = -ENXIO; | |
211 | ||
cfa93fb9 | 212 | if (!plat_device_is_coherent(dev)) |
8c172467 AS |
213 | addr = CAC_ADDR(addr); |
214 | ||
215 | pfn = page_to_pfn(virt_to_page((void *)addr)); | |
216 | ||
00085f1e | 217 | if (attrs & DMA_ATTR_WRITE_COMBINE) |
8c172467 AS |
218 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
219 | else | |
220 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
221 | ||
222 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) | |
223 | return ret; | |
224 | ||
225 | if (off < count && user_count <= (count - off)) { | |
226 | ret = remap_pfn_range(vma, vma->vm_start, | |
227 | pfn + off, | |
228 | user_count << PAGE_SHIFT, | |
229 | vma->vm_page_prot); | |
230 | } | |
231 | ||
232 | return ret; | |
233 | } | |
234 | ||
e36863a5 | 235 | static inline void __dma_sync_virtual(void *addr, size_t size, |
1da177e4 LT |
236 | enum dma_data_direction direction) |
237 | { | |
238 | switch (direction) { | |
239 | case DMA_TO_DEVICE: | |
e36863a5 | 240 | dma_cache_wback((unsigned long)addr, size); |
1da177e4 LT |
241 | break; |
242 | ||
243 | case DMA_FROM_DEVICE: | |
e36863a5 | 244 | dma_cache_inv((unsigned long)addr, size); |
1da177e4 LT |
245 | break; |
246 | ||
247 | case DMA_BIDIRECTIONAL: | |
e36863a5 | 248 | dma_cache_wback_inv((unsigned long)addr, size); |
1da177e4 LT |
249 | break; |
250 | ||
251 | default: | |
252 | BUG(); | |
253 | } | |
254 | } | |
255 | ||
e36863a5 DD |
256 | /* |
257 | * A single sg entry may refer to multiple physically contiguous | |
258 | * pages. But we still need to process highmem pages individually. | |
259 | * If highmem is not configured then the bulk of this loop gets | |
260 | * optimized out. | |
261 | */ | |
262 | static inline void __dma_sync(struct page *page, | |
263 | unsigned long offset, size_t size, enum dma_data_direction direction) | |
264 | { | |
265 | size_t left = size; | |
266 | ||
267 | do { | |
268 | size_t len = left; | |
269 | ||
270 | if (PageHighMem(page)) { | |
271 | void *addr; | |
272 | ||
273 | if (offset + len > PAGE_SIZE) { | |
274 | if (offset >= PAGE_SIZE) { | |
275 | page += offset >> PAGE_SHIFT; | |
276 | offset &= ~PAGE_MASK; | |
277 | } | |
278 | len = PAGE_SIZE - offset; | |
279 | } | |
280 | ||
281 | addr = kmap_atomic(page); | |
282 | __dma_sync_virtual(addr + offset, len, direction); | |
283 | kunmap_atomic(addr); | |
284 | } else | |
285 | __dma_sync_virtual(page_address(page) + offset, | |
286 | size, direction); | |
287 | offset = 0; | |
288 | page++; | |
289 | left -= len; | |
290 | } while (left); | |
291 | } | |
292 | ||
48e1fd5a | 293 | static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, |
00085f1e | 294 | size_t size, enum dma_data_direction direction, unsigned long attrs) |
1da177e4 | 295 | { |
9f318d47 | 296 | if (cpu_needs_post_dma_flush(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
e36863a5 DD |
297 | __dma_sync(dma_addr_to_page(dev, dma_addr), |
298 | dma_addr & ~PAGE_MASK, size, direction); | |
0acbfc66 | 299 | plat_post_dma_flush(dev); |
d3f634b9 | 300 | plat_unmap_dma_mem(dev, dma_addr, size, direction); |
1da177e4 LT |
301 | } |
302 | ||
1e51714c | 303 | static int mips_dma_map_sg(struct device *dev, struct scatterlist *sglist, |
00085f1e | 304 | int nents, enum dma_data_direction direction, unsigned long attrs) |
1da177e4 LT |
305 | { |
306 | int i; | |
1e51714c | 307 | struct scatterlist *sg; |
1da177e4 | 308 | |
1e51714c | 309 | for_each_sg(sglist, sg, nents, i) { |
9f318d47 AD |
310 | if (!plat_device_is_coherent(dev) && |
311 | !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) | |
e36863a5 DD |
312 | __dma_sync(sg_page(sg), sg->offset, sg->length, |
313 | direction); | |
4954a9a2 J |
314 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
315 | sg->dma_length = sg->length; | |
316 | #endif | |
e36863a5 DD |
317 | sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + |
318 | sg->offset; | |
1da177e4 LT |
319 | } |
320 | ||
321 | return nents; | |
322 | } | |
323 | ||
48e1fd5a DD |
324 | static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page, |
325 | unsigned long offset, size_t size, enum dma_data_direction direction, | |
00085f1e | 326 | unsigned long attrs) |
1da177e4 | 327 | { |
9f318d47 | 328 | if (!plat_device_is_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
e36863a5 | 329 | __dma_sync(page, offset, size, direction); |
1da177e4 | 330 | |
e36863a5 | 331 | return plat_map_dma_mem_page(dev, page) + offset; |
1da177e4 LT |
332 | } |
333 | ||
1e51714c | 334 | static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sglist, |
48e1fd5a | 335 | int nhwentries, enum dma_data_direction direction, |
00085f1e | 336 | unsigned long attrs) |
1da177e4 | 337 | { |
1da177e4 | 338 | int i; |
1e51714c | 339 | struct scatterlist *sg; |
1da177e4 | 340 | |
1e51714c | 341 | for_each_sg(sglist, sg, nhwentries, i) { |
9a88cbb5 | 342 | if (!plat_device_is_coherent(dev) && |
9f318d47 | 343 | !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
e36863a5 DD |
344 | direction != DMA_TO_DEVICE) |
345 | __dma_sync(sg_page(sg), sg->offset, sg->length, | |
346 | direction); | |
d3f634b9 | 347 | plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction); |
1da177e4 LT |
348 | } |
349 | } | |
350 | ||
48e1fd5a DD |
351 | static void mips_dma_sync_single_for_cpu(struct device *dev, |
352 | dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) | |
1da177e4 | 353 | { |
f86f55d3 | 354 | if (cpu_needs_post_dma_flush(dev)) |
e36863a5 DD |
355 | __dma_sync(dma_addr_to_page(dev, dma_handle), |
356 | dma_handle & ~PAGE_MASK, size, direction); | |
0acbfc66 | 357 | plat_post_dma_flush(dev); |
1da177e4 LT |
358 | } |
359 | ||
48e1fd5a DD |
360 | static void mips_dma_sync_single_for_device(struct device *dev, |
361 | dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) | |
1da177e4 | 362 | { |
e36863a5 DD |
363 | if (!plat_device_is_coherent(dev)) |
364 | __dma_sync(dma_addr_to_page(dev, dma_handle), | |
365 | dma_handle & ~PAGE_MASK, size, direction); | |
1da177e4 LT |
366 | } |
367 | ||
48e1fd5a | 368 | static void mips_dma_sync_sg_for_cpu(struct device *dev, |
1e51714c AM |
369 | struct scatterlist *sglist, int nelems, |
370 | enum dma_data_direction direction) | |
1da177e4 LT |
371 | { |
372 | int i; | |
1e51714c | 373 | struct scatterlist *sg; |
42a3b4f2 | 374 | |
1e51714c AM |
375 | if (cpu_needs_post_dma_flush(dev)) { |
376 | for_each_sg(sglist, sg, nelems, i) { | |
e36863a5 DD |
377 | __dma_sync(sg_page(sg), sg->offset, sg->length, |
378 | direction); | |
1e51714c AM |
379 | } |
380 | } | |
0acbfc66 | 381 | plat_post_dma_flush(dev); |
1da177e4 LT |
382 | } |
383 | ||
48e1fd5a | 384 | static void mips_dma_sync_sg_for_device(struct device *dev, |
1e51714c AM |
385 | struct scatterlist *sglist, int nelems, |
386 | enum dma_data_direction direction) | |
1da177e4 LT |
387 | { |
388 | int i; | |
1e51714c | 389 | struct scatterlist *sg; |
1da177e4 | 390 | |
1e51714c AM |
391 | if (!plat_device_is_coherent(dev)) { |
392 | for_each_sg(sglist, sg, nelems, i) { | |
e36863a5 DD |
393 | __dma_sync(sg_page(sg), sg->offset, sg->length, |
394 | direction); | |
1e51714c AM |
395 | } |
396 | } | |
1da177e4 LT |
397 | } |
398 | ||
48e1fd5a | 399 | int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
1da177e4 | 400 | { |
4e7f7266 | 401 | return 0; |
1da177e4 LT |
402 | } |
403 | ||
48e1fd5a | 404 | int mips_dma_supported(struct device *dev, u64 mask) |
1da177e4 | 405 | { |
843aef49 | 406 | return plat_dma_supported(dev, mask); |
1da177e4 LT |
407 | } |
408 | ||
a3aad4aa | 409 | void dma_cache_sync(struct device *dev, void *vaddr, size_t size, |
48e1fd5a | 410 | enum dma_data_direction direction) |
1da177e4 | 411 | { |
9a88cbb5 | 412 | BUG_ON(direction == DMA_NONE); |
1da177e4 | 413 | |
9a88cbb5 | 414 | if (!plat_device_is_coherent(dev)) |
e36863a5 | 415 | __dma_sync_virtual(vaddr, size, direction); |
1da177e4 LT |
416 | } |
417 | ||
a3aad4aa RB |
418 | EXPORT_SYMBOL(dma_cache_sync); |
419 | ||
48e1fd5a | 420 | static struct dma_map_ops mips_default_dma_map_ops = { |
e8d51e54 AP |
421 | .alloc = mips_dma_alloc_coherent, |
422 | .free = mips_dma_free_coherent, | |
8c172467 | 423 | .mmap = mips_dma_mmap, |
48e1fd5a DD |
424 | .map_page = mips_dma_map_page, |
425 | .unmap_page = mips_dma_unmap_page, | |
426 | .map_sg = mips_dma_map_sg, | |
427 | .unmap_sg = mips_dma_unmap_sg, | |
428 | .sync_single_for_cpu = mips_dma_sync_single_for_cpu, | |
429 | .sync_single_for_device = mips_dma_sync_single_for_device, | |
430 | .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu, | |
431 | .sync_sg_for_device = mips_dma_sync_sg_for_device, | |
432 | .mapping_error = mips_dma_mapping_error, | |
433 | .dma_supported = mips_dma_supported | |
434 | }; | |
435 | ||
436 | struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops; | |
437 | EXPORT_SYMBOL(mips_dma_map_ops); | |
438 | ||
439 | #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) | |
440 | ||
441 | static int __init mips_dma_init(void) | |
442 | { | |
443 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
444 | ||
445 | return 0; | |
446 | } | |
447 | fs_initcall(mips_dma_init); |