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CommitLineData
1da177e4
LT
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2000 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
10 */
b868868a 11#include <linux/bug.h>
1da177e4
LT
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
631330f5 16#include <linux/smp.h>
1da177e4
LT
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/string.h>
20#include <linux/types.h>
21#include <linux/pagemap.h>
22#include <linux/ptrace.h>
23#include <linux/mman.h>
24#include <linux/mm.h>
25#include <linux/bootmem.h>
26#include <linux/highmem.h>
27#include <linux/swap.h>
3d503753 28#include <linux/proc_fs.h>
22a9835c 29#include <linux/pfn.h>
0f334a3e 30#include <linux/hardirq.h>
5a0e3ad6 31#include <linux/gfp.h>
2f96b8c1 32#include <linux/kcore.h>
1da177e4 33
9975e77d 34#include <asm/asm-offsets.h>
1da177e4
LT
35#include <asm/bootinfo.h>
36#include <asm/cachectl.h>
37#include <asm/cpu.h>
38#include <asm/dma.h>
f8829cae 39#include <asm/kmap_types.h>
1da177e4
LT
40#include <asm/mmu_context.h>
41#include <asm/sections.h>
42#include <asm/pgtable.h>
43#include <asm/pgalloc.h>
44#include <asm/tlb.h>
f8829cae
RB
45#include <asm/fixmap.h>
46
1da177e4
LT
47/*
48 * We have up to 8 empty zeroed pages so we can map one of the right colour
70342287 49 * when needed. This is necessary only on R4000 / R4400 SC and MC versions
1da177e4
LT
50 * where we have to avoid VCED / VECI exceptions for good performance at
51 * any price. Since page is never written to after the initialization we
52 * don't have to care about aliases on other CPUs.
53 */
54unsigned long empty_zero_page, zero_page_mask;
497d2adc 55EXPORT_SYMBOL_GPL(empty_zero_page);
1da177e4
LT
56
57/*
58 * Not static inline because used by IP27 special magic initialization code
59 */
31605922 60void setup_zero_pages(void)
1da177e4 61{
31605922 62 unsigned int order, i;
1da177e4
LT
63 struct page *page;
64
65 if (cpu_has_vce)
66 order = 3;
67 else
68 order = 0;
69
70 empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
71 if (!empty_zero_page)
72 panic("Oh boy, that early out of memory?");
73
99e3b942 74 page = virt_to_page((void *)empty_zero_page);
8dfcc9ba 75 split_page(page, order);
31605922
JL
76 for (i = 0; i < (1 << order); i++, page++)
77 mark_page_reserved(page);
1da177e4 78
31605922 79 zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
1da177e4
LT
80}
81
7575a49f 82void *kmap_coherent(struct page *page, unsigned long addr)
f8829cae
RB
83{
84 enum fixed_addresses idx;
85 unsigned long vaddr, flags, entrylo;
86 unsigned long old_ctx;
87 pte_t pte;
88 int tlbidx;
89
b868868a
RB
90 BUG_ON(Page_dcache_dirty(page));
91
bdb43806 92 pagefault_disable();
f8829cae 93 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
0f334a3e 94 idx += in_interrupt() ? FIX_N_COLOURS : 0;
f8829cae
RB
95 vaddr = __fix_to_virt(FIX_CMAP_END - idx);
96 pte = mk_pte(page, PAGE_KERNEL);
962f480e 97#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
f8829cae
RB
98 entrylo = pte.pte_high;
99#else
6dd9344c 100 entrylo = pte_to_entrylo(pte_val(pte));
f8829cae
RB
101#endif
102
b633648c 103 local_irq_save(flags);
f8829cae
RB
104 old_ctx = read_c0_entryhi();
105 write_c0_entryhi(vaddr & (PAGE_MASK << 1));
106 write_c0_entrylo0(entrylo);
107 write_c0_entrylo1(entrylo);
f8829cae
RB
108 tlbidx = read_c0_wired();
109 write_c0_wired(tlbidx + 1);
110 write_c0_index(tlbidx);
111 mtc0_tlbw_hazard();
112 tlb_write_indexed();
f8829cae
RB
113 tlbw_use_hazard();
114 write_c0_entryhi(old_ctx);
b633648c 115 local_irq_restore(flags);
f8829cae
RB
116
117 return (void*) vaddr;
118}
119
eacb9d61 120void kunmap_coherent(void)
f8829cae 121{
f8829cae
RB
122 unsigned int wired;
123 unsigned long flags, old_ctx;
124
b633648c 125 local_irq_save(flags);
f8829cae
RB
126 old_ctx = read_c0_entryhi();
127 wired = read_c0_wired() - 1;
128 write_c0_wired(wired);
129 write_c0_index(wired);
130 write_c0_entryhi(UNIQUE_ENTRYHI(wired));
131 write_c0_entrylo0(0);
132 write_c0_entrylo1(0);
133 mtc0_tlbw_hazard();
134 tlb_write_indexed();
135 tlbw_use_hazard();
136 write_c0_entryhi(old_ctx);
b633648c 137 local_irq_restore(flags);
bdb43806 138 pagefault_enable();
f8829cae
RB
139}
140
bcd02280
AN
141void copy_user_highpage(struct page *to, struct page *from,
142 unsigned long vaddr, struct vm_area_struct *vma)
143{
144 void *vfrom, *vto;
145
9c02048f 146 vto = kmap_atomic(to);
9a74b3eb
RB
147 if (cpu_has_dc_aliases &&
148 page_mapped(from) && !Page_dcache_dirty(from)) {
bcd02280
AN
149 vfrom = kmap_coherent(from, vaddr);
150 copy_page(vto, vfrom);
eacb9d61 151 kunmap_coherent();
bcd02280 152 } else {
9c02048f 153 vfrom = kmap_atomic(from);
bcd02280 154 copy_page(vto, vfrom);
9c02048f 155 kunmap_atomic(vfrom);
bcd02280 156 }
39b8d525 157 if ((!cpu_has_ic_fills_f_dc) ||
bcd02280
AN
158 pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
159 flush_data_cache_page((unsigned long)vto);
9c02048f 160 kunmap_atomic(vto);
bcd02280
AN
161 /* Make sure this page is cleared on other CPU's too before using it */
162 smp_wmb();
163}
164
f8829cae
RB
165void copy_to_user_page(struct vm_area_struct *vma,
166 struct page *page, unsigned long vaddr, void *dst, const void *src,
167 unsigned long len)
168{
9a74b3eb
RB
169 if (cpu_has_dc_aliases &&
170 page_mapped(page) && !Page_dcache_dirty(page)) {
f8829cae
RB
171 void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
172 memcpy(vto, src, len);
eacb9d61 173 kunmap_coherent();
985c30ef 174 } else {
f8829cae 175 memcpy(dst, src, len);
985c30ef
RB
176 if (cpu_has_dc_aliases)
177 SetPageDcacheDirty(page);
178 }
f8829cae
RB
179 if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
180 flush_cache_page(vma, vaddr, page_to_pfn(page));
181}
182
f8829cae
RB
183void copy_from_user_page(struct vm_area_struct *vma,
184 struct page *page, unsigned long vaddr, void *dst, const void *src,
185 unsigned long len)
186{
9a74b3eb
RB
187 if (cpu_has_dc_aliases &&
188 page_mapped(page) && !Page_dcache_dirty(page)) {
985c30ef 189 void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
f8829cae 190 memcpy(dst, vfrom, len);
eacb9d61 191 kunmap_coherent();
985c30ef 192 } else {
f8829cae 193 memcpy(dst, src, len);
985c30ef
RB
194 if (cpu_has_dc_aliases)
195 SetPageDcacheDirty(page);
196 }
f8829cae 197}
bf9621aa 198EXPORT_SYMBOL_GPL(copy_from_user_page);
f8829cae 199
84fd089a 200void __init fixrange_init(unsigned long start, unsigned long end,
1da177e4
LT
201 pgd_t *pgd_base)
202{
b633648c 203#ifdef CONFIG_HIGHMEM
1da177e4 204 pgd_t *pgd;
c6e8b587 205 pud_t *pud;
1da177e4
LT
206 pmd_t *pmd;
207 pte_t *pte;
c6e8b587 208 int i, j, k;
1da177e4
LT
209 unsigned long vaddr;
210
211 vaddr = start;
212 i = __pgd_offset(vaddr);
c6e8b587
RB
213 j = __pud_offset(vaddr);
214 k = __pmd_offset(vaddr);
1da177e4
LT
215 pgd = pgd_base + i;
216
464fd83e 217 for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
c6e8b587 218 pud = (pud_t *)pgd;
464fd83e 219 for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
c6e8b587 220 pmd = (pmd_t *)pud;
464fd83e 221 for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
c6e8b587
RB
222 if (pmd_none(*pmd)) {
223 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
f8829cae 224 set_pmd(pmd, __pmd((unsigned long)pte));
b72b7092 225 BUG_ON(pte != pte_offset_kernel(pmd, 0));
c6e8b587
RB
226 }
227 vaddr += PMD_SIZE;
1da177e4 228 }
c6e8b587 229 k = 0;
1da177e4
LT
230 }
231 j = 0;
232 }
f8829cae 233#endif
1da177e4 234}
1da177e4 235
b4819b59 236#ifndef CONFIG_NEED_MULTIPLE_NODES
61ef2489 237int page_is_ram(unsigned long pagenr)
565200a1
AN
238{
239 int i;
240
241 for (i = 0; i < boot_mem_map.nr_map; i++) {
242 unsigned long addr, end;
243
43064c0c
DD
244 switch (boot_mem_map.map[i].type) {
245 case BOOT_MEM_RAM:
246 case BOOT_MEM_INIT_RAM:
247 break;
248 default:
565200a1
AN
249 /* not usable memory */
250 continue;
43064c0c 251 }
565200a1
AN
252
253 addr = PFN_UP(boot_mem_map.map[i].addr);
254 end = PFN_DOWN(boot_mem_map.map[i].addr +
255 boot_mem_map.map[i].size);
256
257 if (pagenr >= addr && pagenr < end)
258 return 1;
259 }
260
261 return 0;
262}
263
1da177e4
LT
264void __init paging_init(void)
265{
cce335ae 266 unsigned long max_zone_pfns[MAX_NR_ZONES];
d3ce0e98 267 unsigned long lastpfn __maybe_unused;
1da177e4
LT
268
269 pagetable_init();
270
271#ifdef CONFIG_HIGHMEM
272 kmap_init();
273#endif
05502339 274#ifdef CONFIG_ZONE_DMA
cce335ae 275 max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
1da177e4 276#endif
cce335ae
RB
277#ifdef CONFIG_ZONE_DMA32
278 max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
279#endif
280 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
281 lastpfn = max_low_pfn;
1da177e4 282#ifdef CONFIG_HIGHMEM
cce335ae
RB
283 max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
284 lastpfn = highend_pfn;
cbb8fc07 285
cce335ae 286 if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
cbb8fc07 287 printk(KERN_WARNING "This processor doesn't support highmem."
cce335ae
RB
288 " %ldk highmem ignored\n",
289 (highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
290 max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
291 lastpfn = max_low_pfn;
cbb8fc07 292 }
1da177e4
LT
293#endif
294
cce335ae 295 free_area_init_nodes(max_zone_pfns);
1da177e4
LT
296}
297
3d503753
DJ
298#ifdef CONFIG_64BIT
299static struct kcore_list kcore_kseg0;
300#endif
301
1132137e 302static inline void mem_init_free_highmem(void)
1da177e4 303{
1132137e
JL
304#ifdef CONFIG_HIGHMEM
305 unsigned long tmp;
1da177e4 306
1132137e
JL
307 for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
308 struct page *page = pfn_to_page(tmp);
309
310 if (!page_is_ram(tmp))
311 SetPageReserved(page);
312 else
313 free_highmem_page(page);
314 }
315#endif
316}
317
318void __init mem_init(void)
319{
1da177e4
LT
320#ifdef CONFIG_HIGHMEM
321#ifdef CONFIG_DISCONTIGMEM
322#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
323#endif
b6da0ffb 324 max_mapnr = highend_pfn ? highend_pfn : max_low_pfn;
1da177e4 325#else
565200a1 326 max_mapnr = max_low_pfn;
1da177e4
LT
327#endif
328 high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
329
0c988534 330 free_all_bootmem();
31605922 331 setup_zero_pages(); /* Setup zeroed pages. */
1132137e
JL
332 mem_init_free_highmem();
333 mem_init_print_info(NULL);
1da177e4 334
3d503753
DJ
335#ifdef CONFIG_64BIT
336 if ((unsigned long) &_text > (unsigned long) CKSEG0)
337 /* The -4 is a hack so that user tools don't have to handle
338 the overflow. */
c30bb2a2
KH
339 kclist_add(&kcore_kseg0, (void *) CKSEG0,
340 0x80000000 - 4, KCORE_TEXT);
3d503753 341#endif
1da177e4 342}
b4819b59 343#endif /* !CONFIG_NEED_MULTIPLE_NODES */
1da177e4 344
c44e8d5e 345void free_init_pages(const char *what, unsigned long begin, unsigned long end)
6fd11a21 346{
acd86b86 347 unsigned long pfn;
6fd11a21 348
acd86b86
FBH
349 for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
350 struct page *page = pfn_to_page(pfn);
351 void *addr = phys_to_virt(PFN_PHYS(pfn));
352
acd86b86 353 memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
31605922 354 free_reserved_page(page);
6fd11a21
RB
355 }
356 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
357}
358
1da177e4
LT
359#ifdef CONFIG_BLK_DEV_INITRD
360void free_initrd_mem(unsigned long start, unsigned long end)
361{
11199692
JL
362 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
363 "initrd");
1da177e4
LT
364}
365#endif
366
0893d3fb
MC
367void (*free_init_pages_eva)(void *begin, void *end) = NULL;
368
fb4bb133 369void __init_refok free_initmem(void)
1da177e4 370{
c44e8d5e 371 prom_free_prom_memory();
0893d3fb
MC
372 /*
373 * Let the platform define a specific function to free the
374 * init section since EVA may have used any possible mapping
375 * between virtual and physical addresses.
376 */
377 if (free_init_pages_eva)
378 free_init_pages_eva((void *)&__init_begin, (void *)&__init_end);
379 else
380 free_initmem_default(POISON_FREE_INITMEM);
1da177e4 381}
69a6c312 382
82622284 383#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
69a6c312 384unsigned long pgd_current[NR_CPUS];
82622284 385#endif
9975e77d
RB
386
387/*
388 * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
389 * are constants. So we use the variants from asm-offset.h until that gcc
390 * will officially be retired.
485172b3
DD
391 *
392 * Align swapper_pg_dir in to 64K, allows its address to be loaded
393 * with a single LUI instruction in the TLB handlers. If we used
394 * __aligned(64K), its size would get rounded up to the alignment
395 * size, and waste space. So we place it in its own section and align
396 * it in the linker script.
9975e77d 397 */
485172b3 398pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
325f8a0a 399#ifndef __PAGETABLE_PMD_FOLDED
485172b3 400pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
69a6c312 401#endif
485172b3 402pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;