[mirror_ubuntu-zesty-kernel.git] / arch / mips / pci / pci-bcm1480.c

/*
 * Copyright (C) 2001,2002,2005 Broadcom Corporation
 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

/*
 * BCM1x80/1x55-specific PCI support
 *
 * This module provides the glue between Linux's PCI subsystem
 * and the hardware.  We basically provide glue for accessing
 * configuration space, and set up the translation for I/O
 * space accesses.
 *
 * To access configuration space, we use ioremap.  In the 32-bit
 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
 * kernel mapped memory.  Hopefully neither of these should be a huge
 * problem.
 *
 * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
 */
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/console.h>
#include <linux/tty.h>

#include <asm/sibyte/bcm1480_regs.h>
#include <asm/sibyte/bcm1480_scd.h>
#include <asm/sibyte/board.h>
#include <asm/io.h>

/*
 * Macros for calculating offsets into config space given a device
 * structure or dev/fun/reg
 */
#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
#define CFGADDR(bus,devfn,where)   CFGOFFSET((bus)->number,(devfn),where)

static void *cfg_space;

#define PCI_BUS_ENABLED	1
#define PCI_DEVICE_MODE	2

static int bcm1480_bus_status = 0;

#define PCI_BRIDGE_DEVICE  0

/*
 * Read/write 32-bit values in config space.
 */
static inline u32 READCFG32(u32 addr)
{
	return *(u32 *)(cfg_space + (addr&~3));
}

static inline void WRITECFG32(u32 addr, u32 data)
{
	*(u32 *)(cfg_space + (addr & ~3)) = data;
}

int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	return dev->irq;
}

/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}

/*
 * Some checks before doing config cycles:
 * In PCI Device Mode, hide everything on bus 0 except the LDT host
 * bridge.  Otherwise, access is controlled by bridge MasterEn bits.
 */
static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
{
	u32 devno;

	if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
		return 0;

	if (bus->number == 0) {
		devno = PCI_SLOT(devfn);
		if (bcm1480_bus_status & PCI_DEVICE_MODE)
			return 0;
		else
			return 1;
	} else
		return 1;
}

/*
 * Read/write access functions for various sizes of values
 * in config space.  Return all 1's for disallowed accesses
 * for a kludgy but adequate simulation of master aborts.
 */

static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
				int where, int size, u32 * val)
{
	u32 data = 0;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (bcm1480_pci_can_access(bus, devfn))
		data = READCFG32(CFGADDR(bus, devfn, where));
	else
		data = 0xFFFFFFFF;

	if (size == 1)
		*val = (data >> ((where & 3) << 3)) & 0xff;
	else if (size == 2)
		*val = (data >> ((where & 3) << 3)) & 0xffff;
	else
		*val = data;

	return PCIBIOS_SUCCESSFUL;
}

static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
				int where, int size, u32 val)
{
	u32 cfgaddr = CFGADDR(bus, devfn, where);
	u32 data = 0;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!bcm1480_pci_can_access(bus, devfn))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	data = READCFG32(cfgaddr);

	if (size == 1)
		data = (data & ~(0xff << ((where & 3) << 3))) |
		    (val << ((where & 3) << 3));
	else if (size == 2)
		data = (data & ~(0xffff << ((where & 3) << 3))) |
		    (val << ((where & 3) << 3));
	else
		data = val;

	WRITECFG32(cfgaddr, data);

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops bcm1480_pci_ops = {
	bcm1480_pcibios_read,
	bcm1480_pcibios_write,
};

static struct resource bcm1480_mem_resource = {
	.name	= "BCM1480 PCI MEM",
	.start	= 0x30000000UL,
	.end	= 0x3fffffffUL,
	.flags	= IORESOURCE_MEM,
};

static struct resource bcm1480_io_resource = {
	.name	= "BCM1480 PCI I/O",
	.start	= 0x2c000000UL,
	.end	= 0x2dffffffUL,
	.flags	= IORESOURCE_IO,
};

struct pci_controller bcm1480_controller = {
	.pci_ops	= &bcm1480_pci_ops,
	.mem_resource	= &bcm1480_mem_resource,
	.io_resource	= &bcm1480_io_resource,
};


static int __init bcm1480_pcibios_init(void)
{
	uint32_t cmdreg;
	uint64_t reg;
	extern int pci_probe_only;

	/* CFE will assign PCI resources */
	pci_probe_only = 1;

	/* Avoid ISA compat ranges.  */
	PCIBIOS_MIN_IO = 0x00008000UL;
	PCIBIOS_MIN_MEM = 0x01000000UL;

	/* Set I/O resource limits. - unlimited for now to accomodate HT */
	ioport_resource.end = 0xffffffffUL;
	iomem_resource.end = 0xffffffffUL;

	cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);

	/*
	 * See if the PCI bus has been configured by the firmware.
	 */
	reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
	if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
		bcm1480_bus_status |= PCI_DEVICE_MODE;
	} else {
		cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
					     PCI_COMMAND));
		if (!(cmdreg & PCI_COMMAND_MASTER)) {
			printk
			    ("PCI: Skipping PCI probe.  Bus is not initialized.\n");
			iounmap(cfg_space);
			return 1; /* XXX */
		}
		bcm1480_bus_status |= PCI_BUS_ENABLED;
	}

	/* turn on ExpMemEn */
	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
	WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
			cmdreg | 0x10);
	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));

	/*
	 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
	 * space.  Use "match bytes" policy to make everything look
	 * little-endian.  So, you need to also set
	 * CONFIG_SWAP_IO_SPACE, but this is the combination that
	 * works correctly with most of Linux's drivers.
	 * XXX ehs: Should this happen in PCI Device mode?
	 */

	set_io_port_base((unsigned long)
		ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536));
	isa_slot_offset = (unsigned long)
		ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);

	register_pci_controller(&bcm1480_controller);

#ifdef CONFIG_VGA_CONSOLE
	take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1);
#endif
	return 0;
}

arch_initcall(bcm1480_pcibios_init);
Commit	Line	Data
dc41f94f AI	1	/*
	2	* Copyright (C) 2001,2002,2005 Broadcom Corporation
	3	* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	18	*/
	19
	20	/*
	21	* BCM1x80/1x55-specific PCI support
	22	*
	23	* This module provides the glue between Linux's PCI subsystem
	24	* and the hardware. We basically provide glue for accessing
	25	* configuration space, and set up the translation for I/O
	26	* space accesses.
	27	*
	28	* To access configuration space, we use ioremap. In the 32-bit
	29	* kernel, this consumes either 4 or 8 page table pages, and 16MB of
	30	* kernel mapped memory. Hopefully neither of these should be a huge
	31	* problem.
	32	*
	33	* XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
	34	*/
dc41f94f AI	35	#include <linux/types.h>
	36	#include <linux/pci.h>
	37	#include <linux/kernel.h>
	38	#include <linux/init.h>
	39	#include <linux/mm.h>
	40	#include <linux/console.h>
	41	#include <linux/tty.h>
	42
	43	#include <asm/sibyte/bcm1480_regs.h>
	44	#include <asm/sibyte/bcm1480_scd.h>
	45	#include <asm/sibyte/board.h>
	46	#include <asm/io.h>
	47
	48	/*
	49	* Macros for calculating offsets into config space given a device
	50	* structure or dev/fun/reg
	51	*/
	52	#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
	53	#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
	54
	55	static void *cfg_space;
	56
	57	#define PCI_BUS_ENABLED 1
8a1417de	58	#define PCI_DEVICE_MODE 2
dc41f94f AI	59
	60	static int bcm1480_bus_status = 0;
	61
	62	#define PCI_BRIDGE_DEVICE 0
dc41f94f AI	63
	64	/*
	65	* Read/write 32-bit values in config space.
	66	*/
	67	static inline u32 READCFG32(u32 addr)
	68	{
	69	return (u32 )(cfg_space + (addr&~3));
	70	}
	71
	72	static inline void WRITECFG32(u32 addr, u32 data)
	73	{
	74	(u32 )(cfg_space + (addr & ~3)) = data;
	75	}
	76
	77	int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	78	{
	79	return dev->irq;
	80	}
	81
	82	/* Do platform specific device initialization at pci_enable_device() time */
	83	int pcibios_plat_dev_init(struct pci_dev *dev)
	84	{
	85	return 0;
	86	}
	87
	88	/*
	89	* Some checks before doing config cycles:
	90	* In PCI Device Mode, hide everything on bus 0 except the LDT host
	91	* bridge. Otherwise, access is controlled by bridge MasterEn bits.
	92	*/
	93	static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
	94	{
8a1417de AI	95	u32 devno;
8a1417de AI	96
dc41f94f AI	97	if (!(bcm1480_bus_status & (PCI_BUS_ENABLED \| PCI_DEVICE_MODE)))
	98	return 0;
	99
	100	if (bus->number == 0) {
8a1417de	101	devno = PCI_SLOT(devfn);
a3dddd56	102	if (bcm1480_bus_status & PCI_DEVICE_MODE)
dc41f94f AI	103	return 0;
	104	else
	105	return 1;
	106	} else
	107	return 1;
	108	}
	109
	110	/*
	111	* Read/write access functions for various sizes of values
	112	* in config space. Return all 1's for disallowed accesses
	113	* for a kludgy but adequate simulation of master aborts.
	114	*/
	115
	116	static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
	117	int where, int size, u32 * val)
	118	{
	119	u32 data = 0;
	120
	121	if ((size == 2) && (where & 1))
	122	return PCIBIOS_BAD_REGISTER_NUMBER;
	123	else if ((size == 4) && (where & 3))
	124	return PCIBIOS_BAD_REGISTER_NUMBER;
	125
	126	if (bcm1480_pci_can_access(bus, devfn))
	127	data = READCFG32(CFGADDR(bus, devfn, where));
	128	else
	129	data = 0xFFFFFFFF;
	130
	131	if (size == 1)
	132	*val = (data >> ((where & 3) << 3)) & 0xff;
	133	else if (size == 2)
	134	*val = (data >> ((where & 3) << 3)) & 0xffff;
	135	else
	136	*val = data;
	137
	138	return PCIBIOS_SUCCESSFUL;
	139	}
	140
	141	static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
	142	int where, int size, u32 val)
	143	{
	144	u32 cfgaddr = CFGADDR(bus, devfn, where);
	145	u32 data = 0;
	146
	147	if ((size == 2) && (where & 1))
	148	return PCIBIOS_BAD_REGISTER_NUMBER;
	149	else if ((size == 4) && (where & 3))
	150	return PCIBIOS_BAD_REGISTER_NUMBER;
	151
	152	if (!bcm1480_pci_can_access(bus, devfn))
	153	return PCIBIOS_BAD_REGISTER_NUMBER;
	154
	155	data = READCFG32(cfgaddr);
	156
	157	if (size == 1)
	158	data = (data & ~(0xff << ((where & 3) << 3))) \|
	159	(val << ((where & 3) << 3));
	160	else if (size == 2)
	161	data = (data & ~(0xffff << ((where & 3) << 3))) \|
	162	(val << ((where & 3) << 3));
	163	else
	164	data = val;
	165
	166	WRITECFG32(cfgaddr, data);
167
168	return PCIBIOS_SUCCESSFUL;
169	}
170
171	struct pci_ops bcm1480_pci_ops = {
172	bcm1480_pcibios_read,
173	bcm1480_pcibios_write,
174	};
175
176	static struct resource bcm1480_mem_resource = {
177	.name = "BCM1480 PCI MEM",
8a1417de AI	178	.start = 0x30000000UL,
8a1417de AI	179	.end = 0x3fffffffUL,
dc41f94f AI	180	.flags = IORESOURCE_MEM,
	181	};
	182
	183	static struct resource bcm1480_io_resource = {
	184	.name = "BCM1480 PCI I/O",
8a1417de AI	185	.start = 0x2c000000UL,
8a1417de AI	186	.end = 0x2dffffffUL,
dc41f94f AI	187	.flags = IORESOURCE_IO,
	188	};
	189
	190	struct pci_controller bcm1480_controller = {
	191	.pci_ops = &bcm1480_pci_ops,
	192	.mem_resource = &bcm1480_mem_resource,
	193	.io_resource = &bcm1480_io_resource,
	194	};
	195
	196
	197	static int __init bcm1480_pcibios_init(void)
	198	{
	199	uint32_t cmdreg;
	200	uint64_t reg;
	201	extern int pci_probe_only;
	202
	203	/* CFE will assign PCI resources */
	204	pci_probe_only = 1;
	205
	206	/* Avoid ISA compat ranges. */
	207	PCIBIOS_MIN_IO = 0x00008000UL;
	208	PCIBIOS_MIN_MEM = 0x01000000UL;
	209
8a1417de AI	210	/* Set I/O resource limits. - unlimited for now to accomodate HT */
	211	ioport_resource.end = 0xffffffffUL;
	212	iomem_resource.end = 0xffffffffUL;
dc41f94f AI	213
	214	cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 1610241024);
	215
	216	/*
	217	* See if the PCI bus has been configured by the firmware.
	218	*/
8fb303c7	219	reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
dc41f94f AI	220	if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
	221	bcm1480_bus_status \|= PCI_DEVICE_MODE;
	222	} else {
	223	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
	224	PCI_COMMAND));
	225	if (!(cmdreg & PCI_COMMAND_MASTER)) {
	226	printk
	227	("PCI: Skipping PCI probe. Bus is not initialized.\n");
	228	iounmap(cfg_space);
	229	return 1; /* XXX */
	230	}
	231	bcm1480_bus_status \|= PCI_BUS_ENABLED;
	232	}
	233
cb426248 AI	234	/* turn on ExpMemEn */
cb426248 AI	235	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
cb426248 AI	236	WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
	237	cmdreg \| 0x10);
	238	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
cb426248	239
dc41f94f AI	240	/*
	241	* Establish mappings in KSEG2 (kernel virtual) to PCI I/O
	242	* space. Use "match bytes" policy to make everything look
	243	* little-endian. So, you need to also set
	244	* CONFIG_SWAP_IO_SPACE, but this is the combination that
	245	* works correctly with most of Linux's drivers.
	246	* XXX ehs: Should this happen in PCI Device mode?
	247	*/
	248
	249	set_io_port_base((unsigned long)
	250	ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536));
	251	isa_slot_offset = (unsigned long)
	252	ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
	253
	254	register_pci_controller(&bcm1480_controller);
	255
	256	#ifdef CONFIG_VGA_CONSOLE
	257	take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1);
	258	#endif
	259	return 0;
	260	}
	261
	262	arch_initcall(bcm1480_pcibios_init);