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1da177e4 LT |
1 | /* |
2 | * pci-vr41xx.c, PCI Control Unit routines for the NEC VR4100 series. | |
3 | * | |
4 | * Copyright (C) 2001-2003 MontaVista Software Inc. | |
5 | * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com> | |
6 | * Copyright (C) 2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> | |
7 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | /* | |
24 | * Changes: | |
25 | * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com> | |
26 | * - New creation, NEC VR4122 and VR4131 are supported. | |
27 | */ | |
28 | #include <linux/init.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/types.h> | |
31 | ||
32 | #include <asm/cpu.h> | |
33 | #include <asm/io.h> | |
34 | #include <asm/vr41xx/vr41xx.h> | |
35 | ||
36 | #include "pci-vr41xx.h" | |
37 | ||
38 | extern struct pci_ops vr41xx_pci_ops; | |
39 | ||
40 | static struct pci_master_address_conversion pci_master_memory1 = { | |
41 | .bus_base_address = PCI_MASTER_MEM1_BUS_BASE_ADDRESS, | |
42 | .address_mask = PCI_MASTER_MEM1_ADDRESS_MASK, | |
43 | .pci_base_address = PCI_MASTER_MEM1_PCI_BASE_ADDRESS, | |
44 | }; | |
45 | ||
46 | static struct pci_target_address_conversion pci_target_memory1 = { | |
47 | .address_mask = PCI_TARGET_MEM1_ADDRESS_MASK, | |
48 | .bus_base_address = PCI_TARGET_MEM1_BUS_BASE_ADDRESS, | |
49 | }; | |
50 | ||
51 | static struct pci_master_address_conversion pci_master_io = { | |
52 | .bus_base_address = PCI_MASTER_IO_BUS_BASE_ADDRESS, | |
53 | .address_mask = PCI_MASTER_IO_ADDRESS_MASK, | |
54 | .pci_base_address = PCI_MASTER_IO_PCI_BASE_ADDRESS, | |
55 | }; | |
56 | ||
57 | static struct pci_mailbox_address pci_mailbox = { | |
58 | .base_address = PCI_MAILBOX_BASE_ADDRESS, | |
59 | }; | |
60 | ||
61 | static struct pci_target_address_window pci_target_window1 = { | |
62 | .base_address = PCI_TARGET_WINDOW1_BASE_ADDRESS, | |
63 | }; | |
64 | ||
65 | static struct resource pci_mem_resource = { | |
66 | .name = "PCI Memory resources", | |
67 | .start = PCI_MEM_RESOURCE_START, | |
68 | .end = PCI_MEM_RESOURCE_END, | |
69 | .flags = IORESOURCE_MEM, | |
70 | }; | |
71 | ||
72 | static struct resource pci_io_resource = { | |
73 | .name = "PCI I/O resources", | |
74 | .start = PCI_IO_RESOURCE_START, | |
75 | .end = PCI_IO_RESOURCE_END, | |
76 | .flags = IORESOURCE_IO, | |
77 | }; | |
78 | ||
79 | static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = { | |
80 | .master_memory1 = &pci_master_memory1, | |
81 | .target_memory1 = &pci_target_memory1, | |
82 | .master_io = &pci_master_io, | |
83 | .exclusive_access = CANNOT_LOCK_FROM_DEVICE, | |
84 | .wait_time_limit_from_irdy_to_trdy = 0, | |
85 | .mailbox = &pci_mailbox, | |
86 | .target_window1 = &pci_target_window1, | |
87 | .master_latency_timer = 0x80, | |
88 | .retry_limit = 0, | |
89 | .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR, | |
90 | .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE, | |
91 | }; | |
92 | ||
93 | static struct pci_controller vr41xx_pci_controller = { | |
94 | .pci_ops = &vr41xx_pci_ops, | |
95 | .mem_resource = &pci_mem_resource, | |
96 | .io_resource = &pci_io_resource, | |
97 | }; | |
98 | ||
99 | void __init vr41xx_pciu_setup(struct pci_controller_unit_setup *setup) | |
100 | { | |
101 | vr41xx_pci_controller_unit_setup = *setup; | |
102 | } | |
103 | ||
104 | static int __init vr41xx_pciu_init(void) | |
105 | { | |
106 | struct pci_controller_unit_setup *setup; | |
107 | struct pci_master_address_conversion *master; | |
108 | struct pci_target_address_conversion *target; | |
109 | struct pci_mailbox_address *mailbox; | |
110 | struct pci_target_address_window *window; | |
111 | unsigned long vtclock, pci_clock_max; | |
112 | uint32_t val; | |
113 | ||
114 | setup = &vr41xx_pci_controller_unit_setup; | |
115 | ||
116 | /* Disable PCI interrupt */ | |
117 | vr41xx_disable_pciint(); | |
118 | ||
119 | /* Supply VTClock to PCIU */ | |
120 | vr41xx_supply_clock(PCIU_CLOCK); | |
121 | ||
122 | /* Dummy write, waiting for supply of VTClock. */ | |
123 | vr41xx_disable_pciint(); | |
124 | ||
125 | /* Select PCI clock */ | |
126 | if (setup->pci_clock_max != 0) | |
127 | pci_clock_max = setup->pci_clock_max; | |
128 | else | |
129 | pci_clock_max = PCI_CLOCK_MAX; | |
130 | vtclock = vr41xx_get_vtclock_frequency(); | |
131 | if (vtclock < pci_clock_max) | |
132 | writel(EQUAL_VTCLOCK, PCICLKSELREG); | |
133 | else if ((vtclock / 2) < pci_clock_max) | |
134 | writel(HALF_VTCLOCK, PCICLKSELREG); | |
135 | else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 && | |
136 | (vtclock / 3) < pci_clock_max) | |
137 | writel(ONE_THIRD_VTCLOCK, PCICLKSELREG); | |
138 | else if ((vtclock / 4) < pci_clock_max) | |
139 | writel(QUARTER_VTCLOCK, PCICLKSELREG); | |
140 | else { | |
141 | printk(KERN_ERR "PCI Clock is over 33MHz.\n"); | |
142 | return -EINVAL; | |
143 | } | |
144 | ||
145 | /* Supply PCI clock by PCI bus */ | |
146 | vr41xx_supply_clock(PCI_CLOCK); | |
147 | ||
148 | if (setup->master_memory1 != NULL) { | |
149 | master = setup->master_memory1; | |
150 | val = IBA(master->bus_base_address) | | |
151 | MASTER_MSK(master->address_mask) | | |
152 | WINEN | | |
153 | PCIA(master->pci_base_address); | |
154 | writel(val, PCIMMAW1REG); | |
155 | } else { | |
156 | val = readl(PCIMMAW1REG); | |
157 | val &= ~WINEN; | |
158 | writel(val, PCIMMAW1REG); | |
159 | } | |
160 | ||
161 | if (setup->master_memory2 != NULL) { | |
162 | master = setup->master_memory2; | |
163 | val = IBA(master->bus_base_address) | | |
164 | MASTER_MSK(master->address_mask) | | |
165 | WINEN | | |
166 | PCIA(master->pci_base_address); | |
167 | writel(val, PCIMMAW2REG); | |
168 | } else { | |
169 | val = readl(PCIMMAW2REG); | |
170 | val &= ~WINEN; | |
171 | writel(val, PCIMMAW2REG); | |
172 | } | |
173 | ||
174 | if (setup->target_memory1 != NULL) { | |
175 | target = setup->target_memory1; | |
176 | val = TARGET_MSK(target->address_mask) | | |
177 | WINEN | | |
178 | ITA(target->bus_base_address); | |
179 | writel(val, PCITAW1REG); | |
180 | } else { | |
181 | val = readl(PCITAW1REG); | |
182 | val &= ~WINEN; | |
183 | writel(val, PCITAW1REG); | |
184 | } | |
185 | ||
186 | if (setup->target_memory2 != NULL) { | |
187 | target = setup->target_memory2; | |
188 | val = TARGET_MSK(target->address_mask) | | |
189 | WINEN | | |
190 | ITA(target->bus_base_address); | |
191 | writel(val, PCITAW2REG); | |
192 | } else { | |
193 | val = readl(PCITAW2REG); | |
194 | val &= ~WINEN; | |
195 | writel(val, PCITAW2REG); | |
196 | } | |
197 | ||
198 | if (setup->master_io != NULL) { | |
199 | master = setup->master_io; | |
200 | val = IBA(master->bus_base_address) | | |
201 | MASTER_MSK(master->address_mask) | | |
202 | WINEN | | |
203 | PCIIA(master->pci_base_address); | |
204 | writel(val, PCIMIOAWREG); | |
205 | } else { | |
206 | val = readl(PCIMIOAWREG); | |
207 | val &= ~WINEN; | |
208 | writel(val, PCIMIOAWREG); | |
209 | } | |
210 | ||
211 | if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE) | |
212 | writel(UNLOCK, PCIEXACCREG); | |
213 | else | |
214 | writel(0, PCIEXACCREG); | |
215 | ||
216 | if (current_cpu_data.cputype == CPU_VR4122) | |
217 | writel(TRDYV(setup->wait_time_limit_from_irdy_to_trdy), PCITRDYVREG); | |
218 | ||
219 | writel(MLTIM(setup->master_latency_timer), LATTIMEREG); | |
220 | ||
221 | if (setup->mailbox != NULL) { | |
222 | mailbox = setup->mailbox; | |
223 | val = MBADD(mailbox->base_address) | TYPE_32BITSPACE | | |
224 | MSI_MEMORY | PREF_APPROVAL; | |
225 | writel(val, MAILBAREG); | |
226 | } | |
227 | ||
228 | if (setup->target_window1) { | |
229 | window = setup->target_window1; | |
230 | val = PMBA(window->base_address) | TYPE_32BITSPACE | | |
231 | MSI_MEMORY | PREF_APPROVAL; | |
232 | writel(val, PCIMBA1REG); | |
233 | } | |
234 | ||
235 | if (setup->target_window2) { | |
236 | window = setup->target_window2; | |
237 | val = PMBA(window->base_address) | TYPE_32BITSPACE | | |
238 | MSI_MEMORY | PREF_APPROVAL; | |
239 | writel(val, PCIMBA2REG); | |
240 | } | |
241 | ||
242 | val = readl(RETVALREG); | |
243 | val &= ~RTYVAL_MASK; | |
244 | val |= RTYVAL(setup->retry_limit); | |
245 | writel(val, RETVALREG); | |
246 | ||
247 | val = readl(PCIAPCNTREG); | |
248 | val &= ~(TKYGNT | PAPC); | |
249 | ||
250 | switch (setup->arbiter_priority_control) { | |
251 | case PCI_ARBITRATION_MODE_ALTERNATE_0: | |
252 | val |= PAPC_ALTERNATE_0; | |
253 | break; | |
254 | case PCI_ARBITRATION_MODE_ALTERNATE_B: | |
255 | val |= PAPC_ALTERNATE_B; | |
256 | break; | |
257 | default: | |
258 | val |= PAPC_FAIR; | |
259 | break; | |
260 | } | |
261 | ||
262 | if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE) | |
263 | val |= TKYGNT_ENABLE; | |
264 | ||
265 | writel(val, PCIAPCNTREG); | |
266 | ||
267 | writel(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | | |
268 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, COMMANDREG); | |
269 | ||
270 | /* Clear bus error */ | |
271 | readl(BUSERRADREG); | |
272 | ||
273 | writel(BLOODY_CONFIG_DONE, PCIENREG); | |
274 | ||
275 | if (setup->mem_resource != NULL) | |
276 | vr41xx_pci_controller.mem_resource = setup->mem_resource; | |
277 | ||
278 | if (setup->io_resource != NULL) { | |
279 | vr41xx_pci_controller.io_resource = setup->io_resource; | |
280 | } else { | |
281 | set_io_port_base(IO_PORT_BASE); | |
282 | ioport_resource.start = IO_PORT_RESOURCE_START; | |
283 | ioport_resource.end = IO_PORT_RESOURCE_END; | |
284 | } | |
285 | ||
286 | register_pci_controller(&vr41xx_pci_controller); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | arch_initcall(vr41xx_pciu_init); |