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368dd5ac AT |
1 | /* SMP support routines. |
2 | * | |
3 | * Copyright (C) 2006-2008 Panasonic Corporation | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/interrupt.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/jiffies.h> | |
20 | #include <linux/cpumask.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/sched.h> | |
29930025 | 25 | #include <linux/sched/task.h> |
368dd5ac AT |
26 | #include <linux/profile.h> |
27 | #include <linux/smp.h> | |
568b4455 | 28 | #include <linux/cpu.h> |
368dd5ac | 29 | #include <asm/tlbflush.h> |
368dd5ac AT |
30 | #include <asm/bitops.h> |
31 | #include <asm/processor.h> | |
32 | #include <asm/bug.h> | |
33 | #include <asm/exceptions.h> | |
34 | #include <asm/hardirq.h> | |
35 | #include <asm/fpu.h> | |
36 | #include <asm/mmu_context.h> | |
37 | #include <asm/thread_info.h> | |
38 | #include <asm/cpu-regs.h> | |
39 | #include <asm/intctl-regs.h> | |
40 | #include "internal.h" | |
41 | ||
42 | #ifdef CONFIG_HOTPLUG_CPU | |
368dd5ac AT |
43 | #include <asm/cacheflush.h> |
44 | ||
45 | static unsigned long sleep_mode[NR_CPUS]; | |
46 | ||
47 | static void run_sleep_cpu(unsigned int cpu); | |
48 | static void run_wakeup_cpu(unsigned int cpu); | |
49 | #endif /* CONFIG_HOTPLUG_CPU */ | |
50 | ||
51 | /* | |
52 | * Debug Message function | |
53 | */ | |
54 | ||
55 | #undef DEBUG_SMP | |
56 | #ifdef DEBUG_SMP | |
57 | #define Dprintk(fmt, ...) printk(KERN_DEBUG fmt, ##__VA_ARGS__) | |
58 | #else | |
59 | #define Dprintk(fmt, ...) no_printk(KERN_DEBUG fmt, ##__VA_ARGS__) | |
60 | #endif | |
61 | ||
62 | /* timeout value in msec for smp_nmi_call_function. zero is no timeout. */ | |
63 | #define CALL_FUNCTION_NMI_IPI_TIMEOUT 0 | |
64 | ||
65 | /* | |
66 | * Structure and data for smp_nmi_call_function(). | |
67 | */ | |
68 | struct nmi_call_data_struct { | |
69 | smp_call_func_t func; | |
70 | void *info; | |
71 | cpumask_t started; | |
72 | cpumask_t finished; | |
73 | int wait; | |
74 | char size_alignment[0] | |
75 | __attribute__ ((__aligned__(SMP_CACHE_BYTES))); | |
76 | } __attribute__ ((__aligned__(SMP_CACHE_BYTES))); | |
77 | ||
78 | static DEFINE_SPINLOCK(smp_nmi_call_lock); | |
79 | static struct nmi_call_data_struct *nmi_call_data; | |
80 | ||
81 | /* | |
82 | * Data structures and variables | |
83 | */ | |
84 | static cpumask_t cpu_callin_map; /* Bitmask of callin CPUs */ | |
85 | static cpumask_t cpu_callout_map; /* Bitmask of callout CPUs */ | |
86 | cpumask_t cpu_boot_map; /* Bitmask of boot APs */ | |
87 | unsigned long start_stack[NR_CPUS - 1]; | |
88 | ||
89 | /* | |
90 | * Per CPU parameters | |
91 | */ | |
92 | struct mn10300_cpuinfo cpu_data[NR_CPUS] __cacheline_aligned; | |
93 | ||
94 | static int cpucount; /* The count of boot CPUs */ | |
95 | static cpumask_t smp_commenced_mask; | |
96 | cpumask_t cpu_initialized __initdata = CPU_MASK_NONE; | |
97 | ||
98 | /* | |
99 | * Function Prototypes | |
100 | */ | |
101 | static int do_boot_cpu(int); | |
102 | static void smp_show_cpu_info(int cpu_id); | |
103 | static void smp_callin(void); | |
104 | static void smp_online(void); | |
105 | static void smp_store_cpu_info(int); | |
106 | static void smp_cpu_init(void); | |
107 | static void smp_tune_scheduling(void); | |
108 | static void send_IPI_mask(const cpumask_t *cpumask, int irq); | |
109 | static void init_ipi(void); | |
110 | ||
111 | /* | |
112 | * IPI Initialization interrupt definitions | |
113 | */ | |
114 | static void mn10300_ipi_disable(unsigned int irq); | |
115 | static void mn10300_ipi_enable(unsigned int irq); | |
3ba65467 TG |
116 | static void mn10300_ipi_chip_disable(struct irq_data *d); |
117 | static void mn10300_ipi_chip_enable(struct irq_data *d); | |
118 | static void mn10300_ipi_ack(struct irq_data *d); | |
119 | static void mn10300_ipi_nop(struct irq_data *d); | |
368dd5ac AT |
120 | |
121 | static struct irq_chip mn10300_ipi_type = { | |
122 | .name = "cpu_ipi", | |
3ba65467 TG |
123 | .irq_disable = mn10300_ipi_chip_disable, |
124 | .irq_enable = mn10300_ipi_chip_enable, | |
125 | .irq_ack = mn10300_ipi_ack, | |
126 | .irq_eoi = mn10300_ipi_nop | |
368dd5ac AT |
127 | }; |
128 | ||
129 | static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id); | |
130 | static irqreturn_t smp_call_function_interrupt(int irq, void *dev_id); | |
368dd5ac AT |
131 | |
132 | static struct irqaction reschedule_ipi = { | |
133 | .handler = smp_reschedule_interrupt, | |
7d361cb7 | 134 | .flags = IRQF_NOBALANCING, |
368dd5ac AT |
135 | .name = "smp reschedule IPI" |
136 | }; | |
137 | static struct irqaction call_function_ipi = { | |
138 | .handler = smp_call_function_interrupt, | |
7d361cb7 | 139 | .flags = IRQF_NOBALANCING, |
368dd5ac AT |
140 | .name = "smp call function IPI" |
141 | }; | |
730c1fad MS |
142 | |
143 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) | |
144 | static irqreturn_t smp_ipi_timer_interrupt(int irq, void *dev_id); | |
368dd5ac AT |
145 | static struct irqaction local_timer_ipi = { |
146 | .handler = smp_ipi_timer_interrupt, | |
322a126a | 147 | .flags = IRQF_NOBALANCING, |
368dd5ac AT |
148 | .name = "smp local timer IPI" |
149 | }; | |
730c1fad | 150 | #endif |
368dd5ac AT |
151 | |
152 | /** | |
153 | * init_ipi - Initialise the IPI mechanism | |
154 | */ | |
155 | static void init_ipi(void) | |
156 | { | |
157 | unsigned long flags; | |
158 | u16 tmp16; | |
159 | ||
160 | /* set up the reschedule IPI */ | |
f4c547eb TG |
161 | irq_set_chip_and_handler(RESCHEDULE_IPI, &mn10300_ipi_type, |
162 | handle_percpu_irq); | |
368dd5ac AT |
163 | setup_irq(RESCHEDULE_IPI, &reschedule_ipi); |
164 | set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV); | |
165 | mn10300_ipi_enable(RESCHEDULE_IPI); | |
166 | ||
167 | /* set up the call function IPI */ | |
f4c547eb TG |
168 | irq_set_chip_and_handler(CALL_FUNC_SINGLE_IPI, &mn10300_ipi_type, |
169 | handle_percpu_irq); | |
368dd5ac AT |
170 | setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi); |
171 | set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV); | |
172 | mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI); | |
173 | ||
174 | /* set up the local timer IPI */ | |
730c1fad MS |
175 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \ |
176 | defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) | |
f4c547eb TG |
177 | irq_set_chip_and_handler(LOCAL_TIMER_IPI, &mn10300_ipi_type, |
178 | handle_percpu_irq); | |
368dd5ac AT |
179 | setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi); |
180 | set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV); | |
181 | mn10300_ipi_enable(LOCAL_TIMER_IPI); | |
730c1fad | 182 | #endif |
368dd5ac AT |
183 | |
184 | #ifdef CONFIG_MN10300_CACHE_ENABLED | |
185 | /* set up the cache flush IPI */ | |
7d361cb7 | 186 | irq_set_chip(FLUSH_CACHE_IPI, &mn10300_ipi_type); |
368dd5ac AT |
187 | flags = arch_local_cli_save(); |
188 | __set_intr_stub(NUM2EXCEP_IRQ_LEVEL(FLUSH_CACHE_GxICR_LV), | |
189 | mn10300_low_ipi_handler); | |
190 | GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT; | |
191 | mn10300_ipi_enable(FLUSH_CACHE_IPI); | |
192 | arch_local_irq_restore(flags); | |
193 | #endif | |
194 | ||
195 | /* set up the NMI call function IPI */ | |
7d361cb7 | 196 | irq_set_chip(CALL_FUNCTION_NMI_IPI, &mn10300_ipi_type); |
368dd5ac AT |
197 | flags = arch_local_cli_save(); |
198 | GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; | |
199 | tmp16 = GxICR(CALL_FUNCTION_NMI_IPI); | |
200 | arch_local_irq_restore(flags); | |
201 | ||
202 | /* set up the SMP boot IPI */ | |
203 | flags = arch_local_cli_save(); | |
204 | __set_intr_stub(NUM2EXCEP_IRQ_LEVEL(SMP_BOOT_GxICR_LV), | |
205 | mn10300_low_ipi_handler); | |
206 | arch_local_irq_restore(flags); | |
7d361cb7 MS |
207 | |
208 | #ifdef CONFIG_KERNEL_DEBUGGER | |
209 | irq_set_chip(DEBUGGER_NMI_IPI, &mn10300_ipi_type); | |
210 | #endif | |
368dd5ac AT |
211 | } |
212 | ||
213 | /** | |
214 | * mn10300_ipi_shutdown - Shut down handling of an IPI | |
215 | * @irq: The IPI to be shut down. | |
216 | */ | |
217 | static void mn10300_ipi_shutdown(unsigned int irq) | |
218 | { | |
219 | unsigned long flags; | |
220 | u16 tmp; | |
221 | ||
222 | flags = arch_local_cli_save(); | |
223 | ||
224 | tmp = GxICR(irq); | |
225 | GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT; | |
226 | tmp = GxICR(irq); | |
227 | ||
228 | arch_local_irq_restore(flags); | |
229 | } | |
230 | ||
231 | /** | |
232 | * mn10300_ipi_enable - Enable an IPI | |
233 | * @irq: The IPI to be enabled. | |
234 | */ | |
235 | static void mn10300_ipi_enable(unsigned int irq) | |
236 | { | |
237 | unsigned long flags; | |
238 | u16 tmp; | |
239 | ||
240 | flags = arch_local_cli_save(); | |
241 | ||
242 | tmp = GxICR(irq); | |
243 | GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE; | |
244 | tmp = GxICR(irq); | |
245 | ||
246 | arch_local_irq_restore(flags); | |
247 | } | |
248 | ||
3ba65467 TG |
249 | static void mn10300_ipi_chip_enable(struct irq_data *d) |
250 | { | |
251 | mn10300_ipi_enable(d->irq); | |
252 | } | |
253 | ||
368dd5ac AT |
254 | /** |
255 | * mn10300_ipi_disable - Disable an IPI | |
256 | * @irq: The IPI to be disabled. | |
257 | */ | |
258 | static void mn10300_ipi_disable(unsigned int irq) | |
259 | { | |
260 | unsigned long flags; | |
261 | u16 tmp; | |
262 | ||
263 | flags = arch_local_cli_save(); | |
264 | ||
265 | tmp = GxICR(irq); | |
266 | GxICR(irq) = tmp & GxICR_LEVEL; | |
267 | tmp = GxICR(irq); | |
268 | ||
269 | arch_local_irq_restore(flags); | |
270 | } | |
271 | ||
3ba65467 TG |
272 | static void mn10300_ipi_chip_disable(struct irq_data *d) |
273 | { | |
274 | mn10300_ipi_disable(d->irq); | |
275 | } | |
276 | ||
277 | ||
368dd5ac AT |
278 | /** |
279 | * mn10300_ipi_ack - Acknowledge an IPI interrupt in the PIC | |
280 | * @irq: The IPI to be acknowledged. | |
281 | * | |
282 | * Clear the interrupt detection flag for the IPI on the appropriate interrupt | |
283 | * channel in the PIC. | |
284 | */ | |
3ba65467 | 285 | static void mn10300_ipi_ack(struct irq_data *d) |
368dd5ac | 286 | { |
3ba65467 | 287 | unsigned int irq = d->irq; |
368dd5ac AT |
288 | unsigned long flags; |
289 | u16 tmp; | |
290 | ||
291 | flags = arch_local_cli_save(); | |
292 | GxICR_u8(irq) = GxICR_DETECT; | |
293 | tmp = GxICR(irq); | |
294 | arch_local_irq_restore(flags); | |
295 | } | |
296 | ||
297 | /** | |
298 | * mn10300_ipi_nop - Dummy IPI action | |
299 | * @irq: The IPI to be acted upon. | |
300 | */ | |
3ba65467 | 301 | static void mn10300_ipi_nop(struct irq_data *d) |
368dd5ac AT |
302 | { |
303 | } | |
304 | ||
305 | /** | |
306 | * send_IPI_mask - Send IPIs to all CPUs in list | |
307 | * @cpumask: The list of CPUs to target. | |
308 | * @irq: The IPI request to be sent. | |
309 | * | |
310 | * Send the specified IPI to all the CPUs in the list, not waiting for them to | |
311 | * finish before returning. The caller is responsible for synchronisation if | |
312 | * that is needed. | |
313 | */ | |
314 | static void send_IPI_mask(const cpumask_t *cpumask, int irq) | |
315 | { | |
316 | int i; | |
317 | u16 tmp; | |
318 | ||
319 | for (i = 0; i < NR_CPUS; i++) { | |
8ea9716f | 320 | if (cpumask_test_cpu(i, cpumask)) { |
368dd5ac AT |
321 | /* send IPI */ |
322 | tmp = CROSS_GxICR(irq, i); | |
323 | CROSS_GxICR(irq, i) = | |
324 | tmp | GxICR_REQUEST | GxICR_DETECT; | |
325 | tmp = CROSS_GxICR(irq, i); /* flush write buffer */ | |
326 | } | |
327 | } | |
328 | } | |
329 | ||
330 | /** | |
331 | * send_IPI_self - Send an IPI to this CPU. | |
332 | * @irq: The IPI request to be sent. | |
333 | * | |
334 | * Send the specified IPI to the current CPU. | |
335 | */ | |
336 | void send_IPI_self(int irq) | |
337 | { | |
338 | send_IPI_mask(cpumask_of(smp_processor_id()), irq); | |
339 | } | |
340 | ||
341 | /** | |
342 | * send_IPI_allbutself - Send IPIs to all the other CPUs. | |
343 | * @irq: The IPI request to be sent. | |
344 | * | |
345 | * Send the specified IPI to all CPUs in the system barring the current one, | |
346 | * not waiting for them to finish before returning. The caller is responsible | |
347 | * for synchronisation if that is needed. | |
348 | */ | |
349 | void send_IPI_allbutself(int irq) | |
350 | { | |
351 | cpumask_t cpumask; | |
352 | ||
8ea9716f KM |
353 | cpumask_copy(&cpumask, cpu_online_mask); |
354 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
368dd5ac AT |
355 | send_IPI_mask(&cpumask, irq); |
356 | } | |
357 | ||
358 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) | |
359 | { | |
360 | BUG(); | |
361 | /*send_IPI_mask(mask, CALL_FUNCTION_IPI);*/ | |
362 | } | |
363 | ||
364 | void arch_send_call_function_single_ipi(int cpu) | |
365 | { | |
366 | send_IPI_mask(cpumask_of(cpu), CALL_FUNC_SINGLE_IPI); | |
367 | } | |
368 | ||
369 | /** | |
370 | * smp_send_reschedule - Send reschedule IPI to a CPU | |
371 | * @cpu: The CPU to target. | |
372 | */ | |
373 | void smp_send_reschedule(int cpu) | |
374 | { | |
375 | send_IPI_mask(cpumask_of(cpu), RESCHEDULE_IPI); | |
376 | } | |
377 | ||
378 | /** | |
379 | * smp_nmi_call_function - Send a call function NMI IPI to all CPUs | |
380 | * @func: The function to ask to be run. | |
381 | * @info: The context data to pass to that function. | |
382 | * @wait: If true, wait (atomically) until function is run on all CPUs. | |
383 | * | |
384 | * Send a non-maskable request to all CPUs in the system, requesting them to | |
385 | * run the specified function with the given context data, and, potentially, to | |
386 | * wait for completion of that function on all CPUs. | |
387 | * | |
388 | * Returns 0 if successful, -ETIMEDOUT if we were asked to wait, but hit the | |
389 | * timeout. | |
390 | */ | |
391 | int smp_nmi_call_function(smp_call_func_t func, void *info, int wait) | |
392 | { | |
393 | struct nmi_call_data_struct data; | |
394 | unsigned long flags; | |
395 | unsigned int cnt; | |
396 | int cpus, ret = 0; | |
397 | ||
398 | cpus = num_online_cpus() - 1; | |
399 | if (cpus < 1) | |
400 | return 0; | |
401 | ||
402 | data.func = func; | |
403 | data.info = info; | |
8ea9716f KM |
404 | cpumask_copy(&data.started, cpu_online_mask); |
405 | cpumask_clear_cpu(smp_processor_id(), &data.started); | |
368dd5ac AT |
406 | data.wait = wait; |
407 | if (wait) | |
408 | data.finished = data.started; | |
409 | ||
410 | spin_lock_irqsave(&smp_nmi_call_lock, flags); | |
411 | nmi_call_data = &data; | |
412 | smp_mb(); | |
413 | ||
414 | /* Send a message to all other CPUs and wait for them to respond */ | |
415 | send_IPI_allbutself(CALL_FUNCTION_NMI_IPI); | |
416 | ||
417 | /* Wait for response */ | |
418 | if (CALL_FUNCTION_NMI_IPI_TIMEOUT > 0) { | |
419 | for (cnt = 0; | |
420 | cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT && | |
8ea9716f | 421 | !cpumask_empty(&data.started); |
368dd5ac AT |
422 | cnt++) |
423 | mdelay(1); | |
424 | ||
425 | if (wait && cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT) { | |
426 | for (cnt = 0; | |
427 | cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT && | |
8ea9716f | 428 | !cpumask_empty(&data.finished); |
368dd5ac AT |
429 | cnt++) |
430 | mdelay(1); | |
431 | } | |
432 | ||
433 | if (cnt >= CALL_FUNCTION_NMI_IPI_TIMEOUT) | |
434 | ret = -ETIMEDOUT; | |
435 | ||
436 | } else { | |
437 | /* If timeout value is zero, wait until cpumask has been | |
438 | * cleared */ | |
8ea9716f | 439 | while (!cpumask_empty(&data.started)) |
368dd5ac AT |
440 | barrier(); |
441 | if (wait) | |
8ea9716f | 442 | while (!cpumask_empty(&data.finished)) |
368dd5ac AT |
443 | barrier(); |
444 | } | |
445 | ||
446 | spin_unlock_irqrestore(&smp_nmi_call_lock, flags); | |
447 | return ret; | |
448 | } | |
449 | ||
67ddb405 DH |
450 | /** |
451 | * smp_jump_to_debugger - Make other CPUs enter the debugger by sending an IPI | |
452 | * | |
453 | * Send a non-maskable request to all other CPUs in the system, instructing | |
454 | * them to jump into the debugger. The caller is responsible for checking that | |
455 | * the other CPUs responded to the instruction. | |
456 | * | |
457 | * The caller should make sure that this CPU's debugger IPI is disabled. | |
458 | */ | |
459 | void smp_jump_to_debugger(void) | |
460 | { | |
461 | if (num_online_cpus() > 1) | |
462 | /* Send a message to all other CPUs */ | |
463 | send_IPI_allbutself(DEBUGGER_NMI_IPI); | |
464 | } | |
465 | ||
368dd5ac AT |
466 | /** |
467 | * stop_this_cpu - Callback to stop a CPU. | |
468 | * @unused: Callback context (ignored). | |
469 | */ | |
470 | void stop_this_cpu(void *unused) | |
471 | { | |
472 | static volatile int stopflag; | |
473 | unsigned long flags; | |
474 | ||
475 | #ifdef CONFIG_GDBSTUB | |
476 | /* In case of single stepping smp_send_stop by other CPU, | |
477 | * clear procindebug to avoid deadlock. | |
478 | */ | |
479 | atomic_set(&procindebug[smp_processor_id()], 0); | |
480 | #endif /* CONFIG_GDBSTUB */ | |
481 | ||
482 | flags = arch_local_cli_save(); | |
8ea9716f | 483 | set_cpu_online(smp_processor_id(), false); |
368dd5ac AT |
484 | |
485 | while (!stopflag) | |
486 | cpu_relax(); | |
487 | ||
8ea9716f | 488 | set_cpu_online(smp_processor_id(), true); |
368dd5ac AT |
489 | arch_local_irq_restore(flags); |
490 | } | |
491 | ||
492 | /** | |
493 | * smp_send_stop - Send a stop request to all CPUs. | |
494 | */ | |
495 | void smp_send_stop(void) | |
496 | { | |
497 | smp_nmi_call_function(stop_this_cpu, NULL, 0); | |
498 | } | |
499 | ||
500 | /** | |
501 | * smp_reschedule_interrupt - Reschedule IPI handler | |
502 | * @irq: The interrupt number. | |
503 | * @dev_id: The device ID. | |
504 | * | |
368dd5ac AT |
505 | * Returns IRQ_HANDLED to indicate we handled the interrupt successfully. |
506 | */ | |
507 | static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id) | |
508 | { | |
184748cc | 509 | scheduler_ipi(); |
368dd5ac AT |
510 | return IRQ_HANDLED; |
511 | } | |
512 | ||
513 | /** | |
514 | * smp_call_function_interrupt - Call function IPI handler | |
515 | * @irq: The interrupt number. | |
516 | * @dev_id: The device ID. | |
517 | * | |
518 | * Returns IRQ_HANDLED to indicate we handled the interrupt successfully. | |
519 | */ | |
520 | static irqreturn_t smp_call_function_interrupt(int irq, void *dev_id) | |
521 | { | |
522 | /* generic_smp_call_function_interrupt(); */ | |
523 | generic_smp_call_function_single_interrupt(); | |
524 | return IRQ_HANDLED; | |
525 | } | |
526 | ||
527 | /** | |
528 | * smp_nmi_call_function_interrupt - Non-maskable call function IPI handler | |
529 | */ | |
530 | void smp_nmi_call_function_interrupt(void) | |
531 | { | |
532 | smp_call_func_t func = nmi_call_data->func; | |
533 | void *info = nmi_call_data->info; | |
534 | int wait = nmi_call_data->wait; | |
535 | ||
536 | /* Notify the initiating CPU that I've grabbed the data and am about to | |
537 | * execute the function | |
538 | */ | |
539 | smp_mb(); | |
8ea9716f | 540 | cpumask_clear_cpu(smp_processor_id(), &nmi_call_data->started); |
368dd5ac AT |
541 | (*func)(info); |
542 | ||
543 | if (wait) { | |
544 | smp_mb(); | |
8ea9716f KM |
545 | cpumask_clear_cpu(smp_processor_id(), |
546 | &nmi_call_data->finished); | |
368dd5ac AT |
547 | } |
548 | } | |
549 | ||
730c1fad MS |
550 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \ |
551 | defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) | |
368dd5ac AT |
552 | /** |
553 | * smp_ipi_timer_interrupt - Local timer IPI handler | |
554 | * @irq: The interrupt number. | |
555 | * @dev_id: The device ID. | |
556 | * | |
557 | * Returns IRQ_HANDLED to indicate we handled the interrupt successfully. | |
558 | */ | |
559 | static irqreturn_t smp_ipi_timer_interrupt(int irq, void *dev_id) | |
560 | { | |
561 | return local_timer_interrupt(); | |
562 | } | |
730c1fad | 563 | #endif |
368dd5ac AT |
564 | |
565 | void __init smp_init_cpus(void) | |
566 | { | |
567 | int i; | |
568 | for (i = 0; i < NR_CPUS; i++) { | |
569 | set_cpu_possible(i, true); | |
570 | set_cpu_present(i, true); | |
571 | } | |
572 | } | |
573 | ||
574 | /** | |
575 | * smp_cpu_init - Initialise AP in start_secondary. | |
576 | * | |
577 | * For this Application Processor, set up init_mm, initialise FPU and set | |
578 | * interrupt level 0-6 setting. | |
579 | */ | |
580 | static void __init smp_cpu_init(void) | |
581 | { | |
582 | unsigned long flags; | |
583 | int cpu_id = smp_processor_id(); | |
584 | u16 tmp16; | |
585 | ||
586 | if (test_and_set_bit(cpu_id, &cpu_initialized)) { | |
587 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu_id); | |
588 | for (;;) | |
589 | local_irq_enable(); | |
590 | } | |
591 | printk(KERN_INFO "Initializing CPU#%d\n", cpu_id); | |
592 | ||
f1f10076 | 593 | mmgrab(&init_mm); |
368dd5ac AT |
594 | current->active_mm = &init_mm; |
595 | BUG_ON(current->mm); | |
596 | ||
597 | enter_lazy_tlb(&init_mm, current); | |
598 | ||
599 | /* Force FPU initialization */ | |
600 | clear_using_fpu(current); | |
601 | ||
602 | GxICR(CALL_FUNC_SINGLE_IPI) = CALL_FUNCTION_GxICR_LV | GxICR_DETECT; | |
603 | mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI); | |
604 | ||
605 | GxICR(LOCAL_TIMER_IPI) = LOCAL_TIMER_GxICR_LV | GxICR_DETECT; | |
606 | mn10300_ipi_enable(LOCAL_TIMER_IPI); | |
607 | ||
608 | GxICR(RESCHEDULE_IPI) = RESCHEDULE_GxICR_LV | GxICR_DETECT; | |
609 | mn10300_ipi_enable(RESCHEDULE_IPI); | |
610 | ||
611 | #ifdef CONFIG_MN10300_CACHE_ENABLED | |
612 | GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT; | |
613 | mn10300_ipi_enable(FLUSH_CACHE_IPI); | |
614 | #endif | |
615 | ||
616 | mn10300_ipi_shutdown(SMP_BOOT_IRQ); | |
617 | ||
618 | /* Set up the non-maskable call function IPI */ | |
619 | flags = arch_local_cli_save(); | |
620 | GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; | |
621 | tmp16 = GxICR(CALL_FUNCTION_NMI_IPI); | |
622 | arch_local_irq_restore(flags); | |
623 | } | |
624 | ||
625 | /** | |
626 | * smp_prepare_cpu_init - Initialise CPU in startup_secondary | |
627 | * | |
67ddb405 | 628 | * Set interrupt level 0-6 setting and init ICR of the kernel debugger. |
368dd5ac AT |
629 | */ |
630 | void smp_prepare_cpu_init(void) | |
631 | { | |
632 | int loop; | |
633 | ||
634 | /* Set the interrupt vector registers */ | |
635 | IVAR0 = EXCEP_IRQ_LEVEL0; | |
636 | IVAR1 = EXCEP_IRQ_LEVEL1; | |
637 | IVAR2 = EXCEP_IRQ_LEVEL2; | |
638 | IVAR3 = EXCEP_IRQ_LEVEL3; | |
639 | IVAR4 = EXCEP_IRQ_LEVEL4; | |
640 | IVAR5 = EXCEP_IRQ_LEVEL5; | |
641 | IVAR6 = EXCEP_IRQ_LEVEL6; | |
642 | ||
643 | /* Disable all interrupts and set to priority 6 (lowest) */ | |
644 | for (loop = 0; loop < GxICR_NUM_IRQS; loop++) | |
645 | GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; | |
646 | ||
67ddb405 DH |
647 | #ifdef CONFIG_KERNEL_DEBUGGER |
648 | /* initialise the kernel debugger interrupt */ | |
368dd5ac AT |
649 | do { |
650 | unsigned long flags; | |
651 | u16 tmp16; | |
652 | ||
653 | flags = arch_local_cli_save(); | |
67ddb405 DH |
654 | GxICR(DEBUGGER_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; |
655 | tmp16 = GxICR(DEBUGGER_NMI_IPI); | |
368dd5ac AT |
656 | arch_local_irq_restore(flags); |
657 | } while (0); | |
658 | #endif | |
659 | } | |
660 | ||
661 | /** | |
662 | * start_secondary - Activate a secondary CPU (AP) | |
663 | * @unused: Thread parameter (ignored). | |
664 | */ | |
665 | int __init start_secondary(void *unused) | |
666 | { | |
667 | smp_cpu_init(); | |
368dd5ac | 668 | smp_callin(); |
8ea9716f | 669 | while (!cpumask_test_cpu(smp_processor_id(), &smp_commenced_mask)) |
368dd5ac AT |
670 | cpu_relax(); |
671 | ||
672 | local_flush_tlb(); | |
673 | preempt_disable(); | |
674 | smp_online(); | |
675 | ||
730c1fad MS |
676 | #ifdef CONFIG_GENERIC_CLOCKEVENTS |
677 | init_clockevents(); | |
678 | #endif | |
fc6d73d6 | 679 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
368dd5ac AT |
680 | return 0; |
681 | } | |
682 | ||
683 | /** | |
684 | * smp_prepare_cpus - Boot up secondary CPUs (APs) | |
685 | * @max_cpus: Maximum number of CPUs to boot. | |
686 | * | |
687 | * Call do_boot_cpu, and boot up APs. | |
688 | */ | |
689 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
690 | { | |
691 | int phy_id; | |
692 | ||
693 | /* Setup boot CPU information */ | |
694 | smp_store_cpu_info(0); | |
695 | smp_tune_scheduling(); | |
696 | ||
697 | init_ipi(); | |
698 | ||
699 | /* If SMP should be disabled, then finish */ | |
700 | if (max_cpus == 0) { | |
701 | printk(KERN_INFO "SMP mode deactivated.\n"); | |
702 | goto smp_done; | |
703 | } | |
704 | ||
705 | /* Boot secondary CPUs (for which phy_id > 0) */ | |
706 | for (phy_id = 0; phy_id < NR_CPUS; phy_id++) { | |
707 | /* Don't boot primary CPU */ | |
708 | if (max_cpus <= cpucount + 1) | |
709 | continue; | |
710 | if (phy_id != 0) | |
711 | do_boot_cpu(phy_id); | |
712 | set_cpu_possible(phy_id, true); | |
713 | smp_show_cpu_info(phy_id); | |
714 | } | |
715 | ||
716 | smp_done: | |
717 | Dprintk("Boot done.\n"); | |
718 | } | |
719 | ||
720 | /** | |
721 | * smp_store_cpu_info - Save a CPU's information | |
722 | * @cpu: The CPU to save for. | |
723 | * | |
724 | * Save boot_cpu_data and jiffy for the specified CPU. | |
725 | */ | |
726 | static void __init smp_store_cpu_info(int cpu) | |
727 | { | |
728 | struct mn10300_cpuinfo *ci = &cpu_data[cpu]; | |
729 | ||
730 | *ci = boot_cpu_data; | |
731 | ci->loops_per_jiffy = loops_per_jiffy; | |
732 | ci->type = CPUREV; | |
733 | } | |
734 | ||
735 | /** | |
736 | * smp_tune_scheduling - Set time slice value | |
737 | * | |
738 | * Nothing to do here. | |
739 | */ | |
740 | static void __init smp_tune_scheduling(void) | |
741 | { | |
742 | } | |
743 | ||
744 | /** | |
745 | * do_boot_cpu: Boot up one CPU | |
746 | * @phy_id: Physical ID of CPU to boot. | |
747 | * | |
748 | * Send an IPI to a secondary CPU to boot it. Returns 0 on success, 1 | |
749 | * otherwise. | |
750 | */ | |
751 | static int __init do_boot_cpu(int phy_id) | |
752 | { | |
753 | struct task_struct *idle; | |
754 | unsigned long send_status, callin_status; | |
755 | int timeout, cpu_id; | |
756 | ||
757 | send_status = GxICR_REQUEST; | |
758 | callin_status = 0; | |
759 | timeout = 0; | |
760 | cpu_id = phy_id; | |
761 | ||
762 | cpucount++; | |
763 | ||
764 | /* Create idle thread for this CPU */ | |
765 | idle = fork_idle(cpu_id); | |
766 | if (IS_ERR(idle)) | |
767 | panic("Failed fork for CPU#%d.", cpu_id); | |
768 | ||
769 | idle->thread.pc = (unsigned long)start_secondary; | |
770 | ||
771 | printk(KERN_NOTICE "Booting CPU#%d\n", cpu_id); | |
772 | start_stack[cpu_id - 1] = idle->thread.sp; | |
773 | ||
774 | task_thread_info(idle)->cpu = cpu_id; | |
775 | ||
776 | /* Send boot IPI to AP */ | |
777 | send_IPI_mask(cpumask_of(phy_id), SMP_BOOT_IRQ); | |
778 | ||
779 | Dprintk("Waiting for send to finish...\n"); | |
780 | ||
781 | /* Wait for AP's IPI receive in 100[ms] */ | |
782 | do { | |
783 | udelay(1000); | |
784 | send_status = | |
785 | CROSS_GxICR(SMP_BOOT_IRQ, phy_id) & GxICR_REQUEST; | |
786 | } while (send_status == GxICR_REQUEST && timeout++ < 100); | |
787 | ||
788 | Dprintk("Waiting for cpu_callin_map.\n"); | |
789 | ||
790 | if (send_status == 0) { | |
791 | /* Allow AP to start initializing */ | |
8ea9716f | 792 | cpumask_set_cpu(cpu_id, &cpu_callout_map); |
368dd5ac AT |
793 | |
794 | /* Wait for setting cpu_callin_map */ | |
795 | timeout = 0; | |
796 | do { | |
797 | udelay(1000); | |
8ea9716f KM |
798 | callin_status = cpumask_test_cpu(cpu_id, |
799 | &cpu_callin_map); | |
368dd5ac AT |
800 | } while (callin_status == 0 && timeout++ < 5000); |
801 | ||
802 | if (callin_status == 0) | |
803 | Dprintk("Not responding.\n"); | |
804 | } else { | |
805 | printk(KERN_WARNING "IPI not delivered.\n"); | |
806 | } | |
807 | ||
808 | if (send_status == GxICR_REQUEST || callin_status == 0) { | |
8ea9716f KM |
809 | cpumask_clear_cpu(cpu_id, &cpu_callout_map); |
810 | cpumask_clear_cpu(cpu_id, &cpu_callin_map); | |
811 | cpumask_clear_cpu(cpu_id, &cpu_initialized); | |
368dd5ac AT |
812 | cpucount--; |
813 | return 1; | |
814 | } | |
815 | return 0; | |
816 | } | |
817 | ||
818 | /** | |
819 | * smp_show_cpu_info - Show SMP CPU information | |
820 | * @cpu: The CPU of interest. | |
821 | */ | |
822 | static void __init smp_show_cpu_info(int cpu) | |
823 | { | |
824 | struct mn10300_cpuinfo *ci = &cpu_data[cpu]; | |
825 | ||
826 | printk(KERN_INFO | |
827 | "CPU#%d : ioclk speed: %lu.%02luMHz : bogomips : %lu.%02lu\n", | |
828 | cpu, | |
829 | MN10300_IOCLK / 1000000, | |
830 | (MN10300_IOCLK / 10000) % 100, | |
831 | ci->loops_per_jiffy / (500000 / HZ), | |
832 | (ci->loops_per_jiffy / (5000 / HZ)) % 100); | |
833 | } | |
834 | ||
835 | /** | |
836 | * smp_callin - Set cpu_callin_map of the current CPU ID | |
837 | */ | |
838 | static void __init smp_callin(void) | |
839 | { | |
840 | unsigned long timeout; | |
841 | int cpu; | |
842 | ||
843 | cpu = smp_processor_id(); | |
844 | timeout = jiffies + (2 * HZ); | |
845 | ||
8ea9716f | 846 | if (cpumask_test_cpu(cpu, &cpu_callin_map)) { |
368dd5ac AT |
847 | printk(KERN_ERR "CPU#%d already present.\n", cpu); |
848 | BUG(); | |
849 | } | |
850 | Dprintk("CPU#%d waiting for CALLOUT\n", cpu); | |
851 | ||
852 | /* Wait for AP startup 2s total */ | |
853 | while (time_before(jiffies, timeout)) { | |
8ea9716f | 854 | if (cpumask_test_cpu(cpu, &cpu_callout_map)) |
368dd5ac AT |
855 | break; |
856 | cpu_relax(); | |
857 | } | |
858 | ||
859 | if (!time_before(jiffies, timeout)) { | |
860 | printk(KERN_ERR | |
861 | "BUG: CPU#%d started up but did not get a callout!\n", | |
862 | cpu); | |
863 | BUG(); | |
864 | } | |
865 | ||
866 | #ifdef CONFIG_CALIBRATE_DELAY | |
867 | calibrate_delay(); /* Get our bogomips */ | |
868 | #endif | |
869 | ||
870 | /* Save our processor parameters */ | |
871 | smp_store_cpu_info(cpu); | |
872 | ||
873 | /* Allow the boot processor to continue */ | |
8ea9716f | 874 | cpumask_set_cpu(cpu, &cpu_callin_map); |
368dd5ac AT |
875 | } |
876 | ||
877 | /** | |
8ea9716f | 878 | * smp_online - Set cpu_online_mask |
368dd5ac AT |
879 | */ |
880 | static void __init smp_online(void) | |
881 | { | |
882 | int cpu; | |
883 | ||
884 | cpu = smp_processor_id(); | |
885 | ||
568b4455 | 886 | notify_cpu_starting(cpu); |
368dd5ac | 887 | |
8ea9716f | 888 | set_cpu_online(cpu, true); |
568b4455 SB |
889 | |
890 | local_irq_enable(); | |
368dd5ac AT |
891 | } |
892 | ||
893 | /** | |
894 | * smp_cpus_done - | |
895 | * @max_cpus: Maximum CPU count. | |
896 | * | |
897 | * Do nothing. | |
898 | */ | |
899 | void __init smp_cpus_done(unsigned int max_cpus) | |
900 | { | |
901 | } | |
902 | ||
903 | /* | |
904 | * smp_prepare_boot_cpu - Set up stuff for the boot processor. | |
905 | * | |
8ea9716f | 906 | * Set up the cpu_online_mask, cpu_callout_map and cpu_callin_map of the boot |
368dd5ac AT |
907 | * processor (CPU 0). |
908 | */ | |
b881bc46 | 909 | void smp_prepare_boot_cpu(void) |
368dd5ac | 910 | { |
8ea9716f KM |
911 | cpumask_set_cpu(0, &cpu_callout_map); |
912 | cpumask_set_cpu(0, &cpu_callin_map); | |
368dd5ac AT |
913 | current_thread_info()->cpu = 0; |
914 | } | |
915 | ||
916 | /* | |
917 | * initialize_secondary - Initialise a secondary CPU (Application Processor). | |
918 | * | |
919 | * Set SP register and jump to thread's PC address. | |
920 | */ | |
921 | void initialize_secondary(void) | |
922 | { | |
923 | asm volatile ( | |
924 | "mov %0,sp \n" | |
925 | "jmp (%1) \n" | |
926 | : | |
927 | : "a"(current->thread.sp), "a"(current->thread.pc)); | |
928 | } | |
929 | ||
930 | /** | |
931 | * __cpu_up - Set smp_commenced_mask for the nominated CPU | |
932 | * @cpu: The target CPU. | |
933 | */ | |
b881bc46 | 934 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
368dd5ac AT |
935 | { |
936 | int timeout; | |
937 | ||
938 | #ifdef CONFIG_HOTPLUG_CPU | |
368dd5ac AT |
939 | if (sleep_mode[cpu]) |
940 | run_wakeup_cpu(cpu); | |
941 | #endif /* CONFIG_HOTPLUG_CPU */ | |
942 | ||
8ea9716f | 943 | cpumask_set_cpu(cpu, &smp_commenced_mask); |
368dd5ac AT |
944 | |
945 | /* Wait 5s total for a response */ | |
946 | for (timeout = 0 ; timeout < 5000 ; timeout++) { | |
8ea9716f | 947 | if (cpu_online(cpu)) |
368dd5ac AT |
948 | break; |
949 | udelay(1000); | |
950 | } | |
951 | ||
8ea9716f | 952 | BUG_ON(!cpu_online(cpu)); |
368dd5ac AT |
953 | return 0; |
954 | } | |
955 | ||
956 | /** | |
957 | * setup_profiling_timer - Set up the profiling timer | |
958 | * @multiplier - The frequency multiplier to use | |
959 | * | |
960 | * The frequency of the profiling timer can be changed by writing a multiplier | |
961 | * value into /proc/profile. | |
962 | */ | |
963 | int setup_profiling_timer(unsigned int multiplier) | |
964 | { | |
965 | return -EINVAL; | |
966 | } | |
967 | ||
968 | /* | |
969 | * CPU hotplug routines | |
970 | */ | |
971 | #ifdef CONFIG_HOTPLUG_CPU | |
972 | ||
973 | static DEFINE_PER_CPU(struct cpu, cpu_devices); | |
974 | ||
975 | static int __init topology_init(void) | |
976 | { | |
977 | int cpu, ret; | |
978 | ||
979 | for_each_cpu(cpu) { | |
980 | ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu, NULL); | |
981 | if (ret) | |
982 | printk(KERN_WARNING | |
983 | "topology_init: register_cpu %d failed (%d)\n", | |
984 | cpu, ret); | |
985 | } | |
986 | return 0; | |
987 | } | |
988 | ||
989 | subsys_initcall(topology_init); | |
990 | ||
991 | int __cpu_disable(void) | |
992 | { | |
993 | int cpu = smp_processor_id(); | |
994 | if (cpu == 0) | |
995 | return -EBUSY; | |
996 | ||
997 | migrate_irqs(); | |
8ea9716f | 998 | cpumask_clear_cpu(cpu, &mm_cpumask(current->active_mm)); |
368dd5ac AT |
999 | return 0; |
1000 | } | |
1001 | ||
1002 | void __cpu_die(unsigned int cpu) | |
1003 | { | |
1004 | run_sleep_cpu(cpu); | |
368dd5ac AT |
1005 | } |
1006 | ||
1007 | #ifdef CONFIG_MN10300_CACHE_ENABLED | |
1008 | static inline void hotplug_cpu_disable_cache(void) | |
1009 | { | |
1010 | int tmp; | |
1011 | asm volatile( | |
1012 | " movhu (%1),%0 \n" | |
1013 | " and %2,%0 \n" | |
1014 | " movhu %0,(%1) \n" | |
1015 | "1: movhu (%1),%0 \n" | |
1016 | " btst %3,%0 \n" | |
1017 | " bne 1b \n" | |
1018 | : "=&r"(tmp) | |
1019 | : "a"(&CHCTR), | |
1020 | "i"(~(CHCTR_ICEN | CHCTR_DCEN)), | |
1021 | "i"(CHCTR_ICBUSY | CHCTR_DCBUSY) | |
1022 | : "memory", "cc"); | |
1023 | } | |
1024 | ||
1025 | static inline void hotplug_cpu_enable_cache(void) | |
1026 | { | |
1027 | int tmp; | |
1028 | asm volatile( | |
1029 | "movhu (%1),%0 \n" | |
1030 | "or %2,%0 \n" | |
1031 | "movhu %0,(%1) \n" | |
1032 | : "=&r"(tmp) | |
1033 | : "a"(&CHCTR), | |
1034 | "i"(CHCTR_ICEN | CHCTR_DCEN) | |
1035 | : "memory", "cc"); | |
1036 | } | |
1037 | ||
1038 | static inline void hotplug_cpu_invalidate_cache(void) | |
1039 | { | |
1040 | int tmp; | |
1041 | asm volatile ( | |
1042 | "movhu (%1),%0 \n" | |
1043 | "or %2,%0 \n" | |
1044 | "movhu %0,(%1) \n" | |
1045 | : "=&r"(tmp) | |
1046 | : "a"(&CHCTR), | |
1047 | "i"(CHCTR_ICINV | CHCTR_DCINV) | |
1048 | : "cc"); | |
1049 | } | |
1050 | ||
1051 | #else /* CONFIG_MN10300_CACHE_ENABLED */ | |
1052 | #define hotplug_cpu_disable_cache() do {} while (0) | |
1053 | #define hotplug_cpu_enable_cache() do {} while (0) | |
1054 | #define hotplug_cpu_invalidate_cache() do {} while (0) | |
1055 | #endif /* CONFIG_MN10300_CACHE_ENABLED */ | |
1056 | ||
1057 | /** | |
1058 | * hotplug_cpu_nmi_call_function - Call a function on other CPUs for hotplug | |
1059 | * @cpumask: List of target CPUs. | |
1060 | * @func: The function to call on those CPUs. | |
1061 | * @info: The context data for the function to be called. | |
1062 | * @wait: Whether to wait for the calls to complete. | |
1063 | * | |
1064 | * Non-maskably call a function on another CPU for hotplug purposes. | |
1065 | * | |
1066 | * This function must be called with maskable interrupts disabled. | |
1067 | */ | |
1068 | static int hotplug_cpu_nmi_call_function(cpumask_t cpumask, | |
1069 | smp_call_func_t func, void *info, | |
1070 | int wait) | |
1071 | { | |
1072 | /* | |
1073 | * The address and the size of nmi_call_func_mask_data | |
1074 | * need to be aligned on L1_CACHE_BYTES. | |
1075 | */ | |
1076 | static struct nmi_call_data_struct nmi_call_func_mask_data | |
1077 | __cacheline_aligned; | |
1078 | unsigned long start, end; | |
1079 | ||
1080 | start = (unsigned long)&nmi_call_func_mask_data; | |
1081 | end = start + sizeof(struct nmi_call_data_struct); | |
1082 | ||
1083 | nmi_call_func_mask_data.func = func; | |
1084 | nmi_call_func_mask_data.info = info; | |
1085 | nmi_call_func_mask_data.started = cpumask; | |
1086 | nmi_call_func_mask_data.wait = wait; | |
1087 | if (wait) | |
1088 | nmi_call_func_mask_data.finished = cpumask; | |
1089 | ||
1090 | spin_lock(&smp_nmi_call_lock); | |
1091 | nmi_call_data = &nmi_call_func_mask_data; | |
1092 | mn10300_local_dcache_flush_range(start, end); | |
1093 | smp_wmb(); | |
1094 | ||
1095 | send_IPI_mask(cpumask, CALL_FUNCTION_NMI_IPI); | |
1096 | ||
1097 | do { | |
1098 | mn10300_local_dcache_inv_range(start, end); | |
1099 | barrier(); | |
8ea9716f | 1100 | } while (!cpumask_empty(&nmi_call_func_mask_data.started)); |
368dd5ac AT |
1101 | |
1102 | if (wait) { | |
1103 | do { | |
1104 | mn10300_local_dcache_inv_range(start, end); | |
1105 | barrier(); | |
8ea9716f | 1106 | } while (!cpumask_empty(&nmi_call_func_mask_data.finished)); |
368dd5ac AT |
1107 | } |
1108 | ||
1109 | spin_unlock(&smp_nmi_call_lock); | |
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | static void restart_wakeup_cpu(void) | |
1114 | { | |
1115 | unsigned int cpu = smp_processor_id(); | |
1116 | ||
8ea9716f | 1117 | cpumask_set_cpu(cpu, &cpu_callin_map); |
368dd5ac | 1118 | local_flush_tlb(); |
8ea9716f | 1119 | set_cpu_online(cpu, true); |
368dd5ac AT |
1120 | smp_wmb(); |
1121 | } | |
1122 | ||
1123 | static void prepare_sleep_cpu(void *unused) | |
1124 | { | |
1125 | sleep_mode[smp_processor_id()] = 1; | |
1126 | smp_mb(); | |
1127 | mn10300_local_dcache_flush_inv(); | |
1128 | hotplug_cpu_disable_cache(); | |
1129 | hotplug_cpu_invalidate_cache(); | |
1130 | } | |
1131 | ||
1132 | /* when this function called, IE=0, NMID=0. */ | |
1133 | static void sleep_cpu(void *unused) | |
1134 | { | |
1135 | unsigned int cpu_id = smp_processor_id(); | |
1136 | /* | |
1137 | * CALL_FUNCTION_NMI_IPI for wakeup_cpu() shall not be requested, | |
1138 | * before this cpu goes in SLEEP mode. | |
1139 | */ | |
1140 | do { | |
1141 | smp_mb(); | |
1142 | __sleep_cpu(); | |
1143 | } while (sleep_mode[cpu_id]); | |
1144 | restart_wakeup_cpu(); | |
1145 | } | |
1146 | ||
1147 | static void run_sleep_cpu(unsigned int cpu) | |
1148 | { | |
1149 | unsigned long flags; | |
8ea9716f | 1150 | cpumask_t cpumask; |
368dd5ac | 1151 | |
8ea9716f | 1152 | cpumask_copy(&cpumask, &cpumask_of(cpu)); |
368dd5ac AT |
1153 | flags = arch_local_cli_save(); |
1154 | hotplug_cpu_nmi_call_function(cpumask, prepare_sleep_cpu, NULL, 1); | |
1155 | hotplug_cpu_nmi_call_function(cpumask, sleep_cpu, NULL, 0); | |
1156 | udelay(1); /* delay for the cpu to sleep. */ | |
1157 | arch_local_irq_restore(flags); | |
1158 | } | |
1159 | ||
1160 | static void wakeup_cpu(void) | |
1161 | { | |
1162 | hotplug_cpu_invalidate_cache(); | |
1163 | hotplug_cpu_enable_cache(); | |
1164 | smp_mb(); | |
1165 | sleep_mode[smp_processor_id()] = 0; | |
1166 | } | |
1167 | ||
1168 | static void run_wakeup_cpu(unsigned int cpu) | |
1169 | { | |
1170 | unsigned long flags; | |
1171 | ||
1172 | flags = arch_local_cli_save(); | |
1173 | #if NR_CPUS == 2 | |
1174 | mn10300_local_dcache_flush_inv(); | |
1175 | #else | |
1176 | /* | |
1177 | * Before waking up the cpu, | |
1178 | * all online cpus should stop and flush D-Cache for global data. | |
1179 | */ | |
1180 | #error not support NR_CPUS > 2, when CONFIG_HOTPLUG_CPU=y. | |
1181 | #endif | |
1182 | hotplug_cpu_nmi_call_function(cpumask_of(cpu), wakeup_cpu, NULL, 1); | |
1183 | arch_local_irq_restore(flags); | |
1184 | } | |
1185 | ||
1186 | #endif /* CONFIG_HOTPLUG_CPU */ |