]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PARISC TLB and cache flushing support | |
3 | * Copyright (C) 2000-2001 Hewlett-Packard (John Marvin) | |
4 | * Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org) | |
5 | * Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2, or (at your option) | |
10 | * any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | /* | |
23 | * NOTE: fdc,fic, and pdc instructions that use base register modification | |
24 | * should only use index and base registers that are not shadowed, | |
25 | * so that the fast path emulation in the non access miss handler | |
26 | * can be used. | |
27 | */ | |
28 | ||
413059f2 | 29 | #ifdef CONFIG_64BIT |
1da177e4 LT |
30 | .level 2.0w |
31 | #else | |
1da177e4 LT |
32 | .level 2.0 |
33 | #endif | |
34 | ||
1da177e4 | 35 | #include <asm/psw.h> |
896a3756 | 36 | #include <asm/assembly.h> |
1da177e4 LT |
37 | #include <asm/pgtable.h> |
38 | #include <asm/cache.h> | |
8e9e9844 | 39 | #include <linux/linkage.h> |
1da177e4 | 40 | |
dfcf753b | 41 | .text |
1da177e4 LT |
42 | .align 128 |
43 | ||
f39cce65 | 44 | ENTRY_CFI(flush_tlb_all_local) |
1da177e4 LT |
45 | .proc |
46 | .callinfo NO_CALLS | |
47 | .entry | |
48 | ||
49 | /* | |
50 | * The pitlbe and pdtlbe instructions should only be used to | |
51 | * flush the entire tlb. Also, there needs to be no intervening | |
52 | * tlb operations, e.g. tlb misses, so the operation needs | |
53 | * to happen in real mode with all interruptions disabled. | |
54 | */ | |
55 | ||
896a3756 | 56 | /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */ |
2fd83038 | 57 | rsm PSW_SM_I, %r19 /* save I-bit state */ |
896a3756 | 58 | load32 PA(1f), %r1 |
1da177e4 LT |
59 | nop |
60 | nop | |
61 | nop | |
62 | nop | |
63 | nop | |
896a3756 GG |
64 | |
65 | rsm PSW_SM_Q, %r0 /* prep to load iia queue */ | |
1da177e4 LT |
66 | mtctl %r0, %cr17 /* Clear IIASQ tail */ |
67 | mtctl %r0, %cr17 /* Clear IIASQ head */ | |
1da177e4 LT |
68 | mtctl %r1, %cr18 /* IIAOQ head */ |
69 | ldo 4(%r1), %r1 | |
70 | mtctl %r1, %cr18 /* IIAOQ tail */ | |
896a3756 GG |
71 | load32 REAL_MODE_PSW, %r1 |
72 | mtctl %r1, %ipsw | |
1da177e4 LT |
73 | rfi |
74 | nop | |
75 | ||
2fd83038 | 76 | 1: load32 PA(cache_info), %r1 |
1da177e4 LT |
77 | |
78 | /* Flush Instruction Tlb */ | |
79 | ||
80 | LDREG ITLB_SID_BASE(%r1), %r20 | |
81 | LDREG ITLB_SID_STRIDE(%r1), %r21 | |
82 | LDREG ITLB_SID_COUNT(%r1), %r22 | |
83 | LDREG ITLB_OFF_BASE(%r1), %arg0 | |
84 | LDREG ITLB_OFF_STRIDE(%r1), %arg1 | |
85 | LDREG ITLB_OFF_COUNT(%r1), %arg2 | |
86 | LDREG ITLB_LOOP(%r1), %arg3 | |
87 | ||
872f6deb | 88 | addib,COND(=) -1, %arg3, fitoneloop /* Preadjust and test */ |
1da177e4 LT |
89 | movb,<,n %arg3, %r31, fitdone /* If loop < 0, skip */ |
90 | copy %arg0, %r28 /* Init base addr */ | |
91 | ||
92 | fitmanyloop: /* Loop if LOOP >= 2 */ | |
93 | mtsp %r20, %sr1 | |
94 | add %r21, %r20, %r20 /* increment space */ | |
95 | copy %arg2, %r29 /* Init middle loop count */ | |
96 | ||
97 | fitmanymiddle: /* Loop if LOOP >= 2 */ | |
872f6deb | 98 | addib,COND(>) -1, %r31, fitmanymiddle /* Adjusted inner loop decr */ |
5035b230 | 99 | pitlbe %r0(%sr1, %r28) |
1da177e4 | 100 | pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */ |
872f6deb | 101 | addib,COND(>) -1, %r29, fitmanymiddle /* Middle loop decr */ |
1da177e4 LT |
102 | copy %arg3, %r31 /* Re-init inner loop count */ |
103 | ||
104 | movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */ | |
872f6deb | 105 | addib,COND(<=),n -1, %r22, fitdone /* Outer loop count decr */ |
1da177e4 LT |
106 | |
107 | fitoneloop: /* Loop if LOOP = 1 */ | |
108 | mtsp %r20, %sr1 | |
109 | copy %arg0, %r28 /* init base addr */ | |
110 | copy %arg2, %r29 /* init middle loop count */ | |
111 | ||
112 | fitonemiddle: /* Loop if LOOP = 1 */ | |
872f6deb | 113 | addib,COND(>) -1, %r29, fitonemiddle /* Middle loop count decr */ |
1da177e4 LT |
114 | pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */ |
115 | ||
872f6deb | 116 | addib,COND(>) -1, %r22, fitoneloop /* Outer loop count decr */ |
1da177e4 LT |
117 | add %r21, %r20, %r20 /* increment space */ |
118 | ||
119 | fitdone: | |
120 | ||
121 | /* Flush Data Tlb */ | |
122 | ||
123 | LDREG DTLB_SID_BASE(%r1), %r20 | |
124 | LDREG DTLB_SID_STRIDE(%r1), %r21 | |
125 | LDREG DTLB_SID_COUNT(%r1), %r22 | |
126 | LDREG DTLB_OFF_BASE(%r1), %arg0 | |
127 | LDREG DTLB_OFF_STRIDE(%r1), %arg1 | |
128 | LDREG DTLB_OFF_COUNT(%r1), %arg2 | |
129 | LDREG DTLB_LOOP(%r1), %arg3 | |
130 | ||
872f6deb | 131 | addib,COND(=) -1, %arg3, fdtoneloop /* Preadjust and test */ |
1da177e4 LT |
132 | movb,<,n %arg3, %r31, fdtdone /* If loop < 0, skip */ |
133 | copy %arg0, %r28 /* Init base addr */ | |
134 | ||
135 | fdtmanyloop: /* Loop if LOOP >= 2 */ | |
136 | mtsp %r20, %sr1 | |
137 | add %r21, %r20, %r20 /* increment space */ | |
138 | copy %arg2, %r29 /* Init middle loop count */ | |
139 | ||
140 | fdtmanymiddle: /* Loop if LOOP >= 2 */ | |
872f6deb | 141 | addib,COND(>) -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */ |
5035b230 | 142 | pdtlbe %r0(%sr1, %r28) |
1da177e4 | 143 | pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */ |
872f6deb | 144 | addib,COND(>) -1, %r29, fdtmanymiddle /* Middle loop decr */ |
1da177e4 LT |
145 | copy %arg3, %r31 /* Re-init inner loop count */ |
146 | ||
147 | movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */ | |
872f6deb | 148 | addib,COND(<=),n -1, %r22,fdtdone /* Outer loop count decr */ |
1da177e4 LT |
149 | |
150 | fdtoneloop: /* Loop if LOOP = 1 */ | |
151 | mtsp %r20, %sr1 | |
152 | copy %arg0, %r28 /* init base addr */ | |
153 | copy %arg2, %r29 /* init middle loop count */ | |
154 | ||
155 | fdtonemiddle: /* Loop if LOOP = 1 */ | |
872f6deb | 156 | addib,COND(>) -1, %r29, fdtonemiddle /* Middle loop count decr */ |
1da177e4 LT |
157 | pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */ |
158 | ||
872f6deb | 159 | addib,COND(>) -1, %r22, fdtoneloop /* Outer loop count decr */ |
1da177e4 LT |
160 | add %r21, %r20, %r20 /* increment space */ |
161 | ||
1da177e4 | 162 | |
896a3756 GG |
163 | fdtdone: |
164 | /* | |
165 | * Switch back to virtual mode | |
166 | */ | |
167 | /* pcxt_ssm_bug */ | |
168 | rsm PSW_SM_I, %r0 | |
169 | load32 2f, %r1 | |
170 | nop | |
171 | nop | |
172 | nop | |
173 | nop | |
174 | nop | |
1da177e4 | 175 | |
896a3756 | 176 | rsm PSW_SM_Q, %r0 /* prep to load iia queue */ |
1da177e4 LT |
177 | mtctl %r0, %cr17 /* Clear IIASQ tail */ |
178 | mtctl %r0, %cr17 /* Clear IIASQ head */ | |
1da177e4 LT |
179 | mtctl %r1, %cr18 /* IIAOQ head */ |
180 | ldo 4(%r1), %r1 | |
181 | mtctl %r1, %cr18 /* IIAOQ tail */ | |
896a3756 GG |
182 | load32 KERNEL_PSW, %r1 |
183 | or %r1, %r19, %r1 /* I-bit to state on entry */ | |
184 | mtctl %r1, %ipsw /* restore I-bit (entire PSW) */ | |
1da177e4 LT |
185 | rfi |
186 | nop | |
187 | ||
188 | 2: bv %r0(%r2) | |
189 | nop | |
1da177e4 | 190 | |
896a3756 | 191 | .exit |
1da177e4 | 192 | .procend |
f39cce65 | 193 | ENDPROC_CFI(flush_tlb_all_local) |
1da177e4 | 194 | |
1da177e4 LT |
195 | .import cache_info,data |
196 | ||
f39cce65 | 197 | ENTRY_CFI(flush_instruction_cache_local) |
1da177e4 LT |
198 | .proc |
199 | .callinfo NO_CALLS | |
200 | .entry | |
201 | ||
2fd83038 | 202 | load32 cache_info, %r1 |
1da177e4 LT |
203 | |
204 | /* Flush Instruction Cache */ | |
205 | ||
206 | LDREG ICACHE_BASE(%r1), %arg0 | |
207 | LDREG ICACHE_STRIDE(%r1), %arg1 | |
208 | LDREG ICACHE_COUNT(%r1), %arg2 | |
209 | LDREG ICACHE_LOOP(%r1), %arg3 | |
6d2ddc2f JDA |
210 | rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/ |
211 | mtsp %r0, %sr1 | |
872f6deb | 212 | addib,COND(=) -1, %arg3, fioneloop /* Preadjust and test */ |
1da177e4 LT |
213 | movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */ |
214 | ||
215 | fimanyloop: /* Loop if LOOP >= 2 */ | |
872f6deb | 216 | addib,COND(>) -1, %r31, fimanyloop /* Adjusted inner loop decr */ |
9b3b331d | 217 | fice %r0(%sr1, %arg0) |
1da177e4 LT |
218 | fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */ |
219 | movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */ | |
872f6deb | 220 | addib,COND(<=),n -1, %arg2, fisync /* Outer loop decr */ |
1da177e4 LT |
221 | |
222 | fioneloop: /* Loop if LOOP = 1 */ | |
6d2ddc2f JDA |
223 | /* Some implementations may flush with a single fice instruction */ |
224 | cmpib,COND(>>=),n 15, %arg2, fioneloop2 | |
225 | ||
226 | fioneloop1: | |
227 | fice,m %arg1(%sr1, %arg0) | |
228 | fice,m %arg1(%sr1, %arg0) | |
229 | fice,m %arg1(%sr1, %arg0) | |
230 | fice,m %arg1(%sr1, %arg0) | |
231 | fice,m %arg1(%sr1, %arg0) | |
232 | fice,m %arg1(%sr1, %arg0) | |
233 | fice,m %arg1(%sr1, %arg0) | |
234 | fice,m %arg1(%sr1, %arg0) | |
235 | fice,m %arg1(%sr1, %arg0) | |
236 | fice,m %arg1(%sr1, %arg0) | |
237 | fice,m %arg1(%sr1, %arg0) | |
238 | fice,m %arg1(%sr1, %arg0) | |
239 | fice,m %arg1(%sr1, %arg0) | |
240 | fice,m %arg1(%sr1, %arg0) | |
241 | fice,m %arg1(%sr1, %arg0) | |
242 | addib,COND(>) -16, %arg2, fioneloop1 | |
243 | fice,m %arg1(%sr1, %arg0) | |
244 | ||
245 | /* Check if done */ | |
246 | cmpb,COND(=),n %arg2, %r0, fisync /* Predict branch taken */ | |
247 | ||
248 | fioneloop2: | |
249 | addib,COND(>) -1, %arg2, fioneloop2 /* Outer loop count decr */ | |
1da177e4 LT |
250 | fice,m %arg1(%sr1, %arg0) /* Fice for one loop */ |
251 | ||
252 | fisync: | |
253 | sync | |
896a3756 | 254 | mtsm %r22 /* restore I-bit */ |
1da177e4 LT |
255 | bv %r0(%r2) |
256 | nop | |
257 | .exit | |
258 | ||
259 | .procend | |
f39cce65 | 260 | ENDPROC_CFI(flush_instruction_cache_local) |
1da177e4 | 261 | |
1da177e4 | 262 | |
8e9e9844 | 263 | .import cache_info, data |
f39cce65 | 264 | ENTRY_CFI(flush_data_cache_local) |
1da177e4 LT |
265 | .proc |
266 | .callinfo NO_CALLS | |
267 | .entry | |
268 | ||
6d2ddc2f | 269 | load32 cache_info, %r1 |
1da177e4 LT |
270 | |
271 | /* Flush Data Cache */ | |
272 | ||
273 | LDREG DCACHE_BASE(%r1), %arg0 | |
274 | LDREG DCACHE_STRIDE(%r1), %arg1 | |
275 | LDREG DCACHE_COUNT(%r1), %arg2 | |
276 | LDREG DCACHE_LOOP(%r1), %arg3 | |
6d2ddc2f JDA |
277 | rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/ |
278 | mtsp %r0, %sr1 | |
872f6deb | 279 | addib,COND(=) -1, %arg3, fdoneloop /* Preadjust and test */ |
1da177e4 LT |
280 | movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */ |
281 | ||
282 | fdmanyloop: /* Loop if LOOP >= 2 */ | |
872f6deb | 283 | addib,COND(>) -1, %r31, fdmanyloop /* Adjusted inner loop decr */ |
9b3b331d | 284 | fdce %r0(%sr1, %arg0) |
1da177e4 LT |
285 | fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */ |
286 | movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */ | |
872f6deb | 287 | addib,COND(<=),n -1, %arg2, fdsync /* Outer loop decr */ |
1da177e4 LT |
288 | |
289 | fdoneloop: /* Loop if LOOP = 1 */ | |
6d2ddc2f JDA |
290 | /* Some implementations may flush with a single fdce instruction */ |
291 | cmpib,COND(>>=),n 15, %arg2, fdoneloop2 | |
292 | ||
293 | fdoneloop1: | |
294 | fdce,m %arg1(%sr1, %arg0) | |
295 | fdce,m %arg1(%sr1, %arg0) | |
296 | fdce,m %arg1(%sr1, %arg0) | |
297 | fdce,m %arg1(%sr1, %arg0) | |
298 | fdce,m %arg1(%sr1, %arg0) | |
299 | fdce,m %arg1(%sr1, %arg0) | |
300 | fdce,m %arg1(%sr1, %arg0) | |
301 | fdce,m %arg1(%sr1, %arg0) | |
302 | fdce,m %arg1(%sr1, %arg0) | |
303 | fdce,m %arg1(%sr1, %arg0) | |
304 | fdce,m %arg1(%sr1, %arg0) | |
305 | fdce,m %arg1(%sr1, %arg0) | |
306 | fdce,m %arg1(%sr1, %arg0) | |
307 | fdce,m %arg1(%sr1, %arg0) | |
308 | fdce,m %arg1(%sr1, %arg0) | |
309 | addib,COND(>) -16, %arg2, fdoneloop1 | |
310 | fdce,m %arg1(%sr1, %arg0) | |
311 | ||
312 | /* Check if done */ | |
313 | cmpb,COND(=),n %arg2, %r0, fdsync /* Predict branch taken */ | |
314 | ||
315 | fdoneloop2: | |
316 | addib,COND(>) -1, %arg2, fdoneloop2 /* Outer loop count decr */ | |
1da177e4 LT |
317 | fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */ |
318 | ||
319 | fdsync: | |
320 | syncdma | |
321 | sync | |
896a3756 | 322 | mtsm %r22 /* restore I-bit */ |
1da177e4 LT |
323 | bv %r0(%r2) |
324 | nop | |
325 | .exit | |
326 | ||
327 | .procend | |
f39cce65 | 328 | ENDPROC_CFI(flush_data_cache_local) |
1da177e4 | 329 | |
1da177e4 LT |
330 | .align 16 |
331 | ||
6d2ddc2f JDA |
332 | /* Macros to serialize TLB purge operations on SMP. */ |
333 | ||
334 | .macro tlb_lock la,flags,tmp | |
335 | #ifdef CONFIG_SMP | |
336 | ldil L%pa_tlb_lock,%r1 | |
337 | ldo R%pa_tlb_lock(%r1),\la | |
338 | rsm PSW_SM_I,\flags | |
339 | 1: LDCW 0(\la),\tmp | |
340 | cmpib,<>,n 0,\tmp,3f | |
341 | 2: ldw 0(\la),\tmp | |
342 | cmpb,<> %r0,\tmp,1b | |
343 | nop | |
344 | b,n 2b | |
345 | 3: | |
346 | #endif | |
347 | .endm | |
348 | ||
349 | .macro tlb_unlock la,flags,tmp | |
350 | #ifdef CONFIG_SMP | |
351 | ldi 1,\tmp | |
352 | stw \tmp,0(\la) | |
353 | mtsm \flags | |
354 | #endif | |
355 | .endm | |
356 | ||
357 | /* Clear page using kernel mapping. */ | |
358 | ||
f39cce65 | 359 | ENTRY_CFI(clear_page_asm) |
6d2ddc2f JDA |
360 | .proc |
361 | .callinfo NO_CALLS | |
362 | .entry | |
363 | ||
364 | #ifdef CONFIG_64BIT | |
365 | ||
366 | /* Unroll the loop. */ | |
367 | ldi (PAGE_SIZE / 128), %r1 | |
368 | ||
369 | 1: | |
370 | std %r0, 0(%r26) | |
371 | std %r0, 8(%r26) | |
372 | std %r0, 16(%r26) | |
373 | std %r0, 24(%r26) | |
374 | std %r0, 32(%r26) | |
375 | std %r0, 40(%r26) | |
376 | std %r0, 48(%r26) | |
377 | std %r0, 56(%r26) | |
378 | std %r0, 64(%r26) | |
379 | std %r0, 72(%r26) | |
380 | std %r0, 80(%r26) | |
381 | std %r0, 88(%r26) | |
382 | std %r0, 96(%r26) | |
383 | std %r0, 104(%r26) | |
384 | std %r0, 112(%r26) | |
385 | std %r0, 120(%r26) | |
386 | ||
387 | /* Note reverse branch hint for addib is taken. */ | |
388 | addib,COND(>),n -1, %r1, 1b | |
389 | ldo 128(%r26), %r26 | |
390 | ||
391 | #else | |
392 | ||
393 | /* | |
394 | * Note that until (if) we start saving the full 64-bit register | |
395 | * values on interrupt, we can't use std on a 32 bit kernel. | |
396 | */ | |
397 | ldi (PAGE_SIZE / 64), %r1 | |
398 | ||
399 | 1: | |
400 | stw %r0, 0(%r26) | |
401 | stw %r0, 4(%r26) | |
402 | stw %r0, 8(%r26) | |
403 | stw %r0, 12(%r26) | |
404 | stw %r0, 16(%r26) | |
405 | stw %r0, 20(%r26) | |
406 | stw %r0, 24(%r26) | |
407 | stw %r0, 28(%r26) | |
408 | stw %r0, 32(%r26) | |
409 | stw %r0, 36(%r26) | |
410 | stw %r0, 40(%r26) | |
411 | stw %r0, 44(%r26) | |
412 | stw %r0, 48(%r26) | |
413 | stw %r0, 52(%r26) | |
414 | stw %r0, 56(%r26) | |
415 | stw %r0, 60(%r26) | |
416 | ||
417 | addib,COND(>),n -1, %r1, 1b | |
418 | ldo 64(%r26), %r26 | |
419 | #endif | |
420 | bv %r0(%r2) | |
421 | nop | |
422 | .exit | |
423 | ||
424 | .procend | |
f39cce65 | 425 | ENDPROC_CFI(clear_page_asm) |
6d2ddc2f JDA |
426 | |
427 | /* Copy page using kernel mapping. */ | |
428 | ||
f39cce65 | 429 | ENTRY_CFI(copy_page_asm) |
1da177e4 LT |
430 | .proc |
431 | .callinfo NO_CALLS | |
432 | .entry | |
433 | ||
413059f2 | 434 | #ifdef CONFIG_64BIT |
1da177e4 LT |
435 | /* PA8x00 CPUs can consume 2 loads or 1 store per cycle. |
436 | * Unroll the loop by hand and arrange insn appropriately. | |
6d2ddc2f JDA |
437 | * Prefetch doesn't improve performance on rp3440. |
438 | * GCC probably can do this just as well... | |
1da177e4 LT |
439 | */ |
440 | ||
6ebeafff | 441 | ldi (PAGE_SIZE / 128), %r1 |
2fd83038 | 442 | |
6d2ddc2f JDA |
443 | 1: ldd 0(%r25), %r19 |
444 | ldd 8(%r25), %r20 | |
1da177e4 LT |
445 | |
446 | ldd 16(%r25), %r21 | |
447 | ldd 24(%r25), %r22 | |
448 | std %r19, 0(%r26) | |
449 | std %r20, 8(%r26) | |
450 | ||
451 | ldd 32(%r25), %r19 | |
452 | ldd 40(%r25), %r20 | |
453 | std %r21, 16(%r26) | |
454 | std %r22, 24(%r26) | |
455 | ||
456 | ldd 48(%r25), %r21 | |
457 | ldd 56(%r25), %r22 | |
458 | std %r19, 32(%r26) | |
459 | std %r20, 40(%r26) | |
460 | ||
461 | ldd 64(%r25), %r19 | |
462 | ldd 72(%r25), %r20 | |
463 | std %r21, 48(%r26) | |
464 | std %r22, 56(%r26) | |
465 | ||
466 | ldd 80(%r25), %r21 | |
467 | ldd 88(%r25), %r22 | |
468 | std %r19, 64(%r26) | |
469 | std %r20, 72(%r26) | |
470 | ||
471 | ldd 96(%r25), %r19 | |
472 | ldd 104(%r25), %r20 | |
473 | std %r21, 80(%r26) | |
474 | std %r22, 88(%r26) | |
475 | ||
476 | ldd 112(%r25), %r21 | |
477 | ldd 120(%r25), %r22 | |
6d2ddc2f | 478 | ldo 128(%r25), %r25 |
1da177e4 LT |
479 | std %r19, 96(%r26) |
480 | std %r20, 104(%r26) | |
481 | ||
1da177e4 LT |
482 | std %r21, 112(%r26) |
483 | std %r22, 120(%r26) | |
1da177e4 | 484 | |
6d2ddc2f JDA |
485 | /* Note reverse branch hint for addib is taken. */ |
486 | addib,COND(>),n -1, %r1, 1b | |
487 | ldo 128(%r26), %r26 | |
1da177e4 LT |
488 | |
489 | #else | |
490 | ||
491 | /* | |
492 | * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw | |
493 | * bundles (very restricted rules for bundling). | |
494 | * Note that until (if) we start saving | |
495 | * the full 64 bit register values on interrupt, we can't | |
496 | * use ldd/std on a 32 bit kernel. | |
497 | */ | |
37318a3c | 498 | ldw 0(%r25), %r19 |
6ebeafff | 499 | ldi (PAGE_SIZE / 64), %r1 |
1da177e4 LT |
500 | |
501 | 1: | |
1da177e4 LT |
502 | ldw 4(%r25), %r20 |
503 | ldw 8(%r25), %r21 | |
504 | ldw 12(%r25), %r22 | |
505 | stw %r19, 0(%r26) | |
506 | stw %r20, 4(%r26) | |
507 | stw %r21, 8(%r26) | |
508 | stw %r22, 12(%r26) | |
509 | ldw 16(%r25), %r19 | |
510 | ldw 20(%r25), %r20 | |
511 | ldw 24(%r25), %r21 | |
512 | ldw 28(%r25), %r22 | |
513 | stw %r19, 16(%r26) | |
514 | stw %r20, 20(%r26) | |
515 | stw %r21, 24(%r26) | |
516 | stw %r22, 28(%r26) | |
517 | ldw 32(%r25), %r19 | |
518 | ldw 36(%r25), %r20 | |
519 | ldw 40(%r25), %r21 | |
520 | ldw 44(%r25), %r22 | |
521 | stw %r19, 32(%r26) | |
522 | stw %r20, 36(%r26) | |
523 | stw %r21, 40(%r26) | |
524 | stw %r22, 44(%r26) | |
525 | ldw 48(%r25), %r19 | |
526 | ldw 52(%r25), %r20 | |
527 | ldw 56(%r25), %r21 | |
528 | ldw 60(%r25), %r22 | |
529 | stw %r19, 48(%r26) | |
530 | stw %r20, 52(%r26) | |
37318a3c | 531 | ldo 64(%r25), %r25 |
1da177e4 LT |
532 | stw %r21, 56(%r26) |
533 | stw %r22, 60(%r26) | |
534 | ldo 64(%r26), %r26 | |
872f6deb | 535 | addib,COND(>),n -1, %r1, 1b |
37318a3c | 536 | ldw 0(%r25), %r19 |
1da177e4 LT |
537 | #endif |
538 | bv %r0(%r2) | |
539 | nop | |
540 | .exit | |
541 | ||
542 | .procend | |
f39cce65 | 543 | ENDPROC_CFI(copy_page_asm) |
1da177e4 LT |
544 | |
545 | /* | |
546 | * NOTE: Code in clear_user_page has a hard coded dependency on the | |
547 | * maximum alias boundary being 4 Mb. We've been assured by the | |
548 | * parisc chip designers that there will not ever be a parisc | |
549 | * chip with a larger alias boundary (Never say never :-) ). | |
550 | * | |
551 | * Subtle: the dtlb miss handlers support the temp alias region by | |
552 | * "knowing" that if a dtlb miss happens within the temp alias | |
553 | * region it must have occurred while in clear_user_page. Since | |
554 | * this routine makes use of processor local translations, we | |
555 | * don't want to insert them into the kernel page table. Instead, | |
556 | * we load up some general registers (they need to be registers | |
557 | * which aren't shadowed) with the physical page numbers (preshifted | |
558 | * for tlb insertion) needed to insert the translations. When we | |
559 | * miss on the translation, the dtlb miss handler inserts the | |
560 | * translation into the tlb using these values: | |
561 | * | |
562 | * %r26 physical page (shifted for tlb insert) of "to" translation | |
563 | * %r23 physical page (shifted for tlb insert) of "from" translation | |
564 | */ | |
565 | ||
6a45716a HD |
566 | /* Drop prot bits and convert to page addr for iitlbt and idtlbt */ |
567 | #define PAGE_ADD_SHIFT (PAGE_SHIFT-12) | |
568 | .macro convert_phys_for_tlb_insert20 phys | |
569 | extrd,u \phys, 56-PAGE_ADD_SHIFT, 32-PAGE_ADD_SHIFT, \phys | |
570 | #if _PAGE_SIZE_ENCODING_DEFAULT | |
571 | depdi _PAGE_SIZE_ENCODING_DEFAULT, 63, (63-58), \phys | |
572 | #endif | |
573 | .endm | |
574 | ||
1da177e4 | 575 | /* |
910a8643 JDA |
576 | * copy_user_page_asm() performs a page copy using mappings |
577 | * equivalent to the user page mappings. It can be used to | |
578 | * implement copy_user_page() but unfortunately both the `from' | |
579 | * and `to' pages need to be flushed through mappings equivalent | |
580 | * to the user mappings after the copy because the kernel accesses | |
581 | * the `from' page through the kmap kernel mapping and the `to' | |
582 | * page needs to be flushed since code can be copied. As a | |
583 | * result, this implementation is less efficient than the simpler | |
584 | * copy using the kernel mapping. It only needs the `from' page | |
585 | * to flushed via the user mapping. The kunmap routines handle | |
586 | * the flushes needed for the kernel mapping. | |
1da177e4 LT |
587 | * |
588 | * I'm still keeping this around because it may be possible to | |
589 | * use it if more information is passed into copy_user_page(). | |
590 | * Have to do some measurements to see if it is worthwhile to | |
591 | * lobby for such a change. | |
6d2ddc2f | 592 | * |
1da177e4 LT |
593 | */ |
594 | ||
f39cce65 | 595 | ENTRY_CFI(copy_user_page_asm) |
1da177e4 LT |
596 | .proc |
597 | .callinfo NO_CALLS | |
598 | .entry | |
599 | ||
6d2ddc2f JDA |
600 | /* Convert virtual `to' and `from' addresses to physical addresses. |
601 | Move `from' physical address to non shadowed register. */ | |
1da177e4 LT |
602 | ldil L%(__PAGE_OFFSET), %r1 |
603 | sub %r26, %r1, %r26 | |
6d2ddc2f | 604 | sub %r25, %r1, %r23 |
1da177e4 LT |
605 | |
606 | ldil L%(TMPALIAS_MAP_START), %r28 | |
413059f2 | 607 | #ifdef CONFIG_64BIT |
6d2ddc2f JDA |
608 | #if (TMPALIAS_MAP_START >= 0x80000000) |
609 | depdi 0, 31,32, %r28 /* clear any sign extension */ | |
610 | #endif | |
6a45716a HD |
611 | convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ |
612 | convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */ | |
6d2ddc2f | 613 | depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */ |
d845b5fb | 614 | depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
1da177e4 LT |
615 | copy %r28, %r29 |
616 | depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */ | |
617 | #else | |
618 | extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ | |
619 | extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */ | |
620 | depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */ | |
d845b5fb | 621 | depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
1da177e4 LT |
622 | copy %r28, %r29 |
623 | depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */ | |
624 | #endif | |
625 | ||
626 | /* Purge any old translations */ | |
627 | ||
6d2ddc2f | 628 | #ifdef CONFIG_PA20 |
5035b230 JDA |
629 | pdtlb,l %r0(%r28) |
630 | pdtlb,l %r0(%r29) | |
6d2ddc2f JDA |
631 | #else |
632 | tlb_lock %r20,%r21,%r22 | |
5035b230 JDA |
633 | pdtlb %r0(%r28) |
634 | pdtlb %r0(%r29) | |
6d2ddc2f JDA |
635 | tlb_unlock %r20,%r21,%r22 |
636 | #endif | |
637 | ||
638 | #ifdef CONFIG_64BIT | |
639 | /* PA8x00 CPUs can consume 2 loads or 1 store per cycle. | |
640 | * Unroll the loop by hand and arrange insn appropriately. | |
641 | * GCC probably can do this just as well. | |
642 | */ | |
1da177e4 | 643 | |
6d2ddc2f JDA |
644 | ldd 0(%r29), %r19 |
645 | ldi (PAGE_SIZE / 128), %r1 | |
646 | ||
647 | 1: ldd 8(%r29), %r20 | |
648 | ||
649 | ldd 16(%r29), %r21 | |
650 | ldd 24(%r29), %r22 | |
651 | std %r19, 0(%r28) | |
652 | std %r20, 8(%r28) | |
653 | ||
654 | ldd 32(%r29), %r19 | |
655 | ldd 40(%r29), %r20 | |
656 | std %r21, 16(%r28) | |
657 | std %r22, 24(%r28) | |
658 | ||
659 | ldd 48(%r29), %r21 | |
660 | ldd 56(%r29), %r22 | |
661 | std %r19, 32(%r28) | |
662 | std %r20, 40(%r28) | |
663 | ||
664 | ldd 64(%r29), %r19 | |
665 | ldd 72(%r29), %r20 | |
666 | std %r21, 48(%r28) | |
667 | std %r22, 56(%r28) | |
668 | ||
669 | ldd 80(%r29), %r21 | |
670 | ldd 88(%r29), %r22 | |
671 | std %r19, 64(%r28) | |
672 | std %r20, 72(%r28) | |
673 | ||
674 | ldd 96(%r29), %r19 | |
675 | ldd 104(%r29), %r20 | |
676 | std %r21, 80(%r28) | |
677 | std %r22, 88(%r28) | |
678 | ||
679 | ldd 112(%r29), %r21 | |
680 | ldd 120(%r29), %r22 | |
681 | std %r19, 96(%r28) | |
682 | std %r20, 104(%r28) | |
683 | ||
684 | ldo 128(%r29), %r29 | |
685 | std %r21, 112(%r28) | |
686 | std %r22, 120(%r28) | |
687 | ldo 128(%r28), %r28 | |
688 | ||
689 | /* conditional branches nullify on forward taken branch, and on | |
690 | * non-taken backward branch. Note that .+4 is a backwards branch. | |
691 | * The ldd should only get executed if the branch is taken. | |
692 | */ | |
693 | addib,COND(>),n -1, %r1, 1b /* bundle 10 */ | |
694 | ldd 0(%r29), %r19 /* start next loads */ | |
695 | ||
696 | #else | |
697 | ldi (PAGE_SIZE / 64), %r1 | |
1da177e4 LT |
698 | |
699 | /* | |
700 | * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw | |
701 | * bundles (very restricted rules for bundling). It probably | |
702 | * does OK on PCXU and better, but we could do better with | |
703 | * ldd/std instructions. Note that until (if) we start saving | |
704 | * the full 64 bit register values on interrupt, we can't | |
705 | * use ldd/std on a 32 bit kernel. | |
706 | */ | |
707 | ||
6d2ddc2f | 708 | 1: ldw 0(%r29), %r19 |
1da177e4 LT |
709 | ldw 4(%r29), %r20 |
710 | ldw 8(%r29), %r21 | |
711 | ldw 12(%r29), %r22 | |
712 | stw %r19, 0(%r28) | |
713 | stw %r20, 4(%r28) | |
714 | stw %r21, 8(%r28) | |
715 | stw %r22, 12(%r28) | |
716 | ldw 16(%r29), %r19 | |
717 | ldw 20(%r29), %r20 | |
718 | ldw 24(%r29), %r21 | |
719 | ldw 28(%r29), %r22 | |
720 | stw %r19, 16(%r28) | |
721 | stw %r20, 20(%r28) | |
722 | stw %r21, 24(%r28) | |
723 | stw %r22, 28(%r28) | |
724 | ldw 32(%r29), %r19 | |
725 | ldw 36(%r29), %r20 | |
726 | ldw 40(%r29), %r21 | |
727 | ldw 44(%r29), %r22 | |
728 | stw %r19, 32(%r28) | |
729 | stw %r20, 36(%r28) | |
730 | stw %r21, 40(%r28) | |
731 | stw %r22, 44(%r28) | |
732 | ldw 48(%r29), %r19 | |
733 | ldw 52(%r29), %r20 | |
734 | ldw 56(%r29), %r21 | |
735 | ldw 60(%r29), %r22 | |
736 | stw %r19, 48(%r28) | |
737 | stw %r20, 52(%r28) | |
738 | stw %r21, 56(%r28) | |
739 | stw %r22, 60(%r28) | |
740 | ldo 64(%r28), %r28 | |
6d2ddc2f | 741 | |
872f6deb | 742 | addib,COND(>) -1, %r1,1b |
1da177e4 | 743 | ldo 64(%r29), %r29 |
6d2ddc2f | 744 | #endif |
1da177e4 LT |
745 | |
746 | bv %r0(%r2) | |
747 | nop | |
748 | .exit | |
749 | ||
750 | .procend | |
f39cce65 | 751 | ENDPROC_CFI(copy_user_page_asm) |
1da177e4 | 752 | |
f39cce65 | 753 | ENTRY_CFI(clear_user_page_asm) |
1da177e4 LT |
754 | .proc |
755 | .callinfo NO_CALLS | |
756 | .entry | |
757 | ||
758 | tophys_r1 %r26 | |
759 | ||
760 | ldil L%(TMPALIAS_MAP_START), %r28 | |
413059f2 | 761 | #ifdef CONFIG_64BIT |
1da177e4 LT |
762 | #if (TMPALIAS_MAP_START >= 0x80000000) |
763 | depdi 0, 31,32, %r28 /* clear any sign extension */ | |
764 | #endif | |
6a45716a | 765 | convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ |
1da177e4 | 766 | depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ |
6a45716a | 767 | depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
1da177e4 LT |
768 | #else |
769 | extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ | |
770 | depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ | |
d845b5fb | 771 | depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
1da177e4 LT |
772 | #endif |
773 | ||
774 | /* Purge any old translation */ | |
775 | ||
6d2ddc2f | 776 | #ifdef CONFIG_PA20 |
5035b230 | 777 | pdtlb,l %r0(%r28) |
6d2ddc2f JDA |
778 | #else |
779 | tlb_lock %r20,%r21,%r22 | |
5035b230 | 780 | pdtlb %r0(%r28) |
6d2ddc2f JDA |
781 | tlb_unlock %r20,%r21,%r22 |
782 | #endif | |
1da177e4 | 783 | |
413059f2 | 784 | #ifdef CONFIG_64BIT |
6ebeafff | 785 | ldi (PAGE_SIZE / 128), %r1 |
1da177e4 LT |
786 | |
787 | /* PREFETCH (Write) has not (yet) been proven to help here */ | |
2fd83038 | 788 | /* #define PREFETCHW_OP ldd 256(%0), %r0 */ |
1da177e4 LT |
789 | |
790 | 1: std %r0, 0(%r28) | |
791 | std %r0, 8(%r28) | |
792 | std %r0, 16(%r28) | |
793 | std %r0, 24(%r28) | |
794 | std %r0, 32(%r28) | |
795 | std %r0, 40(%r28) | |
796 | std %r0, 48(%r28) | |
797 | std %r0, 56(%r28) | |
798 | std %r0, 64(%r28) | |
799 | std %r0, 72(%r28) | |
800 | std %r0, 80(%r28) | |
801 | std %r0, 88(%r28) | |
802 | std %r0, 96(%r28) | |
803 | std %r0, 104(%r28) | |
804 | std %r0, 112(%r28) | |
805 | std %r0, 120(%r28) | |
872f6deb | 806 | addib,COND(>) -1, %r1, 1b |
1da177e4 LT |
807 | ldo 128(%r28), %r28 |
808 | ||
413059f2 | 809 | #else /* ! CONFIG_64BIT */ |
6ebeafff | 810 | ldi (PAGE_SIZE / 64), %r1 |
1da177e4 | 811 | |
6d2ddc2f | 812 | 1: stw %r0, 0(%r28) |
1da177e4 LT |
813 | stw %r0, 4(%r28) |
814 | stw %r0, 8(%r28) | |
815 | stw %r0, 12(%r28) | |
816 | stw %r0, 16(%r28) | |
817 | stw %r0, 20(%r28) | |
818 | stw %r0, 24(%r28) | |
819 | stw %r0, 28(%r28) | |
820 | stw %r0, 32(%r28) | |
821 | stw %r0, 36(%r28) | |
822 | stw %r0, 40(%r28) | |
823 | stw %r0, 44(%r28) | |
824 | stw %r0, 48(%r28) | |
825 | stw %r0, 52(%r28) | |
826 | stw %r0, 56(%r28) | |
827 | stw %r0, 60(%r28) | |
872f6deb | 828 | addib,COND(>) -1, %r1, 1b |
1da177e4 | 829 | ldo 64(%r28), %r28 |
413059f2 | 830 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
831 | |
832 | bv %r0(%r2) | |
833 | nop | |
834 | .exit | |
835 | ||
836 | .procend | |
f39cce65 | 837 | ENDPROC_CFI(clear_user_page_asm) |
1da177e4 | 838 | |
f39cce65 | 839 | ENTRY_CFI(flush_dcache_page_asm) |
1da177e4 LT |
840 | .proc |
841 | .callinfo NO_CALLS | |
842 | .entry | |
843 | ||
f311847c JB |
844 | ldil L%(TMPALIAS_MAP_START), %r28 |
845 | #ifdef CONFIG_64BIT | |
846 | #if (TMPALIAS_MAP_START >= 0x80000000) | |
847 | depdi 0, 31,32, %r28 /* clear any sign extension */ | |
f311847c | 848 | #endif |
6a45716a | 849 | convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ |
f311847c | 850 | depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ |
6a45716a | 851 | depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
f311847c JB |
852 | #else |
853 | extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ | |
854 | depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ | |
d845b5fb | 855 | depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
f311847c JB |
856 | #endif |
857 | ||
858 | /* Purge any old translation */ | |
859 | ||
6d2ddc2f | 860 | #ifdef CONFIG_PA20 |
5035b230 | 861 | pdtlb,l %r0(%r28) |
6d2ddc2f JDA |
862 | #else |
863 | tlb_lock %r20,%r21,%r22 | |
5035b230 | 864 | pdtlb %r0(%r28) |
6d2ddc2f JDA |
865 | tlb_unlock %r20,%r21,%r22 |
866 | #endif | |
f311847c | 867 | |
1da177e4 | 868 | ldil L%dcache_stride, %r1 |
d65ea48d | 869 | ldw R%dcache_stride(%r1), r31 |
1da177e4 | 870 | |
413059f2 | 871 | #ifdef CONFIG_64BIT |
1da177e4 LT |
872 | depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
873 | #else | |
874 | depwi,z 1, 31-PAGE_SHIFT,1, %r25 | |
875 | #endif | |
f311847c | 876 | add %r28, %r25, %r25 |
d65ea48d JDA |
877 | sub %r25, r31, %r25 |
878 | ||
879 | ||
880 | 1: fdc,m r31(%r28) | |
881 | fdc,m r31(%r28) | |
882 | fdc,m r31(%r28) | |
883 | fdc,m r31(%r28) | |
884 | fdc,m r31(%r28) | |
885 | fdc,m r31(%r28) | |
886 | fdc,m r31(%r28) | |
887 | fdc,m r31(%r28) | |
888 | fdc,m r31(%r28) | |
889 | fdc,m r31(%r28) | |
890 | fdc,m r31(%r28) | |
891 | fdc,m r31(%r28) | |
892 | fdc,m r31(%r28) | |
893 | fdc,m r31(%r28) | |
894 | fdc,m r31(%r28) | |
f311847c | 895 | cmpb,COND(<<) %r28, %r25,1b |
d65ea48d | 896 | fdc,m r31(%r28) |
1da177e4 LT |
897 | |
898 | sync | |
6d2ddc2f JDA |
899 | |
900 | #ifdef CONFIG_PA20 | |
5035b230 | 901 | pdtlb,l %r0(%r25) |
6d2ddc2f JDA |
902 | #else |
903 | tlb_lock %r20,%r21,%r22 | |
5035b230 | 904 | pdtlb %r0(%r25) |
6d2ddc2f JDA |
905 | tlb_unlock %r20,%r21,%r22 |
906 | #endif | |
907 | ||
1da177e4 | 908 | bv %r0(%r2) |
6d2ddc2f | 909 | nop |
1da177e4 LT |
910 | .exit |
911 | ||
912 | .procend | |
f39cce65 | 913 | ENDPROC_CFI(flush_dcache_page_asm) |
f311847c | 914 | |
f39cce65 | 915 | ENTRY_CFI(flush_icache_page_asm) |
1da177e4 LT |
916 | .proc |
917 | .callinfo NO_CALLS | |
918 | .entry | |
919 | ||
f311847c | 920 | ldil L%(TMPALIAS_MAP_START), %r28 |
413059f2 | 921 | #ifdef CONFIG_64BIT |
f311847c JB |
922 | #if (TMPALIAS_MAP_START >= 0x80000000) |
923 | depdi 0, 31,32, %r28 /* clear any sign extension */ | |
f311847c | 924 | #endif |
6a45716a | 925 | convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ |
f311847c | 926 | depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ |
d845b5fb | 927 | depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
1da177e4 | 928 | #else |
f311847c JB |
929 | extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ |
930 | depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ | |
d845b5fb | 931 | depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
1da177e4 | 932 | #endif |
1da177e4 | 933 | |
5035b230 JDA |
934 | /* Purge any old translation. Note that the FIC instruction |
935 | * may use either the instruction or data TLB. Given that we | |
936 | * have a flat address space, it's not clear which TLB will be | |
937 | * used. So, we purge both entries. */ | |
1da177e4 | 938 | |
6d2ddc2f | 939 | #ifdef CONFIG_PA20 |
5035b230 | 940 | pdtlb,l %r0(%r28) |
6d2ddc2f JDA |
941 | pitlb,l %r0(%sr4,%r28) |
942 | #else | |
943 | tlb_lock %r20,%r21,%r22 | |
5035b230 JDA |
944 | pdtlb %r0(%r28) |
945 | pitlb %r0(%sr4,%r28) | |
6d2ddc2f JDA |
946 | tlb_unlock %r20,%r21,%r22 |
947 | #endif | |
f311847c JB |
948 | |
949 | ldil L%icache_stride, %r1 | |
d65ea48d | 950 | ldw R%icache_stride(%r1), %r31 |
f311847c JB |
951 | |
952 | #ifdef CONFIG_64BIT | |
953 | depdi,z 1, 63-PAGE_SHIFT,1, %r25 | |
954 | #else | |
955 | depwi,z 1, 31-PAGE_SHIFT,1, %r25 | |
956 | #endif | |
957 | add %r28, %r25, %r25 | |
d65ea48d | 958 | sub %r25, %r31, %r25 |
f311847c JB |
959 | |
960 | ||
207f583d JDA |
961 | /* fic only has the type 26 form on PA1.1, requiring an |
962 | * explicit space specification, so use %sr4 */ | |
d65ea48d JDA |
963 | 1: fic,m %r31(%sr4,%r28) |
964 | fic,m %r31(%sr4,%r28) | |
965 | fic,m %r31(%sr4,%r28) | |
966 | fic,m %r31(%sr4,%r28) | |
967 | fic,m %r31(%sr4,%r28) | |
968 | fic,m %r31(%sr4,%r28) | |
969 | fic,m %r31(%sr4,%r28) | |
970 | fic,m %r31(%sr4,%r28) | |
971 | fic,m %r31(%sr4,%r28) | |
972 | fic,m %r31(%sr4,%r28) | |
973 | fic,m %r31(%sr4,%r28) | |
974 | fic,m %r31(%sr4,%r28) | |
975 | fic,m %r31(%sr4,%r28) | |
976 | fic,m %r31(%sr4,%r28) | |
977 | fic,m %r31(%sr4,%r28) | |
6a45716a | 978 | cmpb,COND(<<) %r28, %r25,1b |
d65ea48d | 979 | fic,m %r31(%sr4,%r28) |
1da177e4 LT |
980 | |
981 | sync | |
6d2ddc2f JDA |
982 | |
983 | #ifdef CONFIG_PA20 | |
5035b230 | 984 | pdtlb,l %r0(%r28) |
6d2ddc2f JDA |
985 | pitlb,l %r0(%sr4,%r25) |
986 | #else | |
987 | tlb_lock %r20,%r21,%r22 | |
5035b230 JDA |
988 | pdtlb %r0(%r28) |
989 | pitlb %r0(%sr4,%r25) | |
6d2ddc2f JDA |
990 | tlb_unlock %r20,%r21,%r22 |
991 | #endif | |
992 | ||
1da177e4 | 993 | bv %r0(%r2) |
6d2ddc2f | 994 | nop |
1da177e4 LT |
995 | .exit |
996 | ||
997 | .procend | |
f39cce65 | 998 | ENDPROC_CFI(flush_icache_page_asm) |
1da177e4 | 999 | |
f39cce65 | 1000 | ENTRY_CFI(flush_kernel_dcache_page_asm) |
1da177e4 LT |
1001 | .proc |
1002 | .callinfo NO_CALLS | |
1003 | .entry | |
1004 | ||
1005 | ldil L%dcache_stride, %r1 | |
1006 | ldw R%dcache_stride(%r1), %r23 | |
1007 | ||
413059f2 | 1008 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1009 | depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
1010 | #else | |
1011 | depwi,z 1, 31-PAGE_SHIFT,1, %r25 | |
1012 | #endif | |
1013 | add %r26, %r25, %r25 | |
1014 | sub %r25, %r23, %r25 | |
1015 | ||
1016 | ||
f311847c JB |
1017 | 1: fdc,m %r23(%r26) |
1018 | fdc,m %r23(%r26) | |
1019 | fdc,m %r23(%r26) | |
1020 | fdc,m %r23(%r26) | |
1021 | fdc,m %r23(%r26) | |
1022 | fdc,m %r23(%r26) | |
1023 | fdc,m %r23(%r26) | |
1024 | fdc,m %r23(%r26) | |
1025 | fdc,m %r23(%r26) | |
1026 | fdc,m %r23(%r26) | |
1027 | fdc,m %r23(%r26) | |
1028 | fdc,m %r23(%r26) | |
1029 | fdc,m %r23(%r26) | |
1030 | fdc,m %r23(%r26) | |
1031 | fdc,m %r23(%r26) | |
872f6deb | 1032 | cmpb,COND(<<) %r26, %r25,1b |
f311847c | 1033 | fdc,m %r23(%r26) |
1da177e4 LT |
1034 | |
1035 | sync | |
1036 | bv %r0(%r2) | |
1037 | nop | |
1038 | .exit | |
1039 | ||
1040 | .procend | |
f39cce65 | 1041 | ENDPROC_CFI(flush_kernel_dcache_page_asm) |
1da177e4 | 1042 | |
f39cce65 | 1043 | ENTRY_CFI(purge_kernel_dcache_page_asm) |
1da177e4 LT |
1044 | .proc |
1045 | .callinfo NO_CALLS | |
1046 | .entry | |
1047 | ||
1048 | ldil L%dcache_stride, %r1 | |
1049 | ldw R%dcache_stride(%r1), %r23 | |
1050 | ||
413059f2 | 1051 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1052 | depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
1053 | #else | |
1054 | depwi,z 1, 31-PAGE_SHIFT,1, %r25 | |
1055 | #endif | |
1056 | add %r26, %r25, %r25 | |
1057 | sub %r25, %r23, %r25 | |
1058 | ||
1059 | 1: pdc,m %r23(%r26) | |
1060 | pdc,m %r23(%r26) | |
1061 | pdc,m %r23(%r26) | |
1062 | pdc,m %r23(%r26) | |
1063 | pdc,m %r23(%r26) | |
1064 | pdc,m %r23(%r26) | |
1065 | pdc,m %r23(%r26) | |
1066 | pdc,m %r23(%r26) | |
1067 | pdc,m %r23(%r26) | |
1068 | pdc,m %r23(%r26) | |
1069 | pdc,m %r23(%r26) | |
1070 | pdc,m %r23(%r26) | |
1071 | pdc,m %r23(%r26) | |
1072 | pdc,m %r23(%r26) | |
1073 | pdc,m %r23(%r26) | |
872f6deb | 1074 | cmpb,COND(<<) %r26, %r25, 1b |
1da177e4 LT |
1075 | pdc,m %r23(%r26) |
1076 | ||
1077 | sync | |
1078 | bv %r0(%r2) | |
1079 | nop | |
1080 | .exit | |
1081 | ||
1082 | .procend | |
f39cce65 | 1083 | ENDPROC_CFI(purge_kernel_dcache_page_asm) |
1da177e4 | 1084 | |
f39cce65 | 1085 | ENTRY_CFI(flush_user_dcache_range_asm) |
1da177e4 LT |
1086 | .proc |
1087 | .callinfo NO_CALLS | |
1088 | .entry | |
1089 | ||
1090 | ldil L%dcache_stride, %r1 | |
1091 | ldw R%dcache_stride(%r1), %r23 | |
1092 | ldo -1(%r23), %r21 | |
1093 | ANDCM %r26, %r21, %r26 | |
1094 | ||
872f6deb | 1095 | 1: cmpb,COND(<<),n %r26, %r25, 1b |
1da177e4 LT |
1096 | fdc,m %r23(%sr3, %r26) |
1097 | ||
1098 | sync | |
1099 | bv %r0(%r2) | |
1100 | nop | |
1101 | .exit | |
1102 | ||
1103 | .procend | |
f39cce65 | 1104 | ENDPROC_CFI(flush_user_dcache_range_asm) |
1da177e4 | 1105 | |
f39cce65 | 1106 | ENTRY_CFI(flush_kernel_dcache_range_asm) |
1da177e4 LT |
1107 | .proc |
1108 | .callinfo NO_CALLS | |
1109 | .entry | |
1110 | ||
1111 | ldil L%dcache_stride, %r1 | |
1112 | ldw R%dcache_stride(%r1), %r23 | |
1113 | ldo -1(%r23), %r21 | |
1114 | ANDCM %r26, %r21, %r26 | |
1115 | ||
872f6deb | 1116 | 1: cmpb,COND(<<),n %r26, %r25,1b |
1da177e4 LT |
1117 | fdc,m %r23(%r26) |
1118 | ||
1119 | sync | |
1120 | syncdma | |
1121 | bv %r0(%r2) | |
1122 | nop | |
1123 | .exit | |
1124 | ||
1125 | .procend | |
f39cce65 | 1126 | ENDPROC_CFI(flush_kernel_dcache_range_asm) |
1da177e4 | 1127 | |
f39cce65 | 1128 | ENTRY_CFI(flush_user_icache_range_asm) |
1da177e4 LT |
1129 | .proc |
1130 | .callinfo NO_CALLS | |
1131 | .entry | |
1132 | ||
1133 | ldil L%icache_stride, %r1 | |
1134 | ldw R%icache_stride(%r1), %r23 | |
1135 | ldo -1(%r23), %r21 | |
1136 | ANDCM %r26, %r21, %r26 | |
1137 | ||
872f6deb | 1138 | 1: cmpb,COND(<<),n %r26, %r25,1b |
1da177e4 LT |
1139 | fic,m %r23(%sr3, %r26) |
1140 | ||
1141 | sync | |
1142 | bv %r0(%r2) | |
1143 | nop | |
1144 | .exit | |
1145 | ||
1146 | .procend | |
f39cce65 | 1147 | ENDPROC_CFI(flush_user_icache_range_asm) |
1da177e4 | 1148 | |
f39cce65 | 1149 | ENTRY_CFI(flush_kernel_icache_page) |
1da177e4 LT |
1150 | .proc |
1151 | .callinfo NO_CALLS | |
1152 | .entry | |
1153 | ||
1154 | ldil L%icache_stride, %r1 | |
1155 | ldw R%icache_stride(%r1), %r23 | |
1156 | ||
413059f2 | 1157 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1158 | depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
1159 | #else | |
1160 | depwi,z 1, 31-PAGE_SHIFT,1, %r25 | |
1161 | #endif | |
1162 | add %r26, %r25, %r25 | |
1163 | sub %r25, %r23, %r25 | |
1164 | ||
1165 | ||
e635c96e MW |
1166 | 1: fic,m %r23(%sr4, %r26) |
1167 | fic,m %r23(%sr4, %r26) | |
1168 | fic,m %r23(%sr4, %r26) | |
1169 | fic,m %r23(%sr4, %r26) | |
1170 | fic,m %r23(%sr4, %r26) | |
1171 | fic,m %r23(%sr4, %r26) | |
1172 | fic,m %r23(%sr4, %r26) | |
1173 | fic,m %r23(%sr4, %r26) | |
1174 | fic,m %r23(%sr4, %r26) | |
1175 | fic,m %r23(%sr4, %r26) | |
1176 | fic,m %r23(%sr4, %r26) | |
1177 | fic,m %r23(%sr4, %r26) | |
1178 | fic,m %r23(%sr4, %r26) | |
1179 | fic,m %r23(%sr4, %r26) | |
1180 | fic,m %r23(%sr4, %r26) | |
872f6deb | 1181 | cmpb,COND(<<) %r26, %r25, 1b |
e635c96e | 1182 | fic,m %r23(%sr4, %r26) |
1da177e4 LT |
1183 | |
1184 | sync | |
1185 | bv %r0(%r2) | |
1186 | nop | |
1187 | .exit | |
1188 | ||
1189 | .procend | |
f39cce65 | 1190 | ENDPROC_CFI(flush_kernel_icache_page) |
1da177e4 | 1191 | |
f39cce65 | 1192 | ENTRY_CFI(flush_kernel_icache_range_asm) |
1da177e4 LT |
1193 | .proc |
1194 | .callinfo NO_CALLS | |
1195 | .entry | |
1196 | ||
1197 | ldil L%icache_stride, %r1 | |
1198 | ldw R%icache_stride(%r1), %r23 | |
1199 | ldo -1(%r23), %r21 | |
1200 | ANDCM %r26, %r21, %r26 | |
1201 | ||
872f6deb | 1202 | 1: cmpb,COND(<<),n %r26, %r25, 1b |
e635c96e | 1203 | fic,m %r23(%sr4, %r26) |
1da177e4 LT |
1204 | |
1205 | sync | |
1206 | bv %r0(%r2) | |
1207 | nop | |
1208 | .exit | |
1da177e4 | 1209 | .procend |
f39cce65 | 1210 | ENDPROC_CFI(flush_kernel_icache_range_asm) |
1da177e4 | 1211 | |
896a3756 GG |
1212 | /* align should cover use of rfi in disable_sr_hashing_asm and |
1213 | * srdis_done. | |
1214 | */ | |
1215 | .align 256 | |
f39cce65 | 1216 | ENTRY_CFI(disable_sr_hashing_asm) |
1da177e4 LT |
1217 | .proc |
1218 | .callinfo NO_CALLS | |
1219 | .entry | |
1220 | ||
896a3756 GG |
1221 | /* |
1222 | * Switch to real mode | |
1223 | */ | |
1224 | /* pcxt_ssm_bug */ | |
1225 | rsm PSW_SM_I, %r0 | |
1226 | load32 PA(1f), %r1 | |
1da177e4 LT |
1227 | nop |
1228 | nop | |
1229 | nop | |
1230 | nop | |
1231 | nop | |
896a3756 GG |
1232 | |
1233 | rsm PSW_SM_Q, %r0 /* prep to load iia queue */ | |
1da177e4 LT |
1234 | mtctl %r0, %cr17 /* Clear IIASQ tail */ |
1235 | mtctl %r0, %cr17 /* Clear IIASQ head */ | |
1da177e4 LT |
1236 | mtctl %r1, %cr18 /* IIAOQ head */ |
1237 | ldo 4(%r1), %r1 | |
1238 | mtctl %r1, %cr18 /* IIAOQ tail */ | |
896a3756 GG |
1239 | load32 REAL_MODE_PSW, %r1 |
1240 | mtctl %r1, %ipsw | |
1da177e4 LT |
1241 | rfi |
1242 | nop | |
1243 | ||
1244 | 1: cmpib,=,n SRHASH_PCXST, %r26,srdis_pcxs | |
1245 | cmpib,=,n SRHASH_PCXL, %r26,srdis_pcxl | |
1246 | cmpib,=,n SRHASH_PA20, %r26,srdis_pa20 | |
1247 | b,n srdis_done | |
1248 | ||
1249 | srdis_pcxs: | |
1250 | ||
1251 | /* Disable Space Register Hashing for PCXS,PCXT,PCXT' */ | |
1252 | ||
1253 | .word 0x141c1a00 /* mfdiag %dr0, %r28 */ | |
1254 | .word 0x141c1a00 /* must issue twice */ | |
1255 | depwi 0,18,1, %r28 /* Clear DHE (dcache hash enable) */ | |
1256 | depwi 0,20,1, %r28 /* Clear IHE (icache hash enable) */ | |
1257 | .word 0x141c1600 /* mtdiag %r28, %dr0 */ | |
1258 | .word 0x141c1600 /* must issue twice */ | |
1259 | b,n srdis_done | |
1260 | ||
1261 | srdis_pcxl: | |
1262 | ||
1263 | /* Disable Space Register Hashing for PCXL */ | |
1264 | ||
1265 | .word 0x141c0600 /* mfdiag %dr0, %r28 */ | |
1266 | depwi 0,28,2, %r28 /* Clear DHASH_EN & IHASH_EN */ | |
1267 | .word 0x141c0240 /* mtdiag %r28, %dr0 */ | |
1268 | b,n srdis_done | |
1269 | ||
1270 | srdis_pa20: | |
1271 | ||
896a3756 | 1272 | /* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */ |
1da177e4 LT |
1273 | |
1274 | .word 0x144008bc /* mfdiag %dr2, %r28 */ | |
1275 | depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */ | |
1276 | .word 0x145c1840 /* mtdiag %r28, %dr2 */ | |
1277 | ||
1da177e4 | 1278 | |
896a3756 | 1279 | srdis_done: |
1da177e4 | 1280 | /* Switch back to virtual mode */ |
896a3756 GG |
1281 | rsm PSW_SM_I, %r0 /* prep to load iia queue */ |
1282 | load32 2f, %r1 | |
1283 | nop | |
1284 | nop | |
1285 | nop | |
1286 | nop | |
1287 | nop | |
1da177e4 | 1288 | |
896a3756 | 1289 | rsm PSW_SM_Q, %r0 /* prep to load iia queue */ |
1da177e4 LT |
1290 | mtctl %r0, %cr17 /* Clear IIASQ tail */ |
1291 | mtctl %r0, %cr17 /* Clear IIASQ head */ | |
1da177e4 LT |
1292 | mtctl %r1, %cr18 /* IIAOQ head */ |
1293 | ldo 4(%r1), %r1 | |
1294 | mtctl %r1, %cr18 /* IIAOQ tail */ | |
896a3756 GG |
1295 | load32 KERNEL_PSW, %r1 |
1296 | mtctl %r1, %ipsw | |
1da177e4 LT |
1297 | rfi |
1298 | nop | |
1299 | ||
1300 | 2: bv %r0(%r2) | |
1301 | nop | |
1302 | .exit | |
1303 | ||
1304 | .procend | |
f39cce65 | 1305 | ENDPROC_CFI(disable_sr_hashing_asm) |
1da177e4 LT |
1306 | |
1307 | .end |