]>
Commit | Line | Data |
---|---|---|
5761bc5d LY |
1 | /* |
2 | * MPC8377E MDS Device Tree Source | |
3 | * | |
4 | * Copyright 2007 Freescale Semiconductor Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | /dts-v1/; | |
13 | ||
14 | / { | |
15 | model = "fsl,mpc8377emds"; | |
16 | compatible = "fsl,mpc8377emds","fsl,mpc837xmds"; | |
17 | #address-cells = <1>; | |
18 | #size-cells = <1>; | |
19 | ||
20 | aliases { | |
21 | ethernet0 = &enet0; | |
22 | ethernet1 = &enet1; | |
23 | serial0 = &serial0; | |
24 | serial1 = &serial1; | |
25 | pci0 = &pci0; | |
26 | }; | |
27 | ||
28 | cpus { | |
29 | #address-cells = <1>; | |
30 | #size-cells = <0>; | |
31 | ||
32 | PowerPC,8377@0 { | |
33 | device_type = "cpu"; | |
cda13dd1 PG |
34 | reg = <0x0>; |
35 | d-cache-line-size = <32>; | |
36 | i-cache-line-size = <32>; | |
37 | d-cache-size = <32768>; | |
38 | i-cache-size = <32768>; | |
5761bc5d LY |
39 | timebase-frequency = <0>; |
40 | bus-frequency = <0>; | |
41 | clock-frequency = <0>; | |
42 | }; | |
43 | }; | |
44 | ||
45 | memory { | |
46 | device_type = "memory"; | |
47 | reg = <0x00000000 0x20000000>; // 512MB at 0 | |
48 | }; | |
49 | ||
d7f46190 LY |
50 | localbus@e0005000 { |
51 | #address-cells = <2>; | |
52 | #size-cells = <1>; | |
53 | compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus"; | |
54 | reg = <0xe0005000 0x1000>; | |
55 | interrupts = <77 0x8>; | |
56 | interrupt-parent = <&ipic>; | |
57 | ||
58 | // booting from NOR flash | |
59 | ranges = <0 0x0 0xfe000000 0x02000000 | |
60 | 1 0x0 0xf8000000 0x00008000 | |
61 | 3 0x0 0xe0600000 0x00008000>; | |
62 | ||
63 | flash@0,0 { | |
64 | #address-cells = <1>; | |
65 | #size-cells = <1>; | |
66 | compatible = "cfi-flash"; | |
67 | reg = <0 0x0 0x2000000>; | |
68 | bank-width = <2>; | |
69 | device-width = <1>; | |
70 | ||
71 | u-boot@0 { | |
72 | reg = <0x0 0x100000>; | |
73 | read-only; | |
74 | }; | |
75 | ||
76 | fs@100000 { | |
77 | reg = <0x100000 0x800000>; | |
78 | }; | |
79 | ||
80 | kernel@1d00000 { | |
81 | reg = <0x1d00000 0x200000>; | |
82 | }; | |
83 | ||
84 | dtb@1f00000 { | |
85 | reg = <0x1f00000 0x100000>; | |
86 | }; | |
87 | }; | |
88 | ||
89 | bcsr@1,0 { | |
90 | reg = <1 0x0 0x8000>; | |
91 | compatible = "fsl,mpc837xmds-bcsr"; | |
92 | }; | |
93 | ||
94 | nand@3,0 { | |
95 | #address-cells = <1>; | |
96 | #size-cells = <1>; | |
97 | compatible = "fsl,mpc8377-fcm-nand", | |
98 | "fsl,elbc-fcm-nand"; | |
99 | reg = <3 0x0 0x8000>; | |
100 | ||
101 | u-boot@0 { | |
102 | reg = <0x0 0x100000>; | |
103 | read-only; | |
104 | }; | |
105 | ||
106 | kernel@100000 { | |
107 | reg = <0x100000 0x300000>; | |
108 | }; | |
109 | ||
110 | fs@400000 { | |
111 | reg = <0x400000 0x1c00000>; | |
112 | }; | |
113 | }; | |
114 | }; | |
115 | ||
5761bc5d LY |
116 | soc@e0000000 { |
117 | #address-cells = <1>; | |
118 | #size-cells = <1>; | |
119 | device_type = "soc"; | |
120 | ranges = <0x0 0xe0000000 0x00100000>; | |
121 | reg = <0xe0000000 0x00000200>; | |
122 | bus-frequency = <0>; | |
123 | ||
124 | wdt@200 { | |
125 | compatible = "mpc83xx_wdt"; | |
126 | reg = <0x200 0x100>; | |
127 | }; | |
128 | ||
129 | i2c@3000 { | |
130 | #address-cells = <1>; | |
131 | #size-cells = <0>; | |
132 | cell-index = <0>; | |
133 | compatible = "fsl-i2c"; | |
134 | reg = <0x3000 0x100>; | |
cda13dd1 PG |
135 | interrupts = <14 0x8>; |
136 | interrupt-parent = <&ipic>; | |
5761bc5d LY |
137 | dfsrr; |
138 | }; | |
139 | ||
140 | i2c@3100 { | |
141 | #address-cells = <1>; | |
142 | #size-cells = <0>; | |
143 | cell-index = <1>; | |
144 | compatible = "fsl-i2c"; | |
145 | reg = <0x3100 0x100>; | |
cda13dd1 PG |
146 | interrupts = <15 0x8>; |
147 | interrupt-parent = <&ipic>; | |
5761bc5d LY |
148 | dfsrr; |
149 | }; | |
150 | ||
151 | spi@7000 { | |
f3a2b29d AV |
152 | cell-index = <0>; |
153 | compatible = "fsl,spi"; | |
5761bc5d | 154 | reg = <0x7000 0x1000>; |
cda13dd1 PG |
155 | interrupts = <16 0x8>; |
156 | interrupt-parent = <&ipic>; | |
5761bc5d LY |
157 | mode = "cpu"; |
158 | }; | |
159 | ||
5761bc5d LY |
160 | usb@23000 { |
161 | compatible = "fsl-usb2-dr"; | |
162 | reg = <0x23000 0x1000>; | |
163 | #address-cells = <1>; | |
164 | #size-cells = <0>; | |
cda13dd1 PG |
165 | interrupt-parent = <&ipic>; |
166 | interrupts = <38 0x8>; | |
28b95885 LY |
167 | dr_mode = "host"; |
168 | phy_type = "ulpi"; | |
5761bc5d LY |
169 | }; |
170 | ||
171 | mdio@24520 { | |
172 | #address-cells = <1>; | |
173 | #size-cells = <0>; | |
174 | compatible = "fsl,gianfar-mdio"; | |
175 | reg = <0x24520 0x20>; | |
176 | phy2: ethernet-phy@2 { | |
cda13dd1 PG |
177 | interrupt-parent = <&ipic>; |
178 | interrupts = <17 0x8>; | |
179 | reg = <0x2>; | |
5761bc5d LY |
180 | device_type = "ethernet-phy"; |
181 | }; | |
182 | phy3: ethernet-phy@3 { | |
cda13dd1 PG |
183 | interrupt-parent = <&ipic>; |
184 | interrupts = <18 0x8>; | |
185 | reg = <0x3>; | |
5761bc5d LY |
186 | device_type = "ethernet-phy"; |
187 | }; | |
188 | }; | |
189 | ||
190 | enet0: ethernet@24000 { | |
191 | cell-index = <0>; | |
192 | device_type = "network"; | |
193 | model = "eTSEC"; | |
194 | compatible = "gianfar"; | |
195 | reg = <0x24000 0x1000>; | |
196 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
cda13dd1 | 197 | interrupts = <32 0x8 33 0x8 34 0x8>; |
5761bc5d | 198 | phy-connection-type = "mii"; |
cda13dd1 PG |
199 | interrupt-parent = <&ipic>; |
200 | phy-handle = <&phy2>; | |
5761bc5d LY |
201 | }; |
202 | ||
203 | enet1: ethernet@25000 { | |
204 | cell-index = <1>; | |
205 | device_type = "network"; | |
206 | model = "eTSEC"; | |
207 | compatible = "gianfar"; | |
208 | reg = <0x25000 0x1000>; | |
209 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
cda13dd1 | 210 | interrupts = <35 0x8 36 0x8 37 0x8>; |
5761bc5d | 211 | phy-connection-type = "mii"; |
cda13dd1 PG |
212 | interrupt-parent = <&ipic>; |
213 | phy-handle = <&phy3>; | |
5761bc5d LY |
214 | }; |
215 | ||
216 | serial0: serial@4500 { | |
217 | cell-index = <0>; | |
218 | device_type = "serial"; | |
219 | compatible = "ns16550"; | |
220 | reg = <0x4500 0x100>; | |
221 | clock-frequency = <0>; | |
cda13dd1 PG |
222 | interrupts = <9 0x8>; |
223 | interrupt-parent = <&ipic>; | |
5761bc5d LY |
224 | }; |
225 | ||
226 | serial1: serial@4600 { | |
227 | cell-index = <1>; | |
228 | device_type = "serial"; | |
229 | compatible = "ns16550"; | |
230 | reg = <0x4600 0x100>; | |
231 | clock-frequency = <0>; | |
cda13dd1 PG |
232 | interrupts = <10 0x8>; |
233 | interrupt-parent = <&ipic>; | |
5761bc5d LY |
234 | }; |
235 | ||
3f346935 ZW |
236 | dma@82a8 { |
237 | #address-cells = <1>; | |
238 | #size-cells = <1>; | |
8939700e | 239 | compatible = "fsl,mpc8377-dma", "fsl,elo-dma"; |
3f346935 ZW |
240 | reg = <0x82a8 4>; |
241 | ranges = <0 0x8100 0x1a8>; | |
242 | interrupt-parent = <&ipic>; | |
243 | interrupts = <0x47 8>; | |
244 | cell-index = <0>; | |
245 | dma-channel@0 { | |
8939700e | 246 | compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; |
3f346935 | 247 | reg = <0 0x80>; |
8939700e KG |
248 | interrupt-parent = <&ipic>; |
249 | interrupts = <0x47 8>; | |
3f346935 ZW |
250 | }; |
251 | dma-channel@80 { | |
8939700e | 252 | compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; |
3f346935 | 253 | reg = <0x80 0x80>; |
8939700e KG |
254 | interrupt-parent = <&ipic>; |
255 | interrupts = <0x47 8>; | |
3f346935 ZW |
256 | }; |
257 | dma-channel@100 { | |
8939700e | 258 | compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; |
3f346935 | 259 | reg = <0x100 0x80>; |
8939700e KG |
260 | interrupt-parent = <&ipic>; |
261 | interrupts = <0x47 8>; | |
3f346935 ZW |
262 | }; |
263 | dma-channel@180 { | |
8939700e | 264 | compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; |
3f346935 | 265 | reg = <0x180 0x28>; |
8939700e KG |
266 | interrupt-parent = <&ipic>; |
267 | interrupts = <0x47 8>; | |
3f346935 ZW |
268 | }; |
269 | }; | |
270 | ||
dee80553 | 271 | crypto@30000 { |
3fd44736 KP |
272 | compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", |
273 | "fsl,sec2.1", "fsl,sec2.0"; | |
dee80553 KG |
274 | reg = <0x30000 0x10000>; |
275 | interrupts = <11 0x8>; | |
276 | interrupt-parent = <&ipic>; | |
3fd44736 KP |
277 | fsl,num-channels = <4>; |
278 | fsl,channel-fifo-len = <24>; | |
279 | fsl,exec-units-mask = <0x9fe>; | |
280 | fsl,descriptor-types-mask = <0x3ab0ebf>; | |
dee80553 KG |
281 | }; |
282 | ||
283 | sdhc@2e000 { | |
284 | model = "eSDHC"; | |
285 | compatible = "fsl,esdhc"; | |
286 | reg = <0x2e000 0x1000>; | |
287 | interrupts = <42 0x8>; | |
288 | interrupt-parent = <&ipic>; | |
289 | }; | |
290 | ||
291 | sata@18000 { | |
292 | compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; | |
293 | reg = <0x18000 0x1000>; | |
294 | interrupts = <44 0x8>; | |
295 | interrupt-parent = <&ipic>; | |
296 | }; | |
297 | ||
298 | sata@19000 { | |
299 | compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; | |
300 | reg = <0x19000 0x1000>; | |
301 | interrupts = <45 0x8>; | |
302 | interrupt-parent = <&ipic>; | |
303 | }; | |
304 | ||
5761bc5d LY |
305 | /* IPIC |
306 | * interrupts cell = <intr #, sense> | |
307 | * sense values match linux IORESOURCE_IRQ_* defines: | |
308 | * sense == 8: Level, low assertion | |
309 | * sense == 2: Edge, high-to-low change | |
310 | */ | |
311 | ipic: pic@700 { | |
312 | compatible = "fsl,ipic"; | |
313 | interrupt-controller; | |
314 | #address-cells = <0>; | |
315 | #interrupt-cells = <2>; | |
316 | reg = <0x700 0x100>; | |
317 | }; | |
318 | }; | |
319 | ||
320 | pci0: pci@e0008500 { | |
321 | cell-index = <0>; | |
322 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
323 | interrupt-map = < | |
324 | ||
325 | /* IDSEL 0x11 */ | |
cda13dd1 PG |
326 | 0x8800 0x0 0x0 0x1 &ipic 20 0x8 |
327 | 0x8800 0x0 0x0 0x2 &ipic 21 0x8 | |
328 | 0x8800 0x0 0x0 0x3 &ipic 22 0x8 | |
329 | 0x8800 0x0 0x0 0x4 &ipic 23 0x8 | |
5761bc5d LY |
330 | |
331 | /* IDSEL 0x12 */ | |
cda13dd1 PG |
332 | 0x9000 0x0 0x0 0x1 &ipic 22 0x8 |
333 | 0x9000 0x0 0x0 0x2 &ipic 23 0x8 | |
334 | 0x9000 0x0 0x0 0x3 &ipic 20 0x8 | |
335 | 0x9000 0x0 0x0 0x4 &ipic 21 0x8 | |
5761bc5d LY |
336 | |
337 | /* IDSEL 0x13 */ | |
cda13dd1 PG |
338 | 0x9800 0x0 0x0 0x1 &ipic 23 0x8 |
339 | 0x9800 0x0 0x0 0x2 &ipic 20 0x8 | |
340 | 0x9800 0x0 0x0 0x3 &ipic 21 0x8 | |
341 | 0x9800 0x0 0x0 0x4 &ipic 22 0x8 | |
5761bc5d LY |
342 | |
343 | /* IDSEL 0x15 */ | |
cda13dd1 PG |
344 | 0xa800 0x0 0x0 0x1 &ipic 20 0x8 |
345 | 0xa800 0x0 0x0 0x2 &ipic 21 0x8 | |
346 | 0xa800 0x0 0x0 0x3 &ipic 22 0x8 | |
347 | 0xa800 0x0 0x0 0x4 &ipic 23 0x8 | |
5761bc5d LY |
348 | |
349 | /* IDSEL 0x16 */ | |
cda13dd1 PG |
350 | 0xb000 0x0 0x0 0x1 &ipic 23 0x8 |
351 | 0xb000 0x0 0x0 0x2 &ipic 20 0x8 | |
352 | 0xb000 0x0 0x0 0x3 &ipic 21 0x8 | |
353 | 0xb000 0x0 0x0 0x4 &ipic 22 0x8 | |
5761bc5d LY |
354 | |
355 | /* IDSEL 0x17 */ | |
cda13dd1 PG |
356 | 0xb800 0x0 0x0 0x1 &ipic 22 0x8 |
357 | 0xb800 0x0 0x0 0x2 &ipic 23 0x8 | |
358 | 0xb800 0x0 0x0 0x3 &ipic 20 0x8 | |
359 | 0xb800 0x0 0x0 0x4 &ipic 21 0x8 | |
5761bc5d LY |
360 | |
361 | /* IDSEL 0x18 */ | |
cda13dd1 PG |
362 | 0xc000 0x0 0x0 0x1 &ipic 21 0x8 |
363 | 0xc000 0x0 0x0 0x2 &ipic 22 0x8 | |
364 | 0xc000 0x0 0x0 0x3 &ipic 23 0x8 | |
365 | 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; | |
366 | interrupt-parent = <&ipic>; | |
367 | interrupts = <66 0x8>; | |
368 | bus-range = <0x0 0x0>; | |
5761bc5d LY |
369 | ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 |
370 | 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 | |
371 | 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; | |
372 | clock-frequency = <0>; | |
373 | #interrupt-cells = <1>; | |
374 | #size-cells = <2>; | |
375 | #address-cells = <3>; | |
376 | reg = <0xe0008500 0x100>; | |
377 | compatible = "fsl,mpc8349-pci"; | |
378 | device_type = "pci"; | |
379 | }; | |
380 | }; |