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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
bbeb3f4c SR |
2 | #ifndef _ASM_POWERPC_MPIC_H |
3 | #define _ASM_POWERPC_MPIC_H | |
88ced031 | 4 | #ifdef __KERNEL__ |
bbeb3f4c | 5 | |
14cf11af | 6 | #include <linux/irq.h> |
fbf0274e | 7 | #include <asm/dcr.h> |
25235f71 | 8 | #include <asm/msi_bitmap.h> |
14cf11af PM |
9 | |
10 | /* | |
11 | * Global registers | |
12 | */ | |
13 | ||
14 | #define MPIC_GREG_BASE 0x01000 | |
15 | ||
16 | #define MPIC_GREG_FEATURE_0 0x00000 | |
17 | #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000 | |
18 | #define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16 | |
19 | #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00 | |
20 | #define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8 | |
21 | #define MPIC_GREG_FEATURE_VERSION_MASK 0xff | |
22 | #define MPIC_GREG_FEATURE_1 0x00010 | |
23 | #define MPIC_GREG_GLOBAL_CONF_0 0x00020 | |
24 | #define MPIC_GREG_GCONF_RESET 0x80000000 | |
d91e4ea7 KG |
25 | /* On the FSL mpic implementations the Mode field is expand to be |
26 | * 2 bits wide: | |
27 | * 0b00 = pass through (interrupts routed to IRQ0) | |
28 | * 0b01 = Mixed mode | |
29 | * 0b10 = reserved | |
30 | * 0b11 = External proxy / coreint | |
31 | */ | |
32 | #define MPIC_GREG_GCONF_COREINT 0x60000000 | |
14cf11af | 33 | #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 |
d87bf3be | 34 | #define MPIC_GREG_GCONF_NO_BIAS 0x10000000 |
14cf11af | 35 | #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff |
f365355e | 36 | #define MPIC_GREG_GCONF_MCK 0x08000000 |
14cf11af PM |
37 | #define MPIC_GREG_GLOBAL_CONF_1 0x00030 |
38 | #define MPIC_GREG_VENDOR_0 0x00040 | |
39 | #define MPIC_GREG_VENDOR_1 0x00050 | |
40 | #define MPIC_GREG_VENDOR_2 0x00060 | |
41 | #define MPIC_GREG_VENDOR_3 0x00070 | |
42 | #define MPIC_GREG_VENDOR_ID 0x00080 | |
43 | #define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000 | |
44 | #define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16 | |
45 | #define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 | |
46 | #define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8 | |
47 | #define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff | |
48 | #define MPIC_GREG_PROCESSOR_INIT 0x00090 | |
49 | #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0 | |
50 | #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 | |
51 | #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 | |
52 | #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 | |
7233593b | 53 | #define MPIC_GREG_IPI_STRIDE 0x10 |
14cf11af PM |
54 | #define MPIC_GREG_SPURIOUS 0x000e0 |
55 | #define MPIC_GREG_TIMER_FREQ 0x000f0 | |
56 | ||
57 | /* | |
58 | * | |
59 | * Timer registers | |
60 | */ | |
61 | #define MPIC_TIMER_BASE 0x01100 | |
62 | #define MPIC_TIMER_STRIDE 0x40 | |
03bcb7e3 | 63 | #define MPIC_TIMER_GROUP_STRIDE 0x1000 |
14cf11af PM |
64 | |
65 | #define MPIC_TIMER_CURRENT_CNT 0x00000 | |
66 | #define MPIC_TIMER_BASE_CNT 0x00010 | |
67 | #define MPIC_TIMER_VECTOR_PRI 0x00020 | |
68 | #define MPIC_TIMER_DESTINATION 0x00030 | |
69 | ||
70 | /* | |
71 | * Per-Processor registers | |
72 | */ | |
73 | ||
74 | #define MPIC_CPU_THISBASE 0x00000 | |
75 | #define MPIC_CPU_BASE 0x20000 | |
76 | #define MPIC_CPU_STRIDE 0x01000 | |
77 | ||
78 | #define MPIC_CPU_IPI_DISPATCH_0 0x00040 | |
79 | #define MPIC_CPU_IPI_DISPATCH_1 0x00050 | |
80 | #define MPIC_CPU_IPI_DISPATCH_2 0x00060 | |
81 | #define MPIC_CPU_IPI_DISPATCH_3 0x00070 | |
7233593b | 82 | #define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010 |
14cf11af PM |
83 | #define MPIC_CPU_CURRENT_TASK_PRI 0x00080 |
84 | #define MPIC_CPU_TASKPRI_MASK 0x0000000f | |
85 | #define MPIC_CPU_WHOAMI 0x00090 | |
86 | #define MPIC_CPU_WHOAMI_MASK 0x0000001f | |
87 | #define MPIC_CPU_INTACK 0x000a0 | |
88 | #define MPIC_CPU_EOI 0x000b0 | |
f365355e | 89 | #define MPIC_CPU_MCACK 0x000c0 |
14cf11af PM |
90 | |
91 | /* | |
92 | * Per-source registers | |
93 | */ | |
94 | ||
95 | #define MPIC_IRQ_BASE 0x10000 | |
96 | #define MPIC_IRQ_STRIDE 0x00020 | |
97 | #define MPIC_IRQ_VECTOR_PRI 0x00000 | |
98 | #define MPIC_VECPRI_MASK 0x80000000 | |
99 | #define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */ | |
100 | #define MPIC_VECPRI_PRIORITY_MASK 0x000f0000 | |
101 | #define MPIC_VECPRI_PRIORITY_SHIFT 16 | |
102 | #define MPIC_VECPRI_VECTOR_MASK 0x000007ff | |
103 | #define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000 | |
104 | #define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000 | |
105 | #define MPIC_VECPRI_POLARITY_MASK 0x00800000 | |
106 | #define MPIC_VECPRI_SENSE_LEVEL 0x00400000 | |
107 | #define MPIC_VECPRI_SENSE_EDGE 0x00000000 | |
108 | #define MPIC_VECPRI_SENSE_MASK 0x00400000 | |
109 | #define MPIC_IRQ_DESTINATION 0x00010 | |
110 | ||
03bcb7e3 VS |
111 | #define MPIC_FSL_BRR1 0x00000 |
112 | #define MPIC_FSL_BRR1_VER 0x0000ffff | |
113 | ||
14cf11af PM |
114 | #define MPIC_MAX_IRQ_SOURCES 2048 |
115 | #define MPIC_MAX_CPUS 32 | |
116 | #define MPIC_MAX_ISU 32 | |
117 | ||
0a408164 VS |
118 | #define MPIC_MAX_ERR 32 |
119 | #define MPIC_FSL_ERR_INT 16 | |
120 | ||
7233593b ZR |
121 | /* |
122 | * Tsi108 implementation of MPIC has many differences from the original one | |
123 | */ | |
124 | ||
125 | /* | |
126 | * Global registers | |
127 | */ | |
128 | ||
129 | #define TSI108_GREG_BASE 0x00000 | |
130 | #define TSI108_GREG_FEATURE_0 0x00000 | |
131 | #define TSI108_GREG_GLOBAL_CONF_0 0x00004 | |
132 | #define TSI108_GREG_VENDOR_ID 0x0000c | |
133 | #define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */ | |
134 | #define TSI108_GREG_IPI_STRIDE 0x0c | |
135 | #define TSI108_GREG_SPURIOUS 0x00010 | |
136 | #define TSI108_GREG_TIMER_FREQ 0x00014 | |
137 | ||
138 | /* | |
139 | * Timer registers | |
140 | */ | |
141 | #define TSI108_TIMER_BASE 0x0030 | |
142 | #define TSI108_TIMER_STRIDE 0x10 | |
143 | #define TSI108_TIMER_CURRENT_CNT 0x00000 | |
144 | #define TSI108_TIMER_BASE_CNT 0x00004 | |
145 | #define TSI108_TIMER_VECTOR_PRI 0x00008 | |
146 | #define TSI108_TIMER_DESTINATION 0x0000c | |
147 | ||
148 | /* | |
149 | * Per-Processor registers | |
150 | */ | |
151 | #define TSI108_CPU_BASE 0x00300 | |
152 | #define TSI108_CPU_STRIDE 0x00040 | |
153 | #define TSI108_CPU_IPI_DISPATCH_0 0x00200 | |
154 | #define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000 | |
155 | #define TSI108_CPU_CURRENT_TASK_PRI 0x00000 | |
156 | #define TSI108_CPU_WHOAMI 0xffffffff | |
157 | #define TSI108_CPU_INTACK 0x00004 | |
158 | #define TSI108_CPU_EOI 0x00008 | |
f365355e | 159 | #define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */ |
7233593b ZR |
160 | |
161 | /* | |
162 | * Per-source registers | |
163 | */ | |
164 | #define TSI108_IRQ_BASE 0x00100 | |
165 | #define TSI108_IRQ_STRIDE 0x00008 | |
166 | #define TSI108_IRQ_VECTOR_PRI 0x00000 | |
167 | #define TSI108_VECPRI_VECTOR_MASK 0x000000ff | |
168 | #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000 | |
169 | #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000 | |
170 | #define TSI108_VECPRI_SENSE_LEVEL 0x02000000 | |
171 | #define TSI108_VECPRI_SENSE_EDGE 0x00000000 | |
172 | #define TSI108_VECPRI_POLARITY_MASK 0x01000000 | |
173 | #define TSI108_VECPRI_SENSE_MASK 0x02000000 | |
174 | #define TSI108_IRQ_DESTINATION 0x00004 | |
175 | ||
176 | /* weird mpic register indices and mask bits in the HW info array */ | |
177 | enum { | |
178 | MPIC_IDX_GREG_BASE = 0, | |
179 | MPIC_IDX_GREG_FEATURE_0, | |
180 | MPIC_IDX_GREG_GLOBAL_CONF_0, | |
181 | MPIC_IDX_GREG_VENDOR_ID, | |
182 | MPIC_IDX_GREG_IPI_VECTOR_PRI_0, | |
183 | MPIC_IDX_GREG_IPI_STRIDE, | |
184 | MPIC_IDX_GREG_SPURIOUS, | |
185 | MPIC_IDX_GREG_TIMER_FREQ, | |
186 | ||
187 | MPIC_IDX_TIMER_BASE, | |
188 | MPIC_IDX_TIMER_STRIDE, | |
189 | MPIC_IDX_TIMER_CURRENT_CNT, | |
190 | MPIC_IDX_TIMER_BASE_CNT, | |
191 | MPIC_IDX_TIMER_VECTOR_PRI, | |
192 | MPIC_IDX_TIMER_DESTINATION, | |
193 | ||
194 | MPIC_IDX_CPU_BASE, | |
195 | MPIC_IDX_CPU_STRIDE, | |
196 | MPIC_IDX_CPU_IPI_DISPATCH_0, | |
197 | MPIC_IDX_CPU_IPI_DISPATCH_STRIDE, | |
198 | MPIC_IDX_CPU_CURRENT_TASK_PRI, | |
199 | MPIC_IDX_CPU_WHOAMI, | |
200 | MPIC_IDX_CPU_INTACK, | |
201 | MPIC_IDX_CPU_EOI, | |
f365355e | 202 | MPIC_IDX_CPU_MCACK, |
7233593b ZR |
203 | |
204 | MPIC_IDX_IRQ_BASE, | |
205 | MPIC_IDX_IRQ_STRIDE, | |
206 | MPIC_IDX_IRQ_VECTOR_PRI, | |
207 | ||
208 | MPIC_IDX_VECPRI_VECTOR_MASK, | |
209 | MPIC_IDX_VECPRI_POLARITY_POSITIVE, | |
210 | MPIC_IDX_VECPRI_POLARITY_NEGATIVE, | |
211 | MPIC_IDX_VECPRI_SENSE_LEVEL, | |
212 | MPIC_IDX_VECPRI_SENSE_EDGE, | |
213 | MPIC_IDX_VECPRI_POLARITY_MASK, | |
214 | MPIC_IDX_VECPRI_SENSE_MASK, | |
215 | MPIC_IDX_IRQ_DESTINATION, | |
216 | MPIC_IDX_END | |
217 | }; | |
218 | ||
219 | ||
6cfef5b2 | 220 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
221 | /* Fixup table entry */ |
222 | struct mpic_irq_fixup | |
223 | { | |
224 | u8 __iomem *base; | |
1beb6a7d | 225 | u8 __iomem *applebase; |
c4b22f26 | 226 | u32 data; |
1beb6a7d | 227 | unsigned int index; |
14cf11af | 228 | }; |
6cfef5b2 | 229 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af PM |
230 | |
231 | ||
fbf0274e BH |
232 | enum mpic_reg_type { |
233 | mpic_access_mmio_le, | |
234 | mpic_access_mmio_be, | |
235 | #ifdef CONFIG_PPC_DCR | |
236 | mpic_access_dcr | |
237 | #endif | |
238 | }; | |
239 | ||
240 | struct mpic_reg_bank { | |
241 | u32 __iomem *base; | |
242 | #ifdef CONFIG_PPC_DCR | |
243 | dcr_host_t dhost; | |
fbf0274e BH |
244 | #endif /* CONFIG_PPC_DCR */ |
245 | }; | |
246 | ||
3669e930 JB |
247 | struct mpic_irq_save { |
248 | u32 vecprio, | |
249 | dest; | |
250 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
251 | u32 fixup_data; | |
252 | #endif | |
253 | }; | |
254 | ||
14cf11af PM |
255 | /* The instance data of a given MPIC */ |
256 | struct mpic | |
257 | { | |
c51242e7 KM |
258 | /* The OpenFirmware dt node for this MPIC */ |
259 | struct device_node *node; | |
260 | ||
0ebfff14 | 261 | /* The remapper for this MPIC */ |
bae1d8f1 | 262 | struct irq_domain *irqhost; |
0ebfff14 | 263 | |
14cf11af | 264 | /* The "linux" controller struct */ |
b9e5b4e6 | 265 | struct irq_chip hc_irq; |
6cfef5b2 | 266 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 BH |
267 | struct irq_chip hc_ht_irq; |
268 | #endif | |
14cf11af | 269 | #ifdef CONFIG_SMP |
b9e5b4e6 | 270 | struct irq_chip hc_ipi; |
14cf11af | 271 | #endif |
ea94187f | 272 | struct irq_chip hc_tm; |
0a408164 | 273 | struct irq_chip hc_err; |
14cf11af PM |
274 | const char *name; |
275 | /* Flags */ | |
276 | unsigned int flags; | |
277 | /* How many irq sources in a given ISU */ | |
278 | unsigned int isu_size; | |
279 | unsigned int isu_shift; | |
280 | unsigned int isu_mask; | |
14cf11af PM |
281 | /* Number of sources */ |
282 | unsigned int num_sources; | |
14cf11af | 283 | |
7df2457d OJ |
284 | /* vector numbers used for internal sources (ipi/timers) */ |
285 | unsigned int ipi_vecs[4]; | |
ea94187f | 286 | unsigned int timer_vecs[8]; |
0a408164 VS |
287 | /* vector numbers used for FSL MPIC error interrupts */ |
288 | unsigned int err_int_vecs[MPIC_MAX_ERR]; | |
7df2457d OJ |
289 | |
290 | /* Spurious vector to program into unused sources */ | |
291 | unsigned int spurious_vec; | |
292 | ||
6cfef5b2 | 293 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
294 | /* The fixup table */ |
295 | struct mpic_irq_fixup *fixups; | |
203041ad | 296 | raw_spinlock_t fixup_lock; |
14cf11af PM |
297 | #endif |
298 | ||
fbf0274e BH |
299 | /* Register access method */ |
300 | enum mpic_reg_type reg_type; | |
301 | ||
e7a98675 KM |
302 | /* The physical base address of the MPIC */ |
303 | phys_addr_t paddr; | |
304 | ||
14cf11af | 305 | /* The various ioremap'ed bases */ |
03bcb7e3 | 306 | struct mpic_reg_bank thiscpuregs; |
fbf0274e BH |
307 | struct mpic_reg_bank gregs; |
308 | struct mpic_reg_bank tmregs; | |
309 | struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS]; | |
310 | struct mpic_reg_bank isus[MPIC_MAX_ISU]; | |
311 | ||
0a408164 VS |
312 | /* ioremap'ed base for error interrupt registers */ |
313 | u32 __iomem *err_regs; | |
314 | ||
7fd72186 BH |
315 | /* Protected sources */ |
316 | unsigned long *protected; | |
317 | ||
7233593b ZR |
318 | #ifdef CONFIG_MPIC_WEIRD |
319 | /* Pointer to HW info array */ | |
320 | u32 *hw_set; | |
321 | #endif | |
322 | ||
a7de7c74 | 323 | #ifdef CONFIG_PCI_MSI |
25235f71 | 324 | struct msi_bitmap msi_bitmap; |
a7de7c74 ME |
325 | #endif |
326 | ||
0d72ba93 OJ |
327 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
328 | u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES]; | |
329 | #endif | |
330 | ||
14cf11af PM |
331 | /* link */ |
332 | struct mpic *next; | |
3669e930 | 333 | |
3669e930 JB |
334 | #ifdef CONFIG_PM |
335 | struct mpic_irq_save *save_data; | |
336 | #endif | |
14cf11af PM |
337 | }; |
338 | ||
9e6f31a9 D |
339 | extern struct bus_type mpic_subsys; |
340 | ||
7233593b ZR |
341 | /* |
342 | * MPIC flags (passed to mpic_alloc) | |
343 | * | |
344 | * The top 4 bits contain an MPIC bhw id that is used to index the | |
345 | * register offsets and some masks when CONFIG_MPIC_WEIRD is set. | |
346 | * Note setting any ID (leaving those bits to 0) means standard MPIC | |
347 | */ | |
348 | ||
be8bec56 KM |
349 | /* |
350 | * This is a secondary ("chained") controller; it only uses the CPU0 | |
351 | * registers. Primary controllers have IPIs and affinity control. | |
14cf11af | 352 | */ |
be8bec56 | 353 | #define MPIC_SECONDARY 0x00000001 |
7233593b | 354 | |
14cf11af PM |
355 | /* Set this for a big-endian MPIC */ |
356 | #define MPIC_BIG_ENDIAN 0x00000002 | |
357 | /* Broken U3 MPIC */ | |
6cfef5b2 | 358 | #define MPIC_U3_HT_IRQS 0x00000004 |
14cf11af PM |
359 | /* Broken IPI registers (autodetected) */ |
360 | #define MPIC_BROKEN_IPI 0x00000008 | |
7233593b ZR |
361 | /* Spurious vector requires EOI */ |
362 | #define MPIC_SPV_EOI 0x00000020 | |
363 | /* No passthrough disable */ | |
364 | #define MPIC_NO_PTHROU_DIS 0x00000040 | |
fbf0274e BH |
365 | /* DCR based MPIC */ |
366 | #define MPIC_USES_DCR 0x00000080 | |
7df2457d OJ |
367 | /* MPIC has 11-bit vector fields (or larger) */ |
368 | #define MPIC_LARGE_VECTORS 0x00000100 | |
f365355e OJ |
369 | /* Enable delivery of prio 15 interrupts as MCK instead of EE */ |
370 | #define MPIC_ENABLE_MCK 0x00000200 | |
d87bf3be OJ |
371 | /* Disable bias among target selection, spread interrupts evenly */ |
372 | #define MPIC_NO_BIAS 0x00000400 | |
3c10c9c4 KG |
373 | /* Destination only supports a single CPU at a time */ |
374 | #define MPIC_SINGLE_DEST_CPU 0x00001000 | |
d91e4ea7 KG |
375 | /* Enable CoreInt delivery of interrupts */ |
376 | #define MPIC_ENABLE_COREINT 0x00002000 | |
e55d7f73 | 377 | /* Do not reset the MPIC during initialization */ |
dfec2202 | 378 | #define MPIC_NO_RESET 0x00004000 |
22d168ce SW |
379 | /* Freescale MPIC (compatible includes "fsl,mpic") */ |
380 | #define MPIC_FSL 0x00008000 | |
0a408164 VS |
381 | /* Freescale MPIC supports EIMR (error interrupt mask register). |
382 | * This flag is set for MPIC version >= 4.1 (version determined | |
383 | * from the BRR1 register). | |
384 | */ | |
385 | #define MPIC_FSL_HAS_EIMR 0x00010000 | |
7233593b ZR |
386 | |
387 | /* MPIC HW modification ID */ | |
388 | #define MPIC_REGSET_MASK 0xf0000000 | |
389 | #define MPIC_REGSET(val) (((val) & 0xf ) << 28) | |
390 | #define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf) | |
391 | ||
392 | #define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */ | |
393 | #define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */ | |
14cf11af | 394 | |
807d38b7 | 395 | /* Get the version of primary MPIC */ |
0f99153d | 396 | #ifdef CONFIG_MPIC |
807d38b7 | 397 | extern u32 fsl_mpic_primary_get_version(void); |
0f99153d CL |
398 | #else |
399 | static inline u32 fsl_mpic_primary_get_version(void) | |
400 | { | |
401 | return 0; | |
402 | } | |
403 | #endif | |
807d38b7 | 404 | |
14cf11af PM |
405 | /* Allocate the controller structure and setup the linux irq descs |
406 | * for the range if interrupts passed in. No HW initialization is | |
407 | * actually performed. | |
408 | * | |
409 | * @phys_addr: physial base address of the MPIC | |
410 | * @flags: flags, see constants above | |
411 | * @isu_size: number of interrupts in an ISU. Use 0 to use a | |
412 | * standard ISU-less setup (aka powermac) | |
413 | * @irq_offset: first irq number to assign to this mpic | |
414 | * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0 | |
415 | * to match the number of sources | |
416 | * @ipi_offset: first irq number to assign to this mpic IPI sources, | |
417 | * used only on primary mpic | |
418 | * @senses: array of sense values | |
419 | * @senses_num: number of entries in the array | |
420 | * | |
421 | * Note about the sense array. If none is passed, all interrupts are | |
6cfef5b2 | 422 | * setup to be level negative unless MPIC_U3_HT_IRQS is set in which |
14cf11af PM |
423 | * case they are edge positive (and the array is ignored anyway). |
424 | * The values in the array start at the first source of the MPIC, | |
425 | * that is senses[0] correspond to linux irq "irq_offset". | |
426 | */ | |
0ebfff14 | 427 | extern struct mpic *mpic_alloc(struct device_node *node, |
a959ff56 | 428 | phys_addr_t phys_addr, |
14cf11af PM |
429 | unsigned int flags, |
430 | unsigned int isu_size, | |
14cf11af | 431 | unsigned int irq_count, |
14cf11af PM |
432 | const char *name); |
433 | ||
434 | /* Assign ISUs, to call before mpic_init() | |
435 | * | |
436 | * @mpic: controller structure as returned by mpic_alloc() | |
437 | * @isu_num: ISU number | |
438 | * @phys_addr: physical address of the ISU | |
439 | */ | |
440 | extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 441 | phys_addr_t phys_addr); |
14cf11af | 442 | |
0ebfff14 | 443 | |
14cf11af PM |
444 | /* Initialize the controller. After this has been called, none of the above |
445 | * should be called again for this mpic | |
446 | */ | |
447 | extern void mpic_init(struct mpic *mpic); | |
448 | ||
14cf11af PM |
449 | /* |
450 | * All of the following functions must only be used after the | |
451 | * ISUs have been assigned and the controller fully initialized | |
452 | * with mpic_init() | |
453 | */ | |
454 | ||
455 | ||
06a901c5 | 456 | /* Change the priority of an interrupt. Default is 8 for irqs and |
14cf11af PM |
457 | * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the |
458 | * IPI number is then the offset'ed (linux irq number mapped to the IPI) | |
459 | */ | |
460 | extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri); | |
14cf11af PM |
461 | |
462 | /* Setup a non-boot CPU */ | |
463 | extern void mpic_setup_this_cpu(void); | |
464 | ||
465 | /* Clean up for kexec (or cpu offline or ...) */ | |
466 | extern void mpic_teardown_this_cpu(int secondary); | |
467 | ||
468 | /* Get the current cpu priority for this cpu (0..15) */ | |
469 | extern int mpic_cpu_get_priority(void); | |
470 | ||
471 | /* Set the current cpu priority for this cpu */ | |
472 | extern void mpic_cpu_set_priority(int prio); | |
473 | ||
474 | /* Request IPIs on primary mpic */ | |
475 | extern void mpic_request_ipis(void); | |
476 | ||
a9c59264 PM |
477 | /* Send a message (IPI) to a given target (cpu number or MSG_*) */ |
478 | void smp_mpic_message_pass(int target, int msg); | |
479 | ||
f365355e | 480 | /* Unmask a specific virq */ |
835c0553 | 481 | extern void mpic_unmask_irq(struct irq_data *d); |
f365355e | 482 | /* Mask a specific virq */ |
835c0553 | 483 | extern void mpic_mask_irq(struct irq_data *d); |
f365355e | 484 | /* EOI a specific virq */ |
835c0553 | 485 | extern void mpic_end_irq(struct irq_data *d); |
f365355e | 486 | |
14cf11af | 487 | /* Fetch interrupt from a given mpic */ |
35a84c2f | 488 | extern unsigned int mpic_get_one_irq(struct mpic *mpic); |
f365355e | 489 | /* This one gets from the primary mpic */ |
35a84c2f | 490 | extern unsigned int mpic_get_irq(void); |
d91e4ea7 KG |
491 | /* This one gets from the primary mpic via CoreInt*/ |
492 | extern unsigned int mpic_get_coreint_irq(void); | |
f365355e OJ |
493 | /* Fetch Machine Check interrupt from primary mpic */ |
494 | extern unsigned int mpic_get_mcirq(void); | |
14cf11af | 495 | |
88ced031 | 496 | #endif /* __KERNEL__ */ |
bbeb3f4c | 497 | #endif /* _ASM_POWERPC_MPIC_H */ |