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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
7cba160a | 18 | #include <asm/cpuidle.h> |
da2bc464 | 19 | #include <asm/head-64.h> |
8aa34ab8 | 20 | |
0ebc4cda | 21 | /* |
57f26649 NP |
22 | * There are a few constraints to be concerned with. |
23 | * - Real mode exceptions code/data must be located at their physical location. | |
24 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
25 | * - Fixed location code must not call directly beyond the __end_interrupts | |
26 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
27 | * must be used. | |
28 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
29 | * virtual 0xc00... | |
30 | * - Conditional branch targets must be within +/-32K of caller. | |
31 | * | |
32 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
33 | * therefore don't have to run in physically located code or rfid to | |
34 | * virtual mode kernel code. However on relocatable kernels they do have | |
35 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
36 | * the exception vectors) may be located elsewhere. | |
37 | * | |
38 | * Virtual exceptions correspond with physical, except their entry points | |
39 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
40 | * offset applied. Virtual exceptions are enabled with the Alternate | |
41 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
42 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
43 | * cause exceptions to be delivered in real mode. | |
44 | * | |
45 | * It's impossible to receive interrupts below 0x300 via AIL. | |
46 | * | |
47 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
48 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
49 | * | |
50 | * | |
0ebc4cda BH |
51 | * We layout physical memory as follows: |
52 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
53 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
54 | * 0x1900 - 0x3fff : Real mode trampolines | |
55 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
56 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 57 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
58 | * 0x8000 - .... : Common interrupt handlers, remaining early |
59 | * setup code, rest of kernel. | |
60 | */ | |
61 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
62 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
63 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
64 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
65 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
66 | /* | |
67 | * Data area reserved for FWNMI option. | |
68 | * This address (0x7000) is fixed by the RPA. | |
69 | * pseries and powernv need to keep the whole page from | |
70 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 71 | */ |
57f26649 NP |
72 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
73 | OPEN_TEXT_SECTION(0x8000) | |
74 | #else | |
75 | OPEN_TEXT_SECTION(0x7000) | |
76 | #endif | |
77 | ||
78 | USE_FIXED_SECTION(real_vectors) | |
79 | ||
80 | #define LOAD_SYSCALL_HANDLER(reg) \ | |
81 | ld reg,PACAKBASE(r13); \ | |
82 | ori reg,reg,(ABS_ADDR(system_call_common))@l; | |
83 | ||
742415d6 MN |
84 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ |
85 | #define SYSCALL_PSERIES_1 \ | |
86 | BEGIN_FTR_SECTION \ | |
87 | cmpdi r0,0x1ebe ; \ | |
88 | beq- 1f ; \ | |
89 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
90 | mr r9,r13 ; \ | |
91 | GET_PACA(r13) ; \ | |
92 | mfspr r11,SPRN_SRR0 ; \ | |
93 | 0: | |
94 | ||
95 | #define SYSCALL_PSERIES_2_RFID \ | |
96 | mfspr r12,SPRN_SRR1 ; \ | |
57f26649 | 97 | LOAD_SYSCALL_HANDLER(r10) ; \ |
742415d6 MN |
98 | mtspr SPRN_SRR0,r10 ; \ |
99 | ld r10,PACAKMSR(r13) ; \ | |
100 | mtspr SPRN_SRR1,r10 ; \ | |
101 | rfid ; \ | |
102 | b . ; /* prevent speculative execution */ | |
103 | ||
104 | #define SYSCALL_PSERIES_3 \ | |
105 | /* Fast LE/BE switch system call */ \ | |
106 | 1: mfspr r12,SPRN_SRR1 ; \ | |
107 | xori r12,r12,MSR_LE ; \ | |
108 | mtspr SPRN_SRR1,r12 ; \ | |
109 | rfid ; /* return to userspace */ \ | |
742415d6 MN |
110 | b . ; /* prevent speculative execution */ |
111 | ||
4700dfaf MN |
112 | #if defined(CONFIG_RELOCATABLE) |
113 | /* | |
05b05f28 AB |
114 | * We can't branch directly so we do it via the CTR which |
115 | * is volatile across system calls. | |
4700dfaf MN |
116 | */ |
117 | #define SYSCALL_PSERIES_2_DIRECT \ | |
57f26649 | 118 | LOAD_SYSCALL_HANDLER(r12) ; \ |
6a404806 | 119 | mtctr r12 ; \ |
4700dfaf | 120 | mfspr r12,SPRN_SRR1 ; \ |
18e3f56b NP |
121 | li r10,MSR_RI ; \ |
122 | mtmsrd r10,1 ; \ | |
6a404806 | 123 | bctr ; |
4700dfaf MN |
124 | #else |
125 | /* We can branch directly */ | |
126 | #define SYSCALL_PSERIES_2_DIRECT \ | |
127 | mfspr r12,SPRN_SRR1 ; \ | |
128 | li r10,MSR_RI ; \ | |
129 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
d20be433 | 130 | b system_call_common ; |
4700dfaf | 131 | #endif |
0ebc4cda | 132 | |
0ebc4cda BH |
133 | /* |
134 | * This is the start of the interrupt handlers for pSeries | |
135 | * This code runs with relocation off. | |
136 | * Code from here to __end_interrupts gets copied down to real | |
137 | * address 0x100 when we are running a relocatable kernel. | |
138 | * Therefore any relative branches in this section must only | |
139 | * branch to labels in this section. | |
140 | */ | |
0ebc4cda BH |
141 | .globl __start_interrupts |
142 | __start_interrupts: | |
143 | ||
da2bc464 | 144 | EXC_REAL_BEGIN(system_reset, 0x100, 0x200) |
948cf67c BH |
145 | SET_SCRATCH0(r13) |
146 | #ifdef CONFIG_PPC_P7_NAP | |
147 | BEGIN_FTR_SECTION | |
148 | /* Running native on arch 2.06 or later, check if we are | |
77b54e9f | 149 | * waking up from nap/sleep/winkle. |
948cf67c BH |
150 | */ |
151 | mfspr r13,SPRN_SRR1 | |
371fefd6 PM |
152 | rlwinm. r13,r13,47-31,30,31 |
153 | beq 9f | |
154 | ||
7cba160a | 155 | cmpwi cr3,r13,2 |
371fefd6 | 156 | GET_PACA(r13) |
5fa6b6bd | 157 | bl pnv_restore_hyp_resource |
77b54e9f | 158 | |
7cba160a SP |
159 | li r0,PNV_THREAD_RUNNING |
160 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ | |
371fefd6 | 161 | |
3a167bea | 162 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
f0888f70 PM |
163 | li r0,KVM_HWTHREAD_IN_KERNEL |
164 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
165 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
166 | sync | |
167 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
168 | cmpwi r0,0 | |
169 | beq 1f | |
371fefd6 PM |
170 | b kvm_start_guest |
171 | 1: | |
172 | #endif | |
173 | ||
56548fc0 PM |
174 | /* Return SRR1 from power7_nap() */ |
175 | mfspr r3,SPRN_SRR1 | |
17065671 | 176 | blt cr3,2f |
5fa6b6bd SP |
177 | b pnv_wakeup_loss |
178 | 2: b pnv_wakeup_noloss | |
aca79d2b | 179 | |
371fefd6 | 180 | 9: |
969391c5 | 181 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
948cf67c | 182 | #endif /* CONFIG_PPC_P7_NAP */ |
b01c8b54 PM |
183 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
184 | NOTEST, 0x100) | |
da2bc464 | 185 | EXC_REAL_END(system_reset, 0x100, 0x200) |
582baf44 NP |
186 | EXC_VIRT_NONE(0x4100, 0x4200) |
187 | EXC_COMMON(system_reset_common, 0x100, system_reset_exception) | |
188 | ||
189 | #ifdef CONFIG_PPC_PSERIES | |
190 | /* | |
191 | * Vectors for the FWNMI option. Share common code. | |
192 | */ | |
193 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
194 | SET_SCRATCH0(r13) /* save r13 */ | |
195 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, | |
196 | NOTEST, 0x100) | |
197 | #endif /* CONFIG_PPC_PSERIES */ | |
198 | ||
0ebc4cda | 199 | |
da2bc464 | 200 | EXC_REAL_BEGIN(machine_check, 0x200, 0x300) |
b01c8b54 PM |
201 | /* This is moved out of line as it can be patched by FW, but |
202 | * some code path might still want to branch into the original | |
203 | * vector | |
204 | */ | |
1707dd16 | 205 | SET_SCRATCH0(r13) /* save r13 */ |
bc14c491 MS |
206 | /* |
207 | * Running native on arch 2.06 or later, we may wakeup from winkle | |
208 | * inside machine check. If yes, then last bit of HSPGR0 would be set | |
209 | * to 1. Hence clear it unconditionally. | |
1c51089f | 210 | */ |
bc14c491 MS |
211 | GET_PACA(r13) |
212 | clrrdi r13,r13,1 | |
213 | SET_PACA(r13) | |
1707dd16 | 214 | EXCEPTION_PROLOG_0(PACA_EXMC) |
1e9b4507 | 215 | BEGIN_FTR_SECTION |
2513767d | 216 | b machine_check_powernv_early |
1e9b4507 | 217 | FTR_SECTION_ELSE |
1707dd16 | 218 | b machine_check_pSeries_0 |
1e9b4507 | 219 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
da2bc464 | 220 | EXC_REAL_END(machine_check, 0x200, 0x300) |
afcf0095 NP |
221 | EXC_VIRT_NONE(0x4200, 0x4300) |
222 | TRAMP_REAL_BEGIN(machine_check_powernv_early) | |
223 | BEGIN_FTR_SECTION | |
224 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) | |
225 | /* | |
226 | * Register contents: | |
227 | * R13 = PACA | |
228 | * R9 = CR | |
229 | * Original R9 to R13 is saved on PACA_EXMC | |
230 | * | |
231 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
232 | * the nested MCE upto level 4 to avoid stack overflow). | |
233 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
234 | * | |
235 | * We use paca->in_mce to check whether this is the first entry or | |
236 | * nested machine check. We increment paca->in_mce to track nested | |
237 | * machine checks. | |
238 | * | |
239 | * If this is the first entry then set stack pointer to | |
240 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
241 | * stack frame on mc_emergency stack. | |
242 | * | |
243 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
244 | * checkstop if we get another machine check exception before we do | |
245 | * rfid with MSR_ME=1. | |
246 | */ | |
247 | mr r11,r1 /* Save r1 */ | |
248 | lhz r10,PACA_IN_MCE(r13) | |
249 | cmpwi r10,0 /* Are we in nested machine check */ | |
250 | bne 0f /* Yes, we are. */ | |
251 | /* First machine check entry */ | |
252 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
253 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
254 | addi r10,r10,1 /* increment paca->in_mce */ | |
255 | sth r10,PACA_IN_MCE(r13) | |
256 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
257 | cmpwi r10,4 | |
258 | bgt 2f /* Check if we hit limit of 4 */ | |
259 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
260 | std r11,0(r1) /* make stack chain pointer */ | |
261 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
262 | std r11,_NIP(r1) | |
263 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
264 | std r11,_MSR(r1) | |
265 | mfspr r11,SPRN_DAR /* Save DAR */ | |
266 | std r11,_DAR(r1) | |
267 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
268 | std r11,_DSISR(r1) | |
269 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
270 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
271 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
272 | mfmsr r11 /* get MSR value */ | |
273 | ori r11,r11,MSR_ME /* turn on ME bit */ | |
274 | ori r11,r11,MSR_RI /* turn on RI bit */ | |
275 | LOAD_HANDLER(r12, machine_check_handle_early) | |
276 | 1: mtspr SPRN_SRR0,r12 | |
277 | mtspr SPRN_SRR1,r11 | |
278 | rfid | |
279 | b . /* prevent speculative execution */ | |
280 | 2: | |
281 | /* Stack overflow. Stay on emergency stack and panic. | |
282 | * Keep the ME bit off while panic-ing, so that if we hit | |
283 | * another machine check we checkstop. | |
284 | */ | |
285 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
286 | ld r11,PACAKMSR(r13) | |
287 | LOAD_HANDLER(r12, unrecover_mce) | |
288 | li r10,MSR_ME | |
289 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
290 | b 1b | |
291 | b . /* prevent speculative execution */ | |
292 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
293 | ||
294 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
295 | .globl machine_check_fwnmi | |
296 | machine_check_fwnmi: | |
297 | SET_SCRATCH0(r13) /* save r13 */ | |
298 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
299 | machine_check_pSeries_0: | |
300 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) | |
301 | /* | |
302 | * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the | |
303 | * difference that MSR_RI is not enabled, because PACA_EXMC is being | |
304 | * used, so nested machine check corrupts it. machine_check_common | |
305 | * enables MSR_RI. | |
306 | */ | |
307 | ld r10,PACAKMSR(r13) | |
308 | xori r10,r10,MSR_RI | |
309 | mfspr r11,SPRN_SRR0 | |
310 | LOAD_HANDLER(r12, machine_check_common) | |
311 | mtspr SPRN_SRR0,r12 | |
312 | mfspr r12,SPRN_SRR1 | |
313 | mtspr SPRN_SRR1,r10 | |
314 | rfid | |
315 | b . /* prevent speculative execution */ | |
316 | ||
317 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
318 | ||
319 | EXC_COMMON_BEGIN(machine_check_common) | |
320 | /* | |
321 | * Machine check is different because we use a different | |
322 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
323 | */ | |
324 | mfspr r10,SPRN_DAR | |
325 | std r10,PACA_EXMC+EX_DAR(r13) | |
326 | mfspr r10,SPRN_DSISR | |
327 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
328 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
329 | FINISH_NAP | |
330 | RECONCILE_IRQ_STATE(r10, r11) | |
331 | ld r3,PACA_EXMC+EX_DAR(r13) | |
332 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
333 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
334 | li r10,MSR_RI | |
335 | mtmsrd r10,1 | |
336 | std r3,_DAR(r1) | |
337 | std r4,_DSISR(r1) | |
338 | bl save_nvgprs | |
339 | addi r3,r1,STACK_FRAME_OVERHEAD | |
340 | bl machine_check_exception | |
341 | b ret_from_except | |
342 | ||
343 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
344 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
345 | li r0,MSR_RI; \ | |
346 | mfmsr r9; /* get MSR value */ \ | |
347 | andc r9,r9,r0; \ | |
348 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
349 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
350 | ld r9,_MSR(r1); \ | |
351 | mtspr SPRN_SRR1,r9; \ | |
352 | ld r3,_NIP(r1); \ | |
353 | mtspr SPRN_SRR0,r3; \ | |
354 | ld r9,_CTR(r1); \ | |
355 | mtctr r9; \ | |
356 | ld r9,_XER(r1); \ | |
357 | mtxer r9; \ | |
358 | ld r9,_LINK(r1); \ | |
359 | mtlr r9; \ | |
360 | REST_GPR(0, r1); \ | |
361 | REST_8GPRS(2, r1); \ | |
362 | REST_GPR(10, r1); \ | |
363 | ld r11,_CCR(r1); \ | |
364 | mtcr r11; \ | |
365 | /* Decrement paca->in_mce. */ \ | |
366 | lhz r12,PACA_IN_MCE(r13); \ | |
367 | subi r12,r12,1; \ | |
368 | sth r12,PACA_IN_MCE(r13); \ | |
369 | REST_GPR(11, r1); \ | |
370 | REST_2GPRS(12, r1); \ | |
371 | /* restore original r1. */ \ | |
372 | ld r1,GPR1(r1) | |
373 | ||
374 | /* | |
375 | * Handle machine check early in real mode. We come here with | |
376 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
377 | */ | |
378 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
379 | std r0,GPR0(r1) /* Save r0 */ | |
380 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
381 | bl save_nvgprs | |
382 | addi r3,r1,STACK_FRAME_OVERHEAD | |
383 | bl machine_check_early | |
384 | std r3,RESULT(r1) /* Save result */ | |
385 | ld r12,_MSR(r1) | |
386 | #ifdef CONFIG_PPC_P7_NAP | |
387 | /* | |
388 | * Check if thread was in power saving mode. We come here when any | |
389 | * of the following is true: | |
390 | * a. thread wasn't in power saving mode | |
391 | * b. thread was in power saving mode with no state loss, | |
392 | * supervisor state loss or hypervisor state loss. | |
393 | * | |
394 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
395 | */ | |
396 | rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ | |
397 | beq 4f /* No, it wasn;t */ | |
398 | /* Thread was in power saving mode. Go back to nap again. */ | |
399 | cmpwi r11,2 | |
400 | blt 3f | |
401 | /* Supervisor/Hypervisor state loss */ | |
402 | li r0,1 | |
403 | stb r0,PACA_NAPSTATELOST(r13) | |
404 | 3: bl machine_check_queue_event | |
405 | MACHINE_CHECK_HANDLER_WINDUP | |
406 | GET_PACA(r13) | |
407 | ld r1,PACAR1(r13) | |
408 | /* | |
409 | * Check what idle state this CPU was in and go back to same mode | |
410 | * again. | |
411 | */ | |
412 | lbz r3,PACA_THREAD_IDLE_STATE(r13) | |
413 | cmpwi r3,PNV_THREAD_NAP | |
414 | bgt 10f | |
415 | IDLE_STATE_ENTER_SEQ(PPC_NAP) | |
416 | /* No return */ | |
417 | 10: | |
418 | cmpwi r3,PNV_THREAD_SLEEP | |
419 | bgt 2f | |
420 | IDLE_STATE_ENTER_SEQ(PPC_SLEEP) | |
421 | /* No return */ | |
422 | ||
423 | 2: | |
424 | /* | |
425 | * Go back to winkle. Please note that this thread was woken up in | |
426 | * machine check from winkle and have not restored the per-subcore | |
427 | * state. Hence before going back to winkle, set last bit of HSPGR0 | |
428 | * to 1. This will make sure that if this thread gets woken up | |
429 | * again at reset vector 0x100 then it will get chance to restore | |
430 | * the subcore state. | |
431 | */ | |
432 | ori r13,r13,1 | |
433 | SET_PACA(r13) | |
434 | IDLE_STATE_ENTER_SEQ(PPC_WINKLE) | |
435 | /* No return */ | |
436 | 4: | |
437 | #endif | |
438 | /* | |
439 | * Check if we are coming from hypervisor userspace. If yes then we | |
440 | * continue in host kernel in V mode to deliver the MC event. | |
441 | */ | |
442 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
443 | beq 5f | |
444 | andi. r11,r12,MSR_PR /* See if coming from user. */ | |
445 | bne 9f /* continue in V mode if we are. */ | |
446 | ||
447 | 5: | |
448 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
449 | /* | |
450 | * We are coming from kernel context. Check if we are coming from | |
451 | * guest. if yes, then we can continue. We will fall through | |
452 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
453 | */ | |
454 | lbz r11,HSTATE_IN_GUEST(r13) | |
455 | cmpwi r11,0 /* Check if coming from guest */ | |
456 | bne 9f /* continue if we are. */ | |
457 | #endif | |
458 | /* | |
459 | * At this point we are not sure about what context we come from. | |
460 | * Queue up the MCE event and return from the interrupt. | |
461 | * But before that, check if this is an un-recoverable exception. | |
462 | * If yes, then stay on emergency stack and panic. | |
463 | */ | |
464 | andi. r11,r12,MSR_RI | |
465 | bne 2f | |
466 | 1: mfspr r11,SPRN_SRR0 | |
467 | LOAD_HANDLER(r10,unrecover_mce) | |
468 | mtspr SPRN_SRR0,r10 | |
469 | ld r10,PACAKMSR(r13) | |
470 | /* | |
471 | * We are going down. But there are chances that we might get hit by | |
472 | * another MCE during panic path and we may run into unstable state | |
473 | * with no way out. Hence, turn ME bit off while going down, so that | |
474 | * when another MCE is hit during panic path, system will checkstop | |
475 | * and hypervisor will get restarted cleanly by SP. | |
476 | */ | |
477 | li r3,MSR_ME | |
478 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
479 | mtspr SPRN_SRR1,r10 | |
480 | rfid | |
481 | b . | |
482 | 2: | |
483 | /* | |
484 | * Check if we have successfully handled/recovered from error, if not | |
485 | * then stay on emergency stack and panic. | |
486 | */ | |
487 | ld r3,RESULT(r1) /* Load result */ | |
488 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
489 | ||
490 | beq 1b /* if !handled then panic */ | |
491 | /* | |
492 | * Return from MC interrupt. | |
493 | * Queue up the MCE event so that we can log it later, while | |
494 | * returning from kernel or opal call. | |
495 | */ | |
496 | bl machine_check_queue_event | |
497 | MACHINE_CHECK_HANDLER_WINDUP | |
498 | rfid | |
499 | 9: | |
500 | /* Deliver the machine check to host kernel in V mode. */ | |
501 | MACHINE_CHECK_HANDLER_WINDUP | |
502 | b machine_check_pSeries | |
503 | ||
504 | EXC_COMMON_BEGIN(unrecover_mce) | |
505 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
506 | addi r3,r1,STACK_FRAME_OVERHEAD | |
507 | bl machine_check_exception | |
508 | /* | |
509 | * We will not reach here. Even if we did, there is no way out. Call | |
510 | * unrecoverable_exception and die. | |
511 | */ | |
512 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
513 | bl unrecoverable_exception | |
514 | b 1b | |
515 | ||
0ebc4cda | 516 | |
da2bc464 | 517 | EXC_REAL(data_access, 0x300, 0x380) |
80795e6c NP |
518 | EXC_VIRT(data_access, 0x4300, 0x4380, 0x300) |
519 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) | |
520 | ||
521 | EXC_COMMON_BEGIN(data_access_common) | |
522 | /* | |
523 | * Here r13 points to the paca, r9 contains the saved CR, | |
524 | * SRR0 and SRR1 are saved in r11 and r12, | |
525 | * r9 - r13 are saved in paca->exgen. | |
526 | */ | |
527 | mfspr r10,SPRN_DAR | |
528 | std r10,PACA_EXGEN+EX_DAR(r13) | |
529 | mfspr r10,SPRN_DSISR | |
530 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
531 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
532 | RECONCILE_IRQ_STATE(r10, r11) | |
533 | ld r12,_MSR(r1) | |
534 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
535 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
536 | li r5,0x300 | |
537 | std r3,_DAR(r1) | |
538 | std r4,_DSISR(r1) | |
539 | BEGIN_MMU_FTR_SECTION | |
540 | b do_hash_page /* Try to handle as hpte fault */ | |
541 | MMU_FTR_SECTION_ELSE | |
542 | b handle_page_fault | |
543 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
544 | ||
0ebc4cda | 545 | |
da2bc464 | 546 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400) |
673b189a | 547 | SET_SCRATCH0(r13) |
1707dd16 | 548 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 549 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
0ebc4cda BH |
550 | std r3,PACA_EXSLB+EX_R3(r13) |
551 | mfspr r3,SPRN_DAR | |
b01c8b54 | 552 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 553 | crset 4*cr6+eq |
0ebc4cda | 554 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 555 | b slb_miss_realmode |
0ebc4cda BH |
556 | #else |
557 | /* | |
ad0289e4 | 558 | * We can't just use a direct branch to slb_miss_realmode |
0ebc4cda BH |
559 | * because the distance from here to there depends on where |
560 | * the kernel ends up being put. | |
561 | */ | |
562 | mfctr r11 | |
ad0289e4 | 563 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
564 | mtctr r10 |
565 | bctr | |
566 | #endif | |
da2bc464 | 567 | EXC_REAL_END(data_access_slb, 0x380, 0x400) |
0ebc4cda | 568 | |
2b9af6e4 NP |
569 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400) |
570 | SET_SCRATCH0(r13) | |
571 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
572 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) | |
573 | std r3,PACA_EXSLB+EX_R3(r13) | |
574 | mfspr r3,SPRN_DAR | |
575 | mfspr r12,SPRN_SRR1 | |
576 | crset 4*cr6+eq | |
577 | #ifndef CONFIG_RELOCATABLE | |
578 | b slb_miss_realmode | |
579 | #else | |
580 | /* | |
581 | * We can't just use a direct branch to slb_miss_realmode | |
582 | * because the distance from here to there depends on where | |
583 | * the kernel ends up being put. | |
584 | */ | |
585 | mfctr r11 | |
586 | LOAD_HANDLER(r10, slb_miss_realmode) | |
587 | mtctr r10 | |
588 | bctr | |
589 | #endif | |
590 | EXC_VIRT_END(data_access_slb, 0x4380, 0x4400) | |
591 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) | |
592 | ||
593 | ||
da2bc464 | 594 | EXC_REAL(instruction_access, 0x400, 0x480) |
27ce77df NP |
595 | EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400) |
596 | TRAMP_KVM(PACA_EXGEN, 0x400) | |
597 | ||
598 | EXC_COMMON_BEGIN(instruction_access_common) | |
599 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
600 | RECONCILE_IRQ_STATE(r10, r11) | |
601 | ld r12,_MSR(r1) | |
602 | ld r3,_NIP(r1) | |
603 | andis. r4,r12,0x5820 | |
604 | li r5,0x400 | |
605 | std r3,_DAR(r1) | |
606 | std r4,_DSISR(r1) | |
607 | BEGIN_MMU_FTR_SECTION | |
608 | b do_hash_page /* Try to handle as hpte fault */ | |
609 | MMU_FTR_SECTION_ELSE | |
610 | b handle_page_fault | |
611 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
612 | ||
0ebc4cda | 613 | |
da2bc464 | 614 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500) |
673b189a | 615 | SET_SCRATCH0(r13) |
1707dd16 | 616 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 617 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
618 | std r3,PACA_EXSLB+EX_R3(r13) |
619 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
b01c8b54 | 620 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 621 | crclr 4*cr6+eq |
0ebc4cda | 622 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 623 | b slb_miss_realmode |
0ebc4cda BH |
624 | #else |
625 | mfctr r11 | |
ad0289e4 | 626 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
627 | mtctr r10 |
628 | bctr | |
629 | #endif | |
da2bc464 | 630 | EXC_REAL_END(instruction_access_slb, 0x480, 0x500) |
0ebc4cda | 631 | |
8d04631a NP |
632 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500) |
633 | SET_SCRATCH0(r13) | |
634 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
635 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) | |
636 | std r3,PACA_EXSLB+EX_R3(r13) | |
637 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
638 | mfspr r12,SPRN_SRR1 | |
639 | crclr 4*cr6+eq | |
640 | #ifndef CONFIG_RELOCATABLE | |
641 | b slb_miss_realmode | |
642 | #else | |
643 | mfctr r11 | |
644 | LOAD_HANDLER(r10, slb_miss_realmode) | |
645 | mtctr r10 | |
646 | bctr | |
647 | #endif | |
648 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500) | |
649 | TRAMP_KVM(PACA_EXSLB, 0x480) | |
650 | ||
651 | ||
652 | /* This handler is used by both 0x380 and 0x480 slb miss interrupts */ | |
653 | EXC_COMMON_BEGIN(slb_miss_realmode) | |
654 | /* | |
655 | * r13 points to the PACA, r9 contains the saved CR, | |
656 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
657 | * r3 has the faulting address | |
658 | * r9 - r13 are saved in paca->exslb. | |
659 | * r3 is saved in paca->slb_r3 | |
660 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss | |
661 | * We assume we aren't going to take any exceptions during this | |
662 | * procedure. | |
663 | */ | |
664 | mflr r10 | |
665 | #ifdef CONFIG_RELOCATABLE | |
666 | mtctr r11 | |
667 | #endif | |
668 | ||
669 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
670 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
671 | std r3,PACA_EXSLB+EX_DAR(r13) | |
672 | ||
673 | crset 4*cr0+eq | |
674 | #ifdef CONFIG_PPC_STD_MMU_64 | |
675 | BEGIN_MMU_FTR_SECTION | |
676 | bl slb_allocate_realmode | |
677 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) | |
678 | #endif | |
679 | ||
680 | ld r10,PACA_EXSLB+EX_LR(r13) | |
681 | ld r3,PACA_EXSLB+EX_R3(r13) | |
682 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
683 | mtlr r10 | |
684 | ||
685 | beq 8f /* if bad address, make full stack frame */ | |
686 | ||
687 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
688 | beq- 2f | |
689 | ||
690 | /* All done -- return from exception. */ | |
691 | ||
692 | .machine push | |
693 | .machine "power4" | |
694 | mtcrf 0x80,r9 | |
695 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ | |
696 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
697 | .machine pop | |
698 | ||
699 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
700 | ld r9,PACA_EXSLB+EX_R9(r13) | |
701 | ld r10,PACA_EXSLB+EX_R10(r13) | |
702 | ld r11,PACA_EXSLB+EX_R11(r13) | |
703 | ld r12,PACA_EXSLB+EX_R12(r13) | |
704 | ld r13,PACA_EXSLB+EX_R13(r13) | |
705 | rfid | |
706 | b . /* prevent speculative execution */ | |
707 | ||
708 | 2: mfspr r11,SPRN_SRR0 | |
709 | LOAD_HANDLER(r10,unrecov_slb) | |
710 | mtspr SPRN_SRR0,r10 | |
711 | ld r10,PACAKMSR(r13) | |
712 | mtspr SPRN_SRR1,r10 | |
713 | rfid | |
714 | b . | |
715 | ||
716 | 8: mfspr r11,SPRN_SRR0 | |
717 | LOAD_HANDLER(r10,bad_addr_slb) | |
718 | mtspr SPRN_SRR0,r10 | |
719 | ld r10,PACAKMSR(r13) | |
720 | mtspr SPRN_SRR1,r10 | |
721 | rfid | |
722 | b . | |
723 | ||
724 | EXC_COMMON_BEGIN(unrecov_slb) | |
725 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
726 | RECONCILE_IRQ_STATE(r10, r11) | |
727 | bl save_nvgprs | |
728 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
729 | bl unrecoverable_exception | |
730 | b 1b | |
731 | ||
732 | EXC_COMMON_BEGIN(bad_addr_slb) | |
733 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) | |
734 | RECONCILE_IRQ_STATE(r10, r11) | |
735 | ld r3, PACA_EXSLB+EX_DAR(r13) | |
736 | std r3, _DAR(r1) | |
737 | beq cr6, 2f | |
738 | li r10, 0x480 /* fix trap number for I-SLB miss */ | |
739 | std r10, _TRAP(r1) | |
740 | 2: bl save_nvgprs | |
741 | addi r3, r1, STACK_FRAME_OVERHEAD | |
742 | bl slb_miss_bad_addr | |
743 | b ret_from_except | |
744 | ||
da2bc464 | 745 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600) |
b3e6b5df | 746 | .globl hardware_interrupt_hv; |
b3e6b5df | 747 | hardware_interrupt_hv: |
a5d4f3ad | 748 | BEGIN_FTR_SECTION |
da2bc464 | 749 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
b01c8b54 | 750 | EXC_HV, SOFTEN_TEST_HV) |
da2bc464 | 751 | do_kvm_H0x500: |
b01c8b54 | 752 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) |
de56a948 | 753 | FTR_SECTION_ELSE |
da2bc464 | 754 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
31a40e2b | 755 | EXC_STD, SOFTEN_TEST_PR) |
da2bc464 | 756 | do_kvm_0x500: |
de56a948 | 757 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
969391c5 | 758 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
da2bc464 ME |
759 | EXC_REAL_END(hardware_interrupt, 0x500, 0x600) |
760 | ||
c138e588 NP |
761 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600) |
762 | .globl hardware_interrupt_relon_hv; | |
763 | hardware_interrupt_relon_hv: | |
764 | BEGIN_FTR_SECTION | |
765 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) | |
766 | FTR_SECTION_ELSE | |
767 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) | |
768 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
769 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600) | |
770 | ||
771 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) | |
772 | ||
773 | ||
da2bc464 | 774 | EXC_REAL(alignment, 0x600, 0x700) |
f9aa6714 | 775 | EXC_VIRT(alignment, 0x4600, 0x4700, 0x600) |
da2bc464 | 776 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 NP |
777 | EXC_COMMON_BEGIN(alignment_common) |
778 | mfspr r10,SPRN_DAR | |
779 | std r10,PACA_EXGEN+EX_DAR(r13) | |
780 | mfspr r10,SPRN_DSISR | |
781 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
782 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
783 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
784 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
785 | std r3,_DAR(r1) | |
786 | std r4,_DSISR(r1) | |
787 | bl save_nvgprs | |
788 | RECONCILE_IRQ_STATE(r10, r11) | |
789 | addi r3,r1,STACK_FRAME_OVERHEAD | |
790 | bl alignment_exception | |
791 | b ret_from_except | |
792 | ||
da2bc464 ME |
793 | |
794 | EXC_REAL(program_check, 0x700, 0x800) | |
11e87346 | 795 | EXC_VIRT(program_check, 0x4700, 0x4800, 0x700) |
da2bc464 | 796 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 NP |
797 | EXC_COMMON_BEGIN(program_check_common) |
798 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
799 | bl save_nvgprs | |
800 | RECONCILE_IRQ_STATE(r10, r11) | |
801 | addi r3,r1,STACK_FRAME_OVERHEAD | |
802 | bl program_check_exception | |
803 | b ret_from_except | |
804 | ||
b01c8b54 | 805 | |
da2bc464 | 806 | EXC_REAL(fp_unavailable, 0x800, 0x900) |
c78d9b97 | 807 | EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800) |
da2bc464 | 808 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 NP |
809 | EXC_COMMON_BEGIN(fp_unavailable_common) |
810 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
811 | bne 1f /* if from user, just load it up */ | |
812 | bl save_nvgprs | |
813 | RECONCILE_IRQ_STATE(r10, r11) | |
814 | addi r3,r1,STACK_FRAME_OVERHEAD | |
815 | bl kernel_fp_unavailable_exception | |
816 | BUG_OPCODE | |
817 | 1: | |
818 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
819 | BEGIN_FTR_SECTION | |
820 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
821 | * transaction), go do TM stuff | |
822 | */ | |
823 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
824 | bne- 2f | |
825 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
826 | #endif | |
827 | bl load_up_fpu | |
828 | b fast_exception_return | |
829 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
830 | 2: /* User process was in a transaction */ | |
831 | bl save_nvgprs | |
832 | RECONCILE_IRQ_STATE(r10, r11) | |
833 | addi r3,r1,STACK_FRAME_OVERHEAD | |
834 | bl fp_unavailable_tm | |
835 | b ret_from_except | |
836 | #endif | |
837 | ||
a5d4f3ad | 838 | |
da2bc464 | 839 | EXC_REAL_MASKABLE(decrementer, 0x900, 0x980) |
39c0da57 NP |
840 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) |
841 | TRAMP_KVM(PACA_EXGEN, 0x900) | |
842 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
843 | ||
a485c709 | 844 | |
da2bc464 | 845 | EXC_REAL_HV(hdecrementer, 0x980, 0xa00) |
facc6d74 NP |
846 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980) |
847 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) | |
848 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
849 | ||
a5d4f3ad | 850 | |
da2bc464 | 851 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00) |
ca243163 | 852 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00) |
da2bc464 | 853 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
854 | #ifdef CONFIG_PPC_DOORBELL |
855 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
856 | #else | |
857 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
858 | #endif | |
859 | ||
0ebc4cda | 860 | |
da2bc464 | 861 | EXC_REAL(trap_0b, 0xb00, 0xc00) |
341215dc | 862 | EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) |
da2bc464 | 863 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
864 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
865 | ||
da2bc464 ME |
866 | |
867 | EXC_REAL_BEGIN(system_call, 0xc00, 0xd00) | |
8b91a255 SW |
868 | /* |
869 | * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems | |
870 | * that support it) before changing to HMT_MEDIUM. That allows the KVM | |
871 | * code to save that value into the guest state (it is the guest's PPR | |
872 | * value). Otherwise just change to HMT_MEDIUM as userspace has | |
873 | * already saved the PPR. | |
874 | */ | |
b01c8b54 PM |
875 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
876 | SET_SCRATCH0(r13) | |
877 | GET_PACA(r13) | |
878 | std r9,PACA_EXGEN+EX_R9(r13) | |
8b91a255 SW |
879 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); |
880 | HMT_MEDIUM; | |
b01c8b54 | 881 | std r10,PACA_EXGEN+EX_R10(r13) |
8b91a255 | 882 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); |
b01c8b54 | 883 | mfcr r9 |
da2bc464 | 884 | KVMTEST_PR(0xc00) |
b01c8b54 | 885 | GET_SCRATCH0(r13) |
8b91a255 SW |
886 | #else |
887 | HMT_MEDIUM; | |
b01c8b54 | 888 | #endif |
742415d6 MN |
889 | SYSCALL_PSERIES_1 |
890 | SYSCALL_PSERIES_2_RFID | |
891 | SYSCALL_PSERIES_3 | |
da2bc464 ME |
892 | EXC_REAL_END(system_call, 0xc00, 0xd00) |
893 | ||
894 | TRAMP_KVM(PACA_EXGEN, 0xc00) | |
895 | ||
896 | EXC_REAL(single_step, 0xd00, 0xe00) | |
897 | ||
898 | TRAMP_KVM(PACA_EXGEN, 0xd00) | |
b01c8b54 | 899 | |
b3e6b5df BH |
900 | |
901 | /* At 0xe??? we have a bunch of hypervisor exceptions, we branch | |
902 | * out of line to handle them | |
903 | */ | |
da2bc464 | 904 | __EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20) |
1707dd16 | 905 | |
da2bc464 | 906 | __EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40) |
1707dd16 | 907 | |
da2bc464 | 908 | __EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60) |
1707dd16 | 909 | |
da2bc464 | 910 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early) |
1707dd16 | 911 | |
da2bc464 | 912 | __EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0) |
0ebc4cda | 913 | |
da2bc464 | 914 | __EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0) |
9baaef0a | 915 | |
da2bc464 | 916 | EXC_REAL_NONE(0xec0, 0xf00) |
0ebc4cda | 917 | |
da2bc464 | 918 | __EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20) |
0ebc4cda | 919 | |
da2bc464 | 920 | __EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40) |
0ebc4cda | 921 | |
da2bc464 ME |
922 | __EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60) |
923 | ||
924 | __EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80) | |
925 | ||
926 | __EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0) | |
927 | ||
928 | EXC_REAL_NONE(0xfa0, 0x1200) | |
d0c0c9a1 | 929 | |
0ebc4cda | 930 | #ifdef CONFIG_CBE_RAS |
da2bc464 ME |
931 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300) |
932 | ||
933 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) | |
934 | ||
935 | #else /* CONFIG_CBE_RAS */ | |
936 | EXC_REAL_NONE(0x1200, 0x1300) | |
937 | #endif | |
b01c8b54 | 938 | |
da2bc464 | 939 | EXC_REAL(instruction_breakpoint, 0x1300, 0x1400) |
b01c8b54 | 940 | |
da2bc464 ME |
941 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
942 | ||
943 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600) | |
b92a66a6 | 944 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 945 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 946 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
947 | |
948 | #ifdef CONFIG_PPC_DENORMALISATION | |
949 | mfspr r10,SPRN_HSRR1 | |
950 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
afcf0095 NP |
951 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
952 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
953 | bne+ denorm_assist | |
954 | #endif | |
1e9b4507 | 955 | |
afcf0095 NP |
956 | KVMTEST_PR(0x1500) |
957 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) | |
958 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600) | |
a74599a5 | 959 | |
afcf0095 | 960 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) |
da2bc464 | 961 | |
afcf0095 NP |
962 | #ifdef CONFIG_CBE_RAS |
963 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700) | |
964 | ||
965 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) | |
966 | ||
967 | #else /* CONFIG_CBE_RAS */ | |
968 | EXC_REAL_NONE(0x1600, 0x1700) | |
969 | #endif | |
970 | ||
971 | EXC_REAL(altivec_assist, 0x1700, 0x1800) | |
972 | ||
973 | TRAMP_KVM(PACA_EXGEN, 0x1700) | |
974 | ||
975 | #ifdef CONFIG_CBE_RAS | |
976 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900) | |
977 | ||
978 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) | |
979 | ||
980 | #else /* CONFIG_CBE_RAS */ | |
981 | EXC_REAL_NONE(0x1800, 0x1900) | |
982 | #endif | |
983 | ||
984 | ||
985 | /*** Out of line interrupts support ***/ | |
986 | ||
987 | /* moved from 0x200 */ | |
b01c8b54 | 988 | |
b92a66a6 | 989 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 990 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
991 | BEGIN_FTR_SECTION |
992 | /* | |
993 | * To denormalise we need to move a copy of the register to itself. | |
994 | * For POWER6 do that here for all FP regs. | |
995 | */ | |
996 | mfmsr r10 | |
997 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
998 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
999 | mtmsrd r10 | |
1000 | sync | |
d7c67fb1 MN |
1001 | |
1002 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
1003 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
1004 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
1005 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
1006 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
1007 | FMR32(0) | |
1008 | ||
b92a66a6 MN |
1009 | FTR_SECTION_ELSE |
1010 | /* | |
1011 | * To denormalise we need to move a copy of the register to itself. | |
1012 | * For POWER7 do that here for the first 32 VSX registers only. | |
1013 | */ | |
1014 | mfmsr r10 | |
1015 | oris r10,r10,MSR_VSX@h | |
1016 | mtmsrd r10 | |
1017 | sync | |
d7c67fb1 MN |
1018 | |
1019 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
1020 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
1021 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
1022 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
1023 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
1024 | XVCPSGNDP32(0) | |
1025 | ||
b92a66a6 | 1026 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1027 | |
1028 | BEGIN_FTR_SECTION | |
1029 | b denorm_done | |
1030 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1031 | /* | |
1032 | * To denormalise we need to move a copy of the register to itself. | |
1033 | * For POWER8 we need to do that for all 64 VSX registers | |
1034 | */ | |
1035 | XVCPSGNDP32(32) | |
1036 | denorm_done: | |
b92a66a6 MN |
1037 | mtspr SPRN_HSRR0,r11 |
1038 | mtcrf 0x80,r9 | |
1039 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1040 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1041 | BEGIN_FTR_SECTION |
1042 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1043 | mtspr SPRN_CFAR,r10 | |
1044 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1045 | ld r10,PACA_EXGEN+EX_R10(r13) |
1046 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1047 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1048 | ld r13,PACA_EXGEN+EX_R13(r13) | |
1049 | HRFID | |
1050 | b . | |
1051 | #endif | |
1052 | ||
b3e6b5df | 1053 | /* moved from 0xe00 */ |
da2bc464 ME |
1054 | __TRAMP_REAL_REAL_OOL_HV(h_data_storage, 0xe00) |
1055 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) | |
1056 | ||
1057 | __TRAMP_REAL_REAL_OOL_HV(h_instr_storage, 0xe20) | |
1058 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) | |
1059 | ||
1060 | __TRAMP_REAL_REAL_OOL_HV(emulation_assist, 0xe40) | |
1061 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) | |
0869b6fd | 1062 | |
da2bc464 ME |
1063 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
1064 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) | |
0ebc4cda | 1065 | |
da2bc464 ME |
1066 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80) |
1067 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) | |
1068 | ||
1069 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0) | |
1070 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) | |
9baaef0a | 1071 | |
0ebc4cda | 1072 | /* moved from 0xf00 */ |
da2bc464 ME |
1073 | __TRAMP_REAL_REAL_OOL(performance_monitor, 0xf00) |
1074 | TRAMP_KVM(PACA_EXGEN, 0xf00) | |
1075 | ||
1076 | __TRAMP_REAL_REAL_OOL(altivec_unavailable, 0xf20) | |
1077 | TRAMP_KVM(PACA_EXGEN, 0xf20) | |
1078 | ||
1079 | __TRAMP_REAL_REAL_OOL(vsx_unavailable, 0xf40) | |
1080 | TRAMP_KVM(PACA_EXGEN, 0xf40) | |
1081 | ||
1082 | __TRAMP_REAL_REAL_OOL(facility_unavailable, 0xf60) | |
1083 | TRAMP_KVM(PACA_EXGEN, 0xf60) | |
1084 | ||
1085 | __TRAMP_REAL_REAL_OOL_HV(h_facility_unavailable, 0xf80) | |
1086 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) | |
0ebc4cda BH |
1087 | |
1088 | /* | |
fe9e1d54 IM |
1089 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
1090 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
1091 | * - If it was a doorbell we return immediately since doorbells are edge | |
1092 | * triggered and won't automatically refire. | |
0869b6fd MS |
1093 | * - If it was a HMI we return immediately since we handled it in realmode |
1094 | * and it won't refire. | |
fe9e1d54 IM |
1095 | * - else we hard disable and return. |
1096 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 1097 | */ |
7230c564 BH |
1098 | #define MASKED_INTERRUPT(_H) \ |
1099 | masked_##_H##interrupt: \ | |
1100 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
1101 | lbz r11,PACAIRQHAPPENED(r13); \ | |
1102 | or r11,r11,r10; \ | |
1103 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
1104 | cmpwi r10,PACA_IRQ_DEC; \ |
1105 | bne 1f; \ | |
7230c564 BH |
1106 | lis r10,0x7fff; \ |
1107 | ori r10,r10,0xffff; \ | |
1108 | mtspr SPRN_DEC,r10; \ | |
1109 | b 2f; \ | |
fe9e1d54 | 1110 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
0869b6fd MS |
1111 | beq 2f; \ |
1112 | cmpwi r10,PACA_IRQ_HMI; \ | |
fe9e1d54 IM |
1113 | beq 2f; \ |
1114 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
1115 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
1116 | rotldi r10,r10,16; \ | |
1117 | mtspr SPRN_##_H##SRR1,r10; \ | |
1118 | 2: mtcrf 0x80,r9; \ | |
1119 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
1120 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
1121 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
1122 | GET_SCRATCH0(r13); \ | |
1123 | ##_H##rfid; \ | |
0ebc4cda | 1124 | b . |
57f26649 NP |
1125 | |
1126 | /* | |
1127 | * Real mode exceptions actually use this too, but alternate | |
1128 | * instruction code patches (which end up in the common .text area) | |
1129 | * cannot reach these if they are put there. | |
1130 | */ | |
1131 | USE_FIXED_SECTION(virt_trampolines) | |
7230c564 BH |
1132 | MASKED_INTERRUPT() |
1133 | MASKED_INTERRUPT(H) | |
0ebc4cda | 1134 | |
7230c564 BH |
1135 | /* |
1136 | * Called from arch_local_irq_enable when an interrupt needs | |
fe9e1d54 IM |
1137 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate |
1138 | * which kind of interrupt. MSR:EE is already off. We generate a | |
7230c564 BH |
1139 | * stackframe like if a real interrupt had happened. |
1140 | * | |
1141 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
1142 | * in the generated frame has EE set to 1 or the exception | |
1143 | * handler will not properly re-enable them. | |
1144 | */ | |
57f26649 | 1145 | USE_TEXT_SECTION() |
7230c564 BH |
1146 | _GLOBAL(__replay_interrupt) |
1147 | /* We are going to jump to the exception common code which | |
1148 | * will retrieve various register values from the PACA which | |
1149 | * we don't give a damn about, so we don't bother storing them. | |
1150 | */ | |
1151 | mfmsr r12 | |
1152 | mflr r11 | |
1153 | mfcr r9 | |
1154 | ori r12,r12,MSR_EE | |
fe9e1d54 IM |
1155 | cmpwi r3,0x900 |
1156 | beq decrementer_common | |
1157 | cmpwi r3,0x500 | |
1158 | beq hardware_interrupt_common | |
1159 | BEGIN_FTR_SECTION | |
1160 | cmpwi r3,0xe80 | |
1161 | beq h_doorbell_common | |
9baaef0a BH |
1162 | cmpwi r3,0xea0 |
1163 | beq h_virt_irq_common | |
fd7bacbc MS |
1164 | cmpwi r3,0xe60 |
1165 | beq hmi_exception_common | |
fe9e1d54 IM |
1166 | FTR_SECTION_ELSE |
1167 | cmpwi r3,0xa00 | |
1168 | beq doorbell_super_common | |
1169 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1170 | blr | |
a5d4f3ad | 1171 | |
4f6c11db | 1172 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 1173 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
1174 | /* |
1175 | * Here all GPRs are unchanged from when the interrupt happened | |
1176 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1177 | */ | |
1178 | mfspr r13, SPRN_SRR0 | |
1179 | addi r13, r13, 4 | |
1180 | mtspr SPRN_SRR0, r13 | |
1181 | GET_SCRATCH0(r13) | |
1182 | rfid | |
1183 | b . | |
1184 | ||
da2bc464 | 1185 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
1186 | /* |
1187 | * Here all GPRs are unchanged from when the interrupt happened | |
1188 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1189 | */ | |
1190 | mfspr r13, SPRN_HSRR0 | |
1191 | addi r13, r13, 4 | |
1192 | mtspr SPRN_HSRR0, r13 | |
1193 | GET_SCRATCH0(r13) | |
1194 | hrfid | |
1195 | b . | |
1196 | #endif | |
1197 | ||
0ebc4cda | 1198 | /* |
057b6d7e HB |
1199 | * Ensure that any handlers that get invoked from the exception prologs |
1200 | * above are below the first 64KB (0x10000) of the kernel image because | |
1201 | * the prologs assemble the addresses of these handlers using the | |
1202 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
1203 | */ |
1204 | ||
1205 | /*** Common interrupt handlers ***/ | |
1206 | ||
0ebc4cda | 1207 | |
da2bc464 | 1208 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
da2bc464 | 1209 | EXC_COMMON(trap_0e_common, 0xe00, unknown_exception) |
da2bc464 | 1210 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) |
da2bc464 | 1211 | EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) |
655bb3f4 | 1212 | #ifdef CONFIG_PPC_DOORBELL |
da2bc464 | 1213 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) |
655bb3f4 | 1214 | #else |
da2bc464 | 1215 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) |
655bb3f4 | 1216 | #endif |
da2bc464 | 1217 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) |
da2bc464 | 1218 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) |
da2bc464 | 1219 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
da2bc464 | 1220 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
0ebc4cda | 1221 | #ifdef CONFIG_ALTIVEC |
da2bc464 | 1222 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) |
0ebc4cda | 1223 | #else |
da2bc464 | 1224 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) |
0ebc4cda | 1225 | #endif |
0ebc4cda | 1226 | |
c1fb6816 MN |
1227 | /* |
1228 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
1229 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
1230 | * it. Addresses are the same as the original interrupt addresses, but | |
1231 | * offset by 0xc000000000004000. | |
1232 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
1233 | * KVM: None of these traps are from the guest ; anything that escalated | |
1234 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
1235 | */ | |
1236 | ||
1237 | /* | |
1238 | * This uses the standard macro, since the original 0x300 vector | |
1239 | * only has extra guff for STAB-based processors -- which never | |
1240 | * come here. | |
1241 | */ | |
da2bc464 | 1242 | |
da2bc464 | 1243 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00) |
c1fb6816 MN |
1244 | HMT_MEDIUM |
1245 | SYSCALL_PSERIES_1 | |
1246 | SYSCALL_PSERIES_2_DIRECT | |
1247 | SYSCALL_PSERIES_3 | |
da2bc464 | 1248 | EXC_VIRT_END(system_call, 0x4c00, 0x4d00) |
c1fb6816 | 1249 | |
da2bc464 | 1250 | EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00) |
c1fb6816 | 1251 | |
da2bc464 ME |
1252 | EXC_VIRT_BEGIN(unused, 0x4e00, 0x4e20) |
1253 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ | |
1254 | EXC_VIRT_END(unused, 0x4e00, 0x4e20) | |
c1fb6816 | 1255 | |
da2bc464 ME |
1256 | EXC_VIRT_BEGIN(unused, 0x4e20, 0x4e40) |
1257 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ | |
1258 | EXC_VIRT_END(unused, 0x4e20, 0x4e40) | |
c1fb6816 | 1259 | |
da2bc464 | 1260 | __EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60) |
c1fb6816 | 1261 | |
da2bc464 ME |
1262 | EXC_VIRT_BEGIN(unused, 0x4e60, 0x4e80) |
1263 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ | |
1264 | EXC_VIRT_END(unused, 0x4e60, 0x4e80) | |
c1fb6816 | 1265 | |
da2bc464 | 1266 | __EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0) |
c1fb6816 | 1267 | |
da2bc464 | 1268 | __EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0) |
9baaef0a | 1269 | |
da2bc464 | 1270 | EXC_VIRT_NONE(0x4ec0, 0x4f00) |
c1fb6816 | 1271 | |
da2bc464 | 1272 | __EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20) |
c1fb6816 | 1273 | |
da2bc464 | 1274 | __EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40) |
c1fb6816 | 1275 | |
da2bc464 | 1276 | __EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60) |
d0c0c9a1 | 1277 | |
da2bc464 ME |
1278 | __EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80) |
1279 | ||
1280 | __EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0) | |
1281 | ||
1282 | EXC_VIRT_NONE(0x4fa0, 0x5200) | |
1283 | ||
1284 | EXC_VIRT_NONE(0x5200, 0x5300) | |
1285 | ||
1286 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300) | |
b14b6260 | 1287 | |
c1fb6816 | 1288 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 ME |
1289 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600) |
1290 | b exc_real_0x1500_denorm_exception_hv | |
1291 | EXC_VIRT_END(denorm_exception, 0x5500, 0x5600) | |
1292 | #else | |
1293 | EXC_VIRT_NONE(0x5500, 0x5600) | |
c1fb6816 | 1294 | #endif |
c1fb6816 | 1295 | |
da2bc464 ME |
1296 | EXC_VIRT_NONE(0x5600, 0x5700) |
1297 | ||
1298 | EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700) | |
1299 | ||
1300 | EXC_VIRT_NONE(0x5800, 0x5900) | |
1301 | ||
57f26649 | 1302 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 1303 | b __ppc64_runlatch_on |
fe1952fc | 1304 | |
da2bc464 | 1305 | EXC_COMMON_BEGIN(h_data_storage_common) |
278a6cdc MN |
1306 | mfspr r10,SPRN_HDAR |
1307 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1308 | mfspr r10,SPRN_HDSISR | |
1309 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
1310 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
b1576fec | 1311 | bl save_nvgprs |
9daf112b | 1312 | RECONCILE_IRQ_STATE(r10, r11) |
278a6cdc | 1313 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1314 | bl unknown_exception |
1315 | b ret_from_except | |
b3e6b5df | 1316 | |
0ebc4cda | 1317 | |
da2bc464 | 1318 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) |
b3e6b5df | 1319 | |
da2bc464 | 1320 | EXC_COMMON_BEGIN(altivec_unavailable_common) |
0ebc4cda BH |
1321 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) |
1322 | #ifdef CONFIG_ALTIVEC | |
1323 | BEGIN_FTR_SECTION | |
1324 | beq 1f | |
bc2a9408 MN |
1325 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1326 | BEGIN_FTR_SECTION_NESTED(69) | |
1327 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1328 | * transaction), go do TM stuff | |
1329 | */ | |
1330 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1331 | bne- 2f | |
1332 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1333 | #endif | |
b1576fec | 1334 | bl load_up_altivec |
0ebc4cda | 1335 | b fast_exception_return |
bc2a9408 MN |
1336 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1337 | 2: /* User process was in a transaction */ | |
b1576fec | 1338 | bl save_nvgprs |
9daf112b | 1339 | RECONCILE_IRQ_STATE(r10, r11) |
bc2a9408 | 1340 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1341 | bl altivec_unavailable_tm |
1342 | b ret_from_except | |
bc2a9408 | 1343 | #endif |
0ebc4cda BH |
1344 | 1: |
1345 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1346 | #endif | |
b1576fec | 1347 | bl save_nvgprs |
9daf112b | 1348 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 1349 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1350 | bl altivec_unavailable_exception |
1351 | b ret_from_except | |
0ebc4cda | 1352 | |
da2bc464 | 1353 | EXC_COMMON_BEGIN(vsx_unavailable_common) |
0ebc4cda BH |
1354 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) |
1355 | #ifdef CONFIG_VSX | |
1356 | BEGIN_FTR_SECTION | |
7230c564 | 1357 | beq 1f |
bc2a9408 MN |
1358 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1359 | BEGIN_FTR_SECTION_NESTED(69) | |
1360 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1361 | * transaction), go do TM stuff | |
1362 | */ | |
1363 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1364 | bne- 2f | |
1365 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1366 | #endif | |
b1576fec | 1367 | b load_up_vsx |
bc2a9408 MN |
1368 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1369 | 2: /* User process was in a transaction */ | |
b1576fec | 1370 | bl save_nvgprs |
9daf112b | 1371 | RECONCILE_IRQ_STATE(r10, r11) |
bc2a9408 | 1372 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1373 | bl vsx_unavailable_tm |
1374 | b ret_from_except | |
bc2a9408 | 1375 | #endif |
0ebc4cda BH |
1376 | 1: |
1377 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1378 | #endif | |
b1576fec | 1379 | bl save_nvgprs |
9daf112b | 1380 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 1381 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1382 | bl vsx_unavailable_exception |
1383 | b ret_from_except | |
0ebc4cda | 1384 | |
61383407 | 1385 | /* Equivalents to the above handlers for relocation-on interrupt vectors */ |
da2bc464 ME |
1386 | __TRAMP_REAL_VIRT_OOL_HV(emulation_assist, 0xe40) |
1387 | __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_doorbell, 0xe80) | |
1388 | __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0xea0) | |
1389 | __TRAMP_REAL_VIRT_OOL(performance_monitor, 0xf00) | |
1390 | __TRAMP_REAL_VIRT_OOL(altivec_unavailable, 0xf20) | |
1391 | __TRAMP_REAL_VIRT_OOL(vsx_unavailable, 0xf40) | |
1392 | __TRAMP_REAL_VIRT_OOL(facility_unavailable, 0xf60) | |
1393 | __TRAMP_REAL_VIRT_OOL_HV(h_facility_unavailable, 0xf80) | |
61383407 | 1394 | |
57f26649 | 1395 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1396 | /* |
1397 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1398 | * handlers, so that they are copied to real address 0x100 when running | |
1399 | * a relocatable kernel. This ensures they can be reached from the short | |
1400 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1401 | * directly, without using LOAD_HANDLER(). | |
1402 | */ | |
1403 | .align 7 | |
1404 | .globl __end_interrupts | |
1405 | __end_interrupts: | |
57f26649 | 1406 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1407 | |
da2bc464 | 1408 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) |
da2bc464 | 1409 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) |
b88d4bce BH |
1410 | |
1411 | #ifdef CONFIG_CBE_RAS | |
da2bc464 | 1412 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1413 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
da2bc464 | 1414 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
b88d4bce BH |
1415 | #endif /* CONFIG_CBE_RAS */ |
1416 | ||
da2bc464 | 1417 | |
57f26649 | 1418 | TRAMP_REAL_BEGIN(hmi_exception_early) |
da2bc464 | 1419 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) |
11d54904 GR |
1420 | mr r10,r1 /* Save r1 */ |
1421 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
1422 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
1423 | std r9,_CCR(r1) /* save CR in stackframe */ | |
1424 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ | |
1425 | std r11,_NIP(r1) /* save HSRR0 in stackframe */ | |
1426 | mfspr r12,SPRN_HSRR1 /* Save SRR1 */ | |
1427 | std r12,_MSR(r1) /* save SRR1 in stackframe */ | |
1428 | std r10,0(r1) /* make stack chain pointer */ | |
1429 | std r0,GPR0(r1) /* save r0 in stackframe */ | |
1430 | std r10,GPR1(r1) /* save r1 in stackframe */ | |
1431 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) | |
1432 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1433 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1434 | bl hmi_exception_realmode | |
1435 | /* Windup the stack. */ | |
11d54904 GR |
1436 | /* Move original HSRR0 and HSRR1 into the respective regs */ |
1437 | ld r9,_MSR(r1) | |
1438 | mtspr SPRN_HSRR1,r9 | |
1439 | ld r3,_NIP(r1) | |
1440 | mtspr SPRN_HSRR0,r3 | |
1441 | ld r9,_CTR(r1) | |
1442 | mtctr r9 | |
1443 | ld r9,_XER(r1) | |
1444 | mtxer r9 | |
1445 | ld r9,_LINK(r1) | |
1446 | mtlr r9 | |
1447 | REST_GPR(0, r1) | |
1448 | REST_8GPRS(2, r1) | |
1449 | REST_GPR(10, r1) | |
1450 | ld r11,_CCR(r1) | |
1451 | mtcr r11 | |
1452 | REST_GPR(11, r1) | |
1453 | REST_2GPRS(12, r1) | |
1454 | /* restore original r1. */ | |
1455 | ld r1,GPR1(r1) | |
1456 | ||
1457 | /* | |
1458 | * Go to virtual mode and pull the HMI event information from | |
1459 | * firmware. | |
1460 | */ | |
1461 | .globl hmi_exception_after_realmode | |
1462 | hmi_exception_after_realmode: | |
1463 | SET_SCRATCH0(r13) | |
1464 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
da2bc464 | 1465 | b tramp_real_hmi_exception |
11d54904 | 1466 | |
087aa036 | 1467 | #ifdef CONFIG_PPC_970_NAP |
da2bc464 | 1468 | TRAMP_REAL_BEGIN(power4_fixup_nap) |
087aa036 CG |
1469 | andc r9,r9,r10 |
1470 | std r9,TI_LOCAL_FLAGS(r11) | |
1471 | ld r10,_LINK(r1) /* make idle task do the */ | |
1472 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1473 | blr | |
1474 | #endif | |
1475 | ||
57f26649 NP |
1476 | CLOSE_FIXED_SECTION(real_vectors); |
1477 | CLOSE_FIXED_SECTION(real_trampolines); | |
1478 | CLOSE_FIXED_SECTION(virt_vectors); | |
1479 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1480 | ||
1481 | USE_TEXT_SECTION() | |
1482 | ||
0ebc4cda BH |
1483 | /* |
1484 | * Hash table stuff | |
1485 | */ | |
1486 | .align 7 | |
6a3bab90 | 1487 | do_hash_page: |
caca285e | 1488 | #ifdef CONFIG_PPC_STD_MMU_64 |
9c7cc234 | 1489 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1490 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1491 | andis. r0,r4,DSISR_DABRMATCH@h |
1492 | bne- handle_dabr_fault | |
9778b696 | 1493 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1494 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1495 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1496 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1497 | |
1498 | /* | |
1499 | * r3 contains the faulting address | |
106713a1 | 1500 | * r4 msr |
0ebc4cda | 1501 | * r5 contains the trap number |
aefa5688 | 1502 | * r6 contains dsisr |
0ebc4cda | 1503 | * |
7230c564 | 1504 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1505 | */ |
106713a1 | 1506 | mr r4,r12 |
aefa5688 | 1507 | ld r6,_DSISR(r1) |
106713a1 AK |
1508 | bl __hash_page /* build HPTE if possible */ |
1509 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1510 | |
7230c564 | 1511 | /* Success */ |
0ebc4cda | 1512 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1513 | |
7230c564 BH |
1514 | /* Error */ |
1515 | blt- 13f | |
caca285e | 1516 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
9c7cc234 | 1517 | |
0ebc4cda BH |
1518 | /* Here we have a page fault that hash_page can't handle. */ |
1519 | handle_page_fault: | |
0ebc4cda BH |
1520 | 11: ld r4,_DAR(r1) |
1521 | ld r5,_DSISR(r1) | |
1522 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1523 | bl do_page_fault |
0ebc4cda | 1524 | cmpdi r3,0 |
a546498f | 1525 | beq+ 12f |
b1576fec | 1526 | bl save_nvgprs |
0ebc4cda BH |
1527 | mr r5,r3 |
1528 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1529 | lwz r4,_DAR(r1) | |
b1576fec AB |
1530 | bl bad_page_fault |
1531 | b ret_from_except | |
0ebc4cda | 1532 | |
a546498f BH |
1533 | /* We have a data breakpoint exception - handle it */ |
1534 | handle_dabr_fault: | |
b1576fec | 1535 | bl save_nvgprs |
a546498f BH |
1536 | ld r4,_DAR(r1) |
1537 | ld r5,_DSISR(r1) | |
1538 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1539 | bl do_break |
1540 | 12: b ret_from_except_lite | |
a546498f | 1541 | |
0ebc4cda | 1542 | |
caca285e | 1543 | #ifdef CONFIG_PPC_STD_MMU_64 |
0ebc4cda BH |
1544 | /* We have a page fault that hash_page could handle but HV refused |
1545 | * the PTE insertion | |
1546 | */ | |
b1576fec | 1547 | 13: bl save_nvgprs |
0ebc4cda BH |
1548 | mr r5,r3 |
1549 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1550 | ld r4,_DAR(r1) | |
b1576fec AB |
1551 | bl low_hash_fault |
1552 | b ret_from_except | |
caca285e | 1553 | #endif |
0ebc4cda | 1554 | |
9c1e1052 PM |
1555 | /* |
1556 | * We come here as a result of a DSI at a point where we don't want | |
1557 | * to call hash_page, such as when we are accessing memory (possibly | |
1558 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1559 | * were soft-disabled. We want to invoke the exception handler for | |
1560 | * the access, or panic if there isn't a handler. | |
1561 | */ | |
b1576fec | 1562 | 77: bl save_nvgprs |
9c1e1052 PM |
1563 | mr r4,r3 |
1564 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1565 | li r5,SIGSEGV | |
b1576fec AB |
1566 | bl bad_page_fault |
1567 | b ret_from_except | |
4e2bf01b ME |
1568 | |
1569 | /* | |
1570 | * Here we have detected that the kernel stack pointer is bad. | |
1571 | * R9 contains the saved CR, r13 points to the paca, | |
1572 | * r10 contains the (bad) kernel stack pointer, | |
1573 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1574 | * We switch to using an emergency stack, save the registers there, | |
1575 | * and call kernel_bad_stack(), which panics. | |
1576 | */ | |
1577 | bad_stack: | |
1578 | ld r1,PACAEMERGSP(r13) | |
1579 | subi r1,r1,64+INT_FRAME_SIZE | |
1580 | std r9,_CCR(r1) | |
1581 | std r10,GPR1(r1) | |
1582 | std r11,_NIP(r1) | |
1583 | std r12,_MSR(r1) | |
1584 | mfspr r11,SPRN_DAR | |
1585 | mfspr r12,SPRN_DSISR | |
1586 | std r11,_DAR(r1) | |
1587 | std r12,_DSISR(r1) | |
1588 | mflr r10 | |
1589 | mfctr r11 | |
1590 | mfxer r12 | |
1591 | std r10,_LINK(r1) | |
1592 | std r11,_CTR(r1) | |
1593 | std r12,_XER(r1) | |
1594 | SAVE_GPR(0,r1) | |
1595 | SAVE_GPR(2,r1) | |
1596 | ld r10,EX_R3(r3) | |
1597 | std r10,GPR3(r1) | |
1598 | SAVE_GPR(4,r1) | |
1599 | SAVE_4GPRS(5,r1) | |
1600 | ld r9,EX_R9(r3) | |
1601 | ld r10,EX_R10(r3) | |
1602 | SAVE_2GPRS(9,r1) | |
1603 | ld r9,EX_R11(r3) | |
1604 | ld r10,EX_R12(r3) | |
1605 | ld r11,EX_R13(r3) | |
1606 | std r9,GPR11(r1) | |
1607 | std r10,GPR12(r1) | |
1608 | std r11,GPR13(r1) | |
1609 | BEGIN_FTR_SECTION | |
1610 | ld r10,EX_CFAR(r3) | |
1611 | std r10,ORIG_GPR3(r1) | |
1612 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1613 | SAVE_8GPRS(14,r1) | |
1614 | SAVE_10GPRS(22,r1) | |
1615 | lhz r12,PACA_TRAP_SAVE(r13) | |
1616 | std r12,_TRAP(r1) | |
1617 | addi r11,r1,INT_FRAME_SIZE | |
1618 | std r11,0(r1) | |
1619 | li r12,0 | |
1620 | std r12,0(r11) | |
1621 | ld r2,PACATOC(r13) | |
1622 | ld r11,exception_marker@toc(r2) | |
1623 | std r12,RESULT(r1) | |
1624 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1625 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1626 | bl kernel_bad_stack | |
1627 | b 1b |