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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
7cba160a | 18 | #include <asm/cpuidle.h> |
da2bc464 | 19 | #include <asm/head-64.h> |
8aa34ab8 | 20 | |
0ebc4cda | 21 | /* |
57f26649 NP |
22 | * There are a few constraints to be concerned with. |
23 | * - Real mode exceptions code/data must be located at their physical location. | |
24 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
25 | * - Fixed location code must not call directly beyond the __end_interrupts | |
26 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
27 | * must be used. | |
28 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
29 | * virtual 0xc00... | |
30 | * - Conditional branch targets must be within +/-32K of caller. | |
31 | * | |
32 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
33 | * therefore don't have to run in physically located code or rfid to | |
34 | * virtual mode kernel code. However on relocatable kernels they do have | |
35 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
36 | * the exception vectors) may be located elsewhere. | |
37 | * | |
38 | * Virtual exceptions correspond with physical, except their entry points | |
39 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
40 | * offset applied. Virtual exceptions are enabled with the Alternate | |
41 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
42 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
43 | * cause exceptions to be delivered in real mode. | |
44 | * | |
45 | * It's impossible to receive interrupts below 0x300 via AIL. | |
46 | * | |
47 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
48 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
49 | * | |
50 | * | |
0ebc4cda BH |
51 | * We layout physical memory as follows: |
52 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
53 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
54 | * 0x1900 - 0x3fff : Real mode trampolines | |
55 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
56 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 57 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
58 | * 0x8000 - .... : Common interrupt handlers, remaining early |
59 | * setup code, rest of kernel. | |
e0319829 NP |
60 | * |
61 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
62 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
63 | * vectors there. | |
57f26649 NP |
64 | */ |
65 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
66 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
67 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
68 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
69 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
70 | /* | |
71 | * Data area reserved for FWNMI option. | |
72 | * This address (0x7000) is fixed by the RPA. | |
73 | * pseries and powernv need to keep the whole page from | |
74 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 75 | */ |
57f26649 NP |
76 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
77 | OPEN_TEXT_SECTION(0x8000) | |
78 | #else | |
79 | OPEN_TEXT_SECTION(0x7000) | |
80 | #endif | |
81 | ||
82 | USE_FIXED_SECTION(real_vectors) | |
83 | ||
0ebc4cda BH |
84 | /* |
85 | * This is the start of the interrupt handlers for pSeries | |
86 | * This code runs with relocation off. | |
87 | * Code from here to __end_interrupts gets copied down to real | |
88 | * address 0x100 when we are running a relocatable kernel. | |
89 | * Therefore any relative branches in this section must only | |
90 | * branch to labels in this section. | |
91 | */ | |
0ebc4cda BH |
92 | .globl __start_interrupts |
93 | __start_interrupts: | |
94 | ||
e0319829 | 95 | /* No virt vectors corresponding with 0x0..0x100 */ |
1a6822d1 | 96 | EXC_VIRT_NONE(0x4000, 0x100) |
e0319829 | 97 | |
fb479e44 | 98 | |
948cf67c | 99 | #ifdef CONFIG_PPC_P7_NAP |
fb479e44 NP |
100 | /* |
101 | * If running native on arch 2.06 or later, check if we are waking up | |
102 | * from nap/sleep/winkle, and branch to idle handler. | |
948cf67c | 103 | */ |
fb479e44 NP |
104 | #define IDLETEST(n) \ |
105 | BEGIN_FTR_SECTION ; \ | |
106 | mfspr r10,SPRN_SRR1 ; \ | |
107 | rlwinm. r10,r10,47-31,30,31 ; \ | |
108 | beq- 1f ; \ | |
109 | cmpwi cr3,r10,2 ; \ | |
110 | BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \ | |
111 | 1: \ | |
112 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) | |
113 | #else | |
114 | #define IDLETEST NOTEST | |
115 | #endif | |
371fefd6 | 116 | |
1a6822d1 | 117 | EXC_REAL_BEGIN(system_reset, 0x100, 0x100) |
fb479e44 | 118 | SET_SCRATCH0(r13) |
544686ca | 119 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
fb479e44 NP |
120 | IDLETEST, 0x100) |
121 | ||
1a6822d1 NP |
122 | EXC_REAL_END(system_reset, 0x100, 0x100) |
123 | EXC_VIRT_NONE(0x4100, 0x100) | |
fb479e44 NP |
124 | |
125 | #ifdef CONFIG_PPC_P7_NAP | |
126 | EXC_COMMON_BEGIN(system_reset_idle_common) | |
bf0153c1 | 127 | b pnv_powersave_wakeup |
fb479e44 | 128 | #endif |
aca79d2b | 129 | |
582baf44 NP |
130 | EXC_COMMON(system_reset_common, 0x100, system_reset_exception) |
131 | ||
132 | #ifdef CONFIG_PPC_PSERIES | |
133 | /* | |
134 | * Vectors for the FWNMI option. Share common code. | |
135 | */ | |
136 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
137 | SET_SCRATCH0(r13) /* save r13 */ | |
138 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, | |
139 | NOTEST, 0x100) | |
140 | #endif /* CONFIG_PPC_PSERIES */ | |
141 | ||
0ebc4cda | 142 | |
1a6822d1 | 143 | EXC_REAL_BEGIN(machine_check, 0x200, 0x100) |
b01c8b54 PM |
144 | /* This is moved out of line as it can be patched by FW, but |
145 | * some code path might still want to branch into the original | |
146 | * vector | |
147 | */ | |
1707dd16 PM |
148 | SET_SCRATCH0(r13) /* save r13 */ |
149 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
1e9b4507 | 150 | BEGIN_FTR_SECTION |
2513767d | 151 | b machine_check_powernv_early |
1e9b4507 | 152 | FTR_SECTION_ELSE |
1707dd16 | 153 | b machine_check_pSeries_0 |
1e9b4507 | 154 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 NP |
155 | EXC_REAL_END(machine_check, 0x200, 0x100) |
156 | EXC_VIRT_NONE(0x4200, 0x100) | |
afcf0095 NP |
157 | TRAMP_REAL_BEGIN(machine_check_powernv_early) |
158 | BEGIN_FTR_SECTION | |
159 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) | |
160 | /* | |
161 | * Register contents: | |
162 | * R13 = PACA | |
163 | * R9 = CR | |
164 | * Original R9 to R13 is saved on PACA_EXMC | |
165 | * | |
166 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
167 | * the nested MCE upto level 4 to avoid stack overflow). | |
168 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
169 | * | |
170 | * We use paca->in_mce to check whether this is the first entry or | |
171 | * nested machine check. We increment paca->in_mce to track nested | |
172 | * machine checks. | |
173 | * | |
174 | * If this is the first entry then set stack pointer to | |
175 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
176 | * stack frame on mc_emergency stack. | |
177 | * | |
178 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
179 | * checkstop if we get another machine check exception before we do | |
180 | * rfid with MSR_ME=1. | |
1945bc45 NP |
181 | * |
182 | * This interrupt can wake directly from idle. If that is the case, | |
183 | * the machine check is handled then the idle wakeup code is called | |
184 | * to restore state. In that case, the POWER9 DD1 idle PACA workaround | |
185 | * is not applied in the early machine check code, which will cause | |
186 | * bugs. | |
afcf0095 NP |
187 | */ |
188 | mr r11,r1 /* Save r1 */ | |
189 | lhz r10,PACA_IN_MCE(r13) | |
190 | cmpwi r10,0 /* Are we in nested machine check */ | |
191 | bne 0f /* Yes, we are. */ | |
192 | /* First machine check entry */ | |
193 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
194 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
195 | addi r10,r10,1 /* increment paca->in_mce */ | |
196 | sth r10,PACA_IN_MCE(r13) | |
197 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
198 | cmpwi r10,4 | |
199 | bgt 2f /* Check if we hit limit of 4 */ | |
200 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
201 | std r11,0(r1) /* make stack chain pointer */ | |
202 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
203 | std r11,_NIP(r1) | |
204 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
205 | std r11,_MSR(r1) | |
206 | mfspr r11,SPRN_DAR /* Save DAR */ | |
207 | std r11,_DAR(r1) | |
208 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
209 | std r11,_DSISR(r1) | |
210 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
211 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
212 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
213 | mfmsr r11 /* get MSR value */ | |
214 | ori r11,r11,MSR_ME /* turn on ME bit */ | |
215 | ori r11,r11,MSR_RI /* turn on RI bit */ | |
216 | LOAD_HANDLER(r12, machine_check_handle_early) | |
217 | 1: mtspr SPRN_SRR0,r12 | |
218 | mtspr SPRN_SRR1,r11 | |
219 | rfid | |
220 | b . /* prevent speculative execution */ | |
221 | 2: | |
222 | /* Stack overflow. Stay on emergency stack and panic. | |
223 | * Keep the ME bit off while panic-ing, so that if we hit | |
224 | * another machine check we checkstop. | |
225 | */ | |
226 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
227 | ld r11,PACAKMSR(r13) | |
228 | LOAD_HANDLER(r12, unrecover_mce) | |
229 | li r10,MSR_ME | |
230 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
231 | b 1b | |
232 | b . /* prevent speculative execution */ | |
233 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
234 | ||
235 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
236 | .globl machine_check_fwnmi | |
237 | machine_check_fwnmi: | |
238 | SET_SCRATCH0(r13) /* save r13 */ | |
239 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
240 | machine_check_pSeries_0: | |
241 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) | |
242 | /* | |
243 | * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the | |
244 | * difference that MSR_RI is not enabled, because PACA_EXMC is being | |
245 | * used, so nested machine check corrupts it. machine_check_common | |
246 | * enables MSR_RI. | |
247 | */ | |
248 | ld r10,PACAKMSR(r13) | |
249 | xori r10,r10,MSR_RI | |
250 | mfspr r11,SPRN_SRR0 | |
251 | LOAD_HANDLER(r12, machine_check_common) | |
252 | mtspr SPRN_SRR0,r12 | |
253 | mfspr r12,SPRN_SRR1 | |
254 | mtspr SPRN_SRR1,r10 | |
255 | rfid | |
256 | b . /* prevent speculative execution */ | |
257 | ||
258 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
259 | ||
260 | EXC_COMMON_BEGIN(machine_check_common) | |
261 | /* | |
262 | * Machine check is different because we use a different | |
263 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
264 | */ | |
265 | mfspr r10,SPRN_DAR | |
266 | std r10,PACA_EXMC+EX_DAR(r13) | |
267 | mfspr r10,SPRN_DSISR | |
268 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
269 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
270 | FINISH_NAP | |
271 | RECONCILE_IRQ_STATE(r10, r11) | |
272 | ld r3,PACA_EXMC+EX_DAR(r13) | |
273 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
274 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
275 | li r10,MSR_RI | |
276 | mtmsrd r10,1 | |
277 | std r3,_DAR(r1) | |
278 | std r4,_DSISR(r1) | |
279 | bl save_nvgprs | |
280 | addi r3,r1,STACK_FRAME_OVERHEAD | |
281 | bl machine_check_exception | |
282 | b ret_from_except | |
283 | ||
284 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
285 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
286 | li r0,MSR_RI; \ | |
287 | mfmsr r9; /* get MSR value */ \ | |
288 | andc r9,r9,r0; \ | |
289 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
290 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
291 | ld r9,_MSR(r1); \ | |
292 | mtspr SPRN_SRR1,r9; \ | |
293 | ld r3,_NIP(r1); \ | |
294 | mtspr SPRN_SRR0,r3; \ | |
295 | ld r9,_CTR(r1); \ | |
296 | mtctr r9; \ | |
297 | ld r9,_XER(r1); \ | |
298 | mtxer r9; \ | |
299 | ld r9,_LINK(r1); \ | |
300 | mtlr r9; \ | |
301 | REST_GPR(0, r1); \ | |
302 | REST_8GPRS(2, r1); \ | |
303 | REST_GPR(10, r1); \ | |
304 | ld r11,_CCR(r1); \ | |
305 | mtcr r11; \ | |
306 | /* Decrement paca->in_mce. */ \ | |
307 | lhz r12,PACA_IN_MCE(r13); \ | |
308 | subi r12,r12,1; \ | |
309 | sth r12,PACA_IN_MCE(r13); \ | |
310 | REST_GPR(11, r1); \ | |
311 | REST_2GPRS(12, r1); \ | |
312 | /* restore original r1. */ \ | |
313 | ld r1,GPR1(r1) | |
314 | ||
1945bc45 NP |
315 | #ifdef CONFIG_PPC_P7_NAP |
316 | /* | |
317 | * This is an idle wakeup. Low level machine check has already been | |
318 | * done. Queue the event then call the idle code to do the wake up. | |
319 | */ | |
320 | EXC_COMMON_BEGIN(machine_check_idle_common) | |
321 | bl machine_check_queue_event | |
322 | ||
323 | /* | |
324 | * We have not used any non-volatile GPRs here, and as a rule | |
325 | * most exception code including machine check does not. | |
326 | * Therefore PACA_NAPSTATELOST does not need to be set. Idle | |
327 | * wakeup will restore volatile registers. | |
328 | * | |
329 | * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. | |
330 | * | |
331 | * Then decrement MCE nesting after finishing with the stack. | |
332 | */ | |
333 | ld r3,_MSR(r1) | |
334 | ||
335 | lhz r11,PACA_IN_MCE(r13) | |
336 | subi r11,r11,1 | |
337 | sth r11,PACA_IN_MCE(r13) | |
338 | ||
339 | /* Turn off the RI bit because SRR1 is used by idle wakeup code. */ | |
340 | /* Recoverability could be improved by reducing the use of SRR1. */ | |
341 | li r11,0 | |
342 | mtmsrd r11,1 | |
343 | ||
344 | b pnv_powersave_wakeup_mce | |
345 | #endif | |
afcf0095 NP |
346 | /* |
347 | * Handle machine check early in real mode. We come here with | |
348 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
349 | */ | |
350 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
351 | std r0,GPR0(r1) /* Save r0 */ | |
352 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
353 | bl save_nvgprs | |
354 | addi r3,r1,STACK_FRAME_OVERHEAD | |
355 | bl machine_check_early | |
356 | std r3,RESULT(r1) /* Save result */ | |
357 | ld r12,_MSR(r1) | |
1945bc45 | 358 | |
afcf0095 NP |
359 | #ifdef CONFIG_PPC_P7_NAP |
360 | /* | |
361 | * Check if thread was in power saving mode. We come here when any | |
362 | * of the following is true: | |
363 | * a. thread wasn't in power saving mode | |
364 | * b. thread was in power saving mode with no state loss, | |
365 | * supervisor state loss or hypervisor state loss. | |
366 | * | |
367 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
368 | */ | |
1945bc45 NP |
369 | BEGIN_FTR_SECTION |
370 | rlwinm. r11,r12,47-31,30,31 | |
371 | beq- 4f | |
372 | BRANCH_TO_COMMON(r10, machine_check_idle_common) | |
afcf0095 | 373 | 4: |
1945bc45 | 374 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
afcf0095 | 375 | #endif |
1945bc45 | 376 | |
afcf0095 NP |
377 | /* |
378 | * Check if we are coming from hypervisor userspace. If yes then we | |
379 | * continue in host kernel in V mode to deliver the MC event. | |
380 | */ | |
381 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
382 | beq 5f | |
383 | andi. r11,r12,MSR_PR /* See if coming from user. */ | |
384 | bne 9f /* continue in V mode if we are. */ | |
385 | ||
386 | 5: | |
387 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
388 | /* | |
389 | * We are coming from kernel context. Check if we are coming from | |
390 | * guest. if yes, then we can continue. We will fall through | |
391 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
392 | */ | |
393 | lbz r11,HSTATE_IN_GUEST(r13) | |
394 | cmpwi r11,0 /* Check if coming from guest */ | |
395 | bne 9f /* continue if we are. */ | |
396 | #endif | |
397 | /* | |
398 | * At this point we are not sure about what context we come from. | |
399 | * Queue up the MCE event and return from the interrupt. | |
400 | * But before that, check if this is an un-recoverable exception. | |
401 | * If yes, then stay on emergency stack and panic. | |
402 | */ | |
403 | andi. r11,r12,MSR_RI | |
404 | bne 2f | |
405 | 1: mfspr r11,SPRN_SRR0 | |
406 | LOAD_HANDLER(r10,unrecover_mce) | |
407 | mtspr SPRN_SRR0,r10 | |
408 | ld r10,PACAKMSR(r13) | |
409 | /* | |
410 | * We are going down. But there are chances that we might get hit by | |
411 | * another MCE during panic path and we may run into unstable state | |
412 | * with no way out. Hence, turn ME bit off while going down, so that | |
413 | * when another MCE is hit during panic path, system will checkstop | |
414 | * and hypervisor will get restarted cleanly by SP. | |
415 | */ | |
416 | li r3,MSR_ME | |
417 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
418 | mtspr SPRN_SRR1,r10 | |
419 | rfid | |
420 | b . | |
421 | 2: | |
422 | /* | |
423 | * Check if we have successfully handled/recovered from error, if not | |
424 | * then stay on emergency stack and panic. | |
425 | */ | |
426 | ld r3,RESULT(r1) /* Load result */ | |
427 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
428 | ||
429 | beq 1b /* if !handled then panic */ | |
430 | /* | |
431 | * Return from MC interrupt. | |
432 | * Queue up the MCE event so that we can log it later, while | |
433 | * returning from kernel or opal call. | |
434 | */ | |
435 | bl machine_check_queue_event | |
436 | MACHINE_CHECK_HANDLER_WINDUP | |
437 | rfid | |
438 | 9: | |
439 | /* Deliver the machine check to host kernel in V mode. */ | |
440 | MACHINE_CHECK_HANDLER_WINDUP | |
441 | b machine_check_pSeries | |
442 | ||
443 | EXC_COMMON_BEGIN(unrecover_mce) | |
444 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
445 | addi r3,r1,STACK_FRAME_OVERHEAD | |
446 | bl machine_check_exception | |
447 | /* | |
448 | * We will not reach here. Even if we did, there is no way out. Call | |
449 | * unrecoverable_exception and die. | |
450 | */ | |
451 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
452 | bl unrecoverable_exception | |
453 | b 1b | |
454 | ||
0ebc4cda | 455 | |
1a6822d1 NP |
456 | EXC_REAL(data_access, 0x300, 0x80) |
457 | EXC_VIRT(data_access, 0x4300, 0x80, 0x300) | |
80795e6c NP |
458 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
459 | ||
460 | EXC_COMMON_BEGIN(data_access_common) | |
461 | /* | |
462 | * Here r13 points to the paca, r9 contains the saved CR, | |
463 | * SRR0 and SRR1 are saved in r11 and r12, | |
464 | * r9 - r13 are saved in paca->exgen. | |
465 | */ | |
466 | mfspr r10,SPRN_DAR | |
467 | std r10,PACA_EXGEN+EX_DAR(r13) | |
468 | mfspr r10,SPRN_DSISR | |
469 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
470 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
471 | RECONCILE_IRQ_STATE(r10, r11) | |
472 | ld r12,_MSR(r1) | |
473 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
474 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
475 | li r5,0x300 | |
476 | std r3,_DAR(r1) | |
477 | std r4,_DSISR(r1) | |
478 | BEGIN_MMU_FTR_SECTION | |
479 | b do_hash_page /* Try to handle as hpte fault */ | |
480 | MMU_FTR_SECTION_ELSE | |
481 | b handle_page_fault | |
482 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
483 | ||
0ebc4cda | 484 | |
1a6822d1 | 485 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) |
673b189a | 486 | SET_SCRATCH0(r13) |
1707dd16 | 487 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 488 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
0ebc4cda BH |
489 | std r3,PACA_EXSLB+EX_R3(r13) |
490 | mfspr r3,SPRN_DAR | |
b01c8b54 | 491 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 492 | crset 4*cr6+eq |
0ebc4cda | 493 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 494 | b slb_miss_realmode |
0ebc4cda BH |
495 | #else |
496 | /* | |
ad0289e4 | 497 | * We can't just use a direct branch to slb_miss_realmode |
0ebc4cda BH |
498 | * because the distance from here to there depends on where |
499 | * the kernel ends up being put. | |
500 | */ | |
501 | mfctr r11 | |
ad0289e4 | 502 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
503 | mtctr r10 |
504 | bctr | |
505 | #endif | |
1a6822d1 | 506 | EXC_REAL_END(data_access_slb, 0x380, 0x80) |
0ebc4cda | 507 | |
1a6822d1 | 508 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) |
2b9af6e4 NP |
509 | SET_SCRATCH0(r13) |
510 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
511 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) | |
512 | std r3,PACA_EXSLB+EX_R3(r13) | |
513 | mfspr r3,SPRN_DAR | |
514 | mfspr r12,SPRN_SRR1 | |
515 | crset 4*cr6+eq | |
516 | #ifndef CONFIG_RELOCATABLE | |
517 | b slb_miss_realmode | |
518 | #else | |
519 | /* | |
520 | * We can't just use a direct branch to slb_miss_realmode | |
521 | * because the distance from here to there depends on where | |
522 | * the kernel ends up being put. | |
523 | */ | |
524 | mfctr r11 | |
525 | LOAD_HANDLER(r10, slb_miss_realmode) | |
526 | mtctr r10 | |
527 | bctr | |
528 | #endif | |
1a6822d1 | 529 | EXC_VIRT_END(data_access_slb, 0x4380, 0x80) |
2b9af6e4 NP |
530 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
531 | ||
532 | ||
1a6822d1 NP |
533 | EXC_REAL(instruction_access, 0x400, 0x80) |
534 | EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) | |
27ce77df NP |
535 | TRAMP_KVM(PACA_EXGEN, 0x400) |
536 | ||
537 | EXC_COMMON_BEGIN(instruction_access_common) | |
538 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
539 | RECONCILE_IRQ_STATE(r10, r11) | |
540 | ld r12,_MSR(r1) | |
541 | ld r3,_NIP(r1) | |
542 | andis. r4,r12,0x5820 | |
543 | li r5,0x400 | |
544 | std r3,_DAR(r1) | |
545 | std r4,_DSISR(r1) | |
546 | BEGIN_MMU_FTR_SECTION | |
547 | b do_hash_page /* Try to handle as hpte fault */ | |
548 | MMU_FTR_SECTION_ELSE | |
549 | b handle_page_fault | |
550 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
551 | ||
0ebc4cda | 552 | |
1a6822d1 | 553 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) |
673b189a | 554 | SET_SCRATCH0(r13) |
1707dd16 | 555 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 556 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
557 | std r3,PACA_EXSLB+EX_R3(r13) |
558 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
b01c8b54 | 559 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 560 | crclr 4*cr6+eq |
0ebc4cda | 561 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 562 | b slb_miss_realmode |
0ebc4cda BH |
563 | #else |
564 | mfctr r11 | |
ad0289e4 | 565 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
566 | mtctr r10 |
567 | bctr | |
568 | #endif | |
1a6822d1 | 569 | EXC_REAL_END(instruction_access_slb, 0x480, 0x80) |
0ebc4cda | 570 | |
1a6822d1 | 571 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) |
8d04631a NP |
572 | SET_SCRATCH0(r13) |
573 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
574 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) | |
575 | std r3,PACA_EXSLB+EX_R3(r13) | |
576 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
577 | mfspr r12,SPRN_SRR1 | |
578 | crclr 4*cr6+eq | |
579 | #ifndef CONFIG_RELOCATABLE | |
580 | b slb_miss_realmode | |
581 | #else | |
582 | mfctr r11 | |
583 | LOAD_HANDLER(r10, slb_miss_realmode) | |
584 | mtctr r10 | |
585 | bctr | |
586 | #endif | |
1a6822d1 | 587 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) |
8d04631a NP |
588 | TRAMP_KVM(PACA_EXSLB, 0x480) |
589 | ||
590 | ||
591 | /* This handler is used by both 0x380 and 0x480 slb miss interrupts */ | |
592 | EXC_COMMON_BEGIN(slb_miss_realmode) | |
593 | /* | |
594 | * r13 points to the PACA, r9 contains the saved CR, | |
595 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
596 | * r3 has the faulting address | |
597 | * r9 - r13 are saved in paca->exslb. | |
598 | * r3 is saved in paca->slb_r3 | |
599 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss | |
600 | * We assume we aren't going to take any exceptions during this | |
601 | * procedure. | |
602 | */ | |
603 | mflr r10 | |
604 | #ifdef CONFIG_RELOCATABLE | |
605 | mtctr r11 | |
606 | #endif | |
607 | ||
608 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
609 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
610 | std r3,PACA_EXSLB+EX_DAR(r13) | |
611 | ||
612 | crset 4*cr0+eq | |
613 | #ifdef CONFIG_PPC_STD_MMU_64 | |
614 | BEGIN_MMU_FTR_SECTION | |
615 | bl slb_allocate_realmode | |
616 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) | |
617 | #endif | |
618 | ||
619 | ld r10,PACA_EXSLB+EX_LR(r13) | |
620 | ld r3,PACA_EXSLB+EX_R3(r13) | |
621 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
622 | mtlr r10 | |
623 | ||
624 | beq 8f /* if bad address, make full stack frame */ | |
625 | ||
626 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
627 | beq- 2f | |
628 | ||
629 | /* All done -- return from exception. */ | |
630 | ||
631 | .machine push | |
632 | .machine "power4" | |
633 | mtcrf 0x80,r9 | |
634 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ | |
635 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
636 | .machine pop | |
637 | ||
638 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
639 | ld r9,PACA_EXSLB+EX_R9(r13) | |
640 | ld r10,PACA_EXSLB+EX_R10(r13) | |
641 | ld r11,PACA_EXSLB+EX_R11(r13) | |
642 | ld r12,PACA_EXSLB+EX_R12(r13) | |
643 | ld r13,PACA_EXSLB+EX_R13(r13) | |
644 | rfid | |
645 | b . /* prevent speculative execution */ | |
646 | ||
647 | 2: mfspr r11,SPRN_SRR0 | |
648 | LOAD_HANDLER(r10,unrecov_slb) | |
649 | mtspr SPRN_SRR0,r10 | |
650 | ld r10,PACAKMSR(r13) | |
651 | mtspr SPRN_SRR1,r10 | |
652 | rfid | |
653 | b . | |
654 | ||
655 | 8: mfspr r11,SPRN_SRR0 | |
656 | LOAD_HANDLER(r10,bad_addr_slb) | |
657 | mtspr SPRN_SRR0,r10 | |
658 | ld r10,PACAKMSR(r13) | |
659 | mtspr SPRN_SRR1,r10 | |
660 | rfid | |
661 | b . | |
662 | ||
663 | EXC_COMMON_BEGIN(unrecov_slb) | |
664 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
665 | RECONCILE_IRQ_STATE(r10, r11) | |
666 | bl save_nvgprs | |
667 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
668 | bl unrecoverable_exception | |
669 | b 1b | |
670 | ||
671 | EXC_COMMON_BEGIN(bad_addr_slb) | |
672 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) | |
673 | RECONCILE_IRQ_STATE(r10, r11) | |
674 | ld r3, PACA_EXSLB+EX_DAR(r13) | |
675 | std r3, _DAR(r1) | |
676 | beq cr6, 2f | |
677 | li r10, 0x480 /* fix trap number for I-SLB miss */ | |
678 | std r10, _TRAP(r1) | |
679 | 2: bl save_nvgprs | |
680 | addi r3, r1, STACK_FRAME_OVERHEAD | |
681 | bl slb_miss_bad_addr | |
682 | b ret_from_except | |
683 | ||
1a6822d1 | 684 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) |
b3e6b5df | 685 | .globl hardware_interrupt_hv; |
b3e6b5df | 686 | hardware_interrupt_hv: |
a5d4f3ad | 687 | BEGIN_FTR_SECTION |
da2bc464 | 688 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
b01c8b54 | 689 | EXC_HV, SOFTEN_TEST_HV) |
de56a948 | 690 | FTR_SECTION_ELSE |
da2bc464 | 691 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
31a40e2b | 692 | EXC_STD, SOFTEN_TEST_PR) |
969391c5 | 693 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
1a6822d1 | 694 | EXC_REAL_END(hardware_interrupt, 0x500, 0x100) |
da2bc464 | 695 | |
1a6822d1 | 696 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) |
c138e588 NP |
697 | .globl hardware_interrupt_relon_hv; |
698 | hardware_interrupt_relon_hv: | |
699 | BEGIN_FTR_SECTION | |
700 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) | |
701 | FTR_SECTION_ELSE | |
702 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) | |
703 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1a6822d1 | 704 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) |
c138e588 | 705 | |
7ede5317 NP |
706 | TRAMP_KVM(PACA_EXGEN, 0x500) |
707 | TRAMP_KVM_HV(PACA_EXGEN, 0x500) | |
c138e588 NP |
708 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
709 | ||
710 | ||
1a6822d1 NP |
711 | EXC_REAL(alignment, 0x600, 0x100) |
712 | EXC_VIRT(alignment, 0x4600, 0x100, 0x600) | |
da2bc464 | 713 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 NP |
714 | EXC_COMMON_BEGIN(alignment_common) |
715 | mfspr r10,SPRN_DAR | |
716 | std r10,PACA_EXGEN+EX_DAR(r13) | |
717 | mfspr r10,SPRN_DSISR | |
718 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
719 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
720 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
721 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
722 | std r3,_DAR(r1) | |
723 | std r4,_DSISR(r1) | |
724 | bl save_nvgprs | |
725 | RECONCILE_IRQ_STATE(r10, r11) | |
726 | addi r3,r1,STACK_FRAME_OVERHEAD | |
727 | bl alignment_exception | |
728 | b ret_from_except | |
729 | ||
da2bc464 | 730 | |
1a6822d1 NP |
731 | EXC_REAL(program_check, 0x700, 0x100) |
732 | EXC_VIRT(program_check, 0x4700, 0x100, 0x700) | |
da2bc464 | 733 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 NP |
734 | EXC_COMMON_BEGIN(program_check_common) |
735 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
736 | bl save_nvgprs | |
737 | RECONCILE_IRQ_STATE(r10, r11) | |
738 | addi r3,r1,STACK_FRAME_OVERHEAD | |
739 | bl program_check_exception | |
740 | b ret_from_except | |
741 | ||
b01c8b54 | 742 | |
1a6822d1 NP |
743 | EXC_REAL(fp_unavailable, 0x800, 0x100) |
744 | EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) | |
da2bc464 | 745 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 NP |
746 | EXC_COMMON_BEGIN(fp_unavailable_common) |
747 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
748 | bne 1f /* if from user, just load it up */ | |
749 | bl save_nvgprs | |
750 | RECONCILE_IRQ_STATE(r10, r11) | |
751 | addi r3,r1,STACK_FRAME_OVERHEAD | |
752 | bl kernel_fp_unavailable_exception | |
753 | BUG_OPCODE | |
754 | 1: | |
755 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
756 | BEGIN_FTR_SECTION | |
757 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
758 | * transaction), go do TM stuff | |
759 | */ | |
760 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
761 | bne- 2f | |
762 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
763 | #endif | |
764 | bl load_up_fpu | |
765 | b fast_exception_return | |
766 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
767 | 2: /* User process was in a transaction */ | |
768 | bl save_nvgprs | |
769 | RECONCILE_IRQ_STATE(r10, r11) | |
770 | addi r3,r1,STACK_FRAME_OVERHEAD | |
771 | bl fp_unavailable_tm | |
772 | b ret_from_except | |
773 | #endif | |
774 | ||
a5d4f3ad | 775 | |
1a6822d1 NP |
776 | EXC_REAL_MASKABLE(decrementer, 0x900, 0x80) |
777 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900) | |
39c0da57 NP |
778 | TRAMP_KVM(PACA_EXGEN, 0x900) |
779 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
780 | ||
a485c709 | 781 | |
1a6822d1 NP |
782 | EXC_REAL_HV(hdecrementer, 0x980, 0x80) |
783 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) | |
facc6d74 NP |
784 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
785 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
786 | ||
a5d4f3ad | 787 | |
1a6822d1 NP |
788 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100) |
789 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00) | |
da2bc464 | 790 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
791 | #ifdef CONFIG_PPC_DOORBELL |
792 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
793 | #else | |
794 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
795 | #endif | |
796 | ||
0ebc4cda | 797 | |
1a6822d1 NP |
798 | EXC_REAL(trap_0b, 0xb00, 0x100) |
799 | EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) | |
da2bc464 | 800 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
801 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
802 | ||
bc355125 PM |
803 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
804 | /* | |
805 | * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems | |
806 | * that support it) before changing to HMT_MEDIUM. That allows the KVM | |
807 | * code to save that value into the guest state (it is the guest's PPR | |
808 | * value). Otherwise just change to HMT_MEDIUM as userspace has | |
809 | * already saved the PPR. | |
810 | */ | |
811 | #define SYSCALL_KVMTEST \ | |
812 | SET_SCRATCH0(r13); \ | |
813 | GET_PACA(r13); \ | |
814 | std r9,PACA_EXGEN+EX_R9(r13); \ | |
815 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ | |
816 | HMT_MEDIUM; \ | |
817 | std r10,PACA_EXGEN+EX_R10(r13); \ | |
818 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); \ | |
819 | mfcr r9; \ | |
820 | KVMTEST_PR(0xc00); \ | |
821 | GET_SCRATCH0(r13) | |
822 | ||
823 | #else | |
824 | #define SYSCALL_KVMTEST \ | |
825 | HMT_MEDIUM | |
826 | #endif | |
827 | ||
fb479e44 NP |
828 | #define LOAD_SYSCALL_HANDLER(reg) \ |
829 | __LOAD_HANDLER(reg, system_call_common) | |
d807ad37 NP |
830 | |
831 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ | |
832 | #define SYSCALL_PSERIES_1 \ | |
833 | BEGIN_FTR_SECTION \ | |
834 | cmpdi r0,0x1ebe ; \ | |
835 | beq- 1f ; \ | |
836 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
837 | mr r9,r13 ; \ | |
838 | GET_PACA(r13) ; \ | |
839 | mfspr r11,SPRN_SRR0 ; \ | |
840 | 0: | |
841 | ||
842 | #define SYSCALL_PSERIES_2_RFID \ | |
843 | mfspr r12,SPRN_SRR1 ; \ | |
844 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
845 | mtspr SPRN_SRR0,r10 ; \ | |
846 | ld r10,PACAKMSR(r13) ; \ | |
847 | mtspr SPRN_SRR1,r10 ; \ | |
848 | rfid ; \ | |
849 | b . ; /* prevent speculative execution */ | |
850 | ||
851 | #define SYSCALL_PSERIES_3 \ | |
852 | /* Fast LE/BE switch system call */ \ | |
853 | 1: mfspr r12,SPRN_SRR1 ; \ | |
854 | xori r12,r12,MSR_LE ; \ | |
855 | mtspr SPRN_SRR1,r12 ; \ | |
856 | rfid ; /* return to userspace */ \ | |
857 | b . ; /* prevent speculative execution */ | |
858 | ||
859 | #if defined(CONFIG_RELOCATABLE) | |
860 | /* | |
861 | * We can't branch directly so we do it via the CTR which | |
862 | * is volatile across system calls. | |
863 | */ | |
864 | #define SYSCALL_PSERIES_2_DIRECT \ | |
865 | LOAD_SYSCALL_HANDLER(r12) ; \ | |
866 | mtctr r12 ; \ | |
867 | mfspr r12,SPRN_SRR1 ; \ | |
868 | li r10,MSR_RI ; \ | |
869 | mtmsrd r10,1 ; \ | |
870 | bctr ; | |
871 | #else | |
872 | /* We can branch directly */ | |
873 | #define SYSCALL_PSERIES_2_DIRECT \ | |
874 | mfspr r12,SPRN_SRR1 ; \ | |
875 | li r10,MSR_RI ; \ | |
876 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
877 | b system_call_common ; | |
878 | #endif | |
879 | ||
1a6822d1 | 880 | EXC_REAL_BEGIN(system_call, 0xc00, 0x100) |
bc355125 | 881 | SYSCALL_KVMTEST |
742415d6 MN |
882 | SYSCALL_PSERIES_1 |
883 | SYSCALL_PSERIES_2_RFID | |
884 | SYSCALL_PSERIES_3 | |
1a6822d1 | 885 | EXC_REAL_END(system_call, 0xc00, 0x100) |
da2bc464 | 886 | |
1a6822d1 | 887 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) |
bc355125 | 888 | SYSCALL_KVMTEST |
d807ad37 NP |
889 | SYSCALL_PSERIES_1 |
890 | SYSCALL_PSERIES_2_DIRECT | |
891 | SYSCALL_PSERIES_3 | |
1a6822d1 | 892 | EXC_VIRT_END(system_call, 0x4c00, 0x100) |
d807ad37 | 893 | |
da2bc464 ME |
894 | TRAMP_KVM(PACA_EXGEN, 0xc00) |
895 | ||
d807ad37 | 896 | |
1a6822d1 NP |
897 | EXC_REAL(single_step, 0xd00, 0x100) |
898 | EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) | |
da2bc464 | 899 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 900 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 901 | |
1a6822d1 | 902 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) |
da0e7e62 | 903 | EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) |
f5c32c1d NP |
904 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
905 | EXC_COMMON_BEGIN(h_data_storage_common) | |
906 | mfspr r10,SPRN_HDAR | |
907 | std r10,PACA_EXGEN+EX_DAR(r13) | |
908 | mfspr r10,SPRN_HDSISR | |
909 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
910 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
911 | bl save_nvgprs | |
912 | RECONCILE_IRQ_STATE(r10, r11) | |
913 | addi r3,r1,STACK_FRAME_OVERHEAD | |
914 | bl unknown_exception | |
915 | b ret_from_except | |
f5c32c1d | 916 | |
1707dd16 | 917 | |
1a6822d1 | 918 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) |
da0e7e62 | 919 | EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) |
82517cab NP |
920 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
921 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
922 | ||
1707dd16 | 923 | |
1a6822d1 NP |
924 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) |
925 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) | |
031b4026 NP |
926 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
927 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
928 | ||
1707dd16 | 929 | |
e0319829 NP |
930 | /* |
931 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
932 | * first, and then eventaully from there to the trampoline to get into virtual | |
933 | * mode. | |
934 | */ | |
1a6822d1 | 935 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) |
852e5da9 | 936 | __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
1a6822d1 | 937 | EXC_VIRT_NONE(0x4e60, 0x20) |
62f9b03b NP |
938 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
939 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
940 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) | |
941 | mr r10,r1 /* Save r1 */ | |
942 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
943 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
944 | std r9,_CCR(r1) /* save CR in stackframe */ | |
945 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ | |
946 | std r11,_NIP(r1) /* save HSRR0 in stackframe */ | |
947 | mfspr r12,SPRN_HSRR1 /* Save SRR1 */ | |
948 | std r12,_MSR(r1) /* save SRR1 in stackframe */ | |
949 | std r10,0(r1) /* make stack chain pointer */ | |
950 | std r0,GPR0(r1) /* save r0 in stackframe */ | |
951 | std r10,GPR1(r1) /* save r1 in stackframe */ | |
952 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) | |
953 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
954 | addi r3,r1,STACK_FRAME_OVERHEAD | |
2337d207 | 955 | BRANCH_LINK_TO_FAR(r4, hmi_exception_realmode) |
62f9b03b NP |
956 | /* Windup the stack. */ |
957 | /* Move original HSRR0 and HSRR1 into the respective regs */ | |
958 | ld r9,_MSR(r1) | |
959 | mtspr SPRN_HSRR1,r9 | |
960 | ld r3,_NIP(r1) | |
961 | mtspr SPRN_HSRR0,r3 | |
962 | ld r9,_CTR(r1) | |
963 | mtctr r9 | |
964 | ld r9,_XER(r1) | |
965 | mtxer r9 | |
966 | ld r9,_LINK(r1) | |
967 | mtlr r9 | |
968 | REST_GPR(0, r1) | |
969 | REST_8GPRS(2, r1) | |
970 | REST_GPR(10, r1) | |
971 | ld r11,_CCR(r1) | |
972 | mtcr r11 | |
973 | REST_GPR(11, r1) | |
974 | REST_2GPRS(12, r1) | |
975 | /* restore original r1. */ | |
976 | ld r1,GPR1(r1) | |
977 | ||
978 | /* | |
979 | * Go to virtual mode and pull the HMI event information from | |
980 | * firmware. | |
981 | */ | |
982 | .globl hmi_exception_after_realmode | |
983 | hmi_exception_after_realmode: | |
984 | SET_SCRATCH0(r13) | |
985 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
986 | b tramp_real_hmi_exception | |
987 | ||
988 | EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) | |
989 | ||
1707dd16 | 990 | |
1a6822d1 NP |
991 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20) |
992 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80) | |
9bcb81bf NP |
993 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
994 | #ifdef CONFIG_PPC_DOORBELL | |
995 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
996 | #else | |
997 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
998 | #endif | |
999 | ||
0ebc4cda | 1000 | |
1a6822d1 NP |
1001 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20) |
1002 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0) | |
74408776 NP |
1003 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1004 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1005 | ||
9baaef0a | 1006 | |
1a6822d1 NP |
1007 | EXC_REAL_NONE(0xec0, 0x20) |
1008 | EXC_VIRT_NONE(0x4ec0, 0x20) | |
1009 | EXC_REAL_NONE(0xee0, 0x20) | |
1010 | EXC_VIRT_NONE(0x4ee0, 0x20) | |
bda7fea2 | 1011 | |
0ebc4cda | 1012 | |
1a6822d1 NP |
1013 | EXC_REAL_OOL(performance_monitor, 0xf00, 0x20) |
1014 | EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00) | |
b1c7f150 NP |
1015 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1016 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1017 | ||
0ebc4cda | 1018 | |
1a6822d1 NP |
1019 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) |
1020 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) | |
d1a0ca9c NP |
1021 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1022 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
1023 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1024 | #ifdef CONFIG_ALTIVEC | |
1025 | BEGIN_FTR_SECTION | |
1026 | beq 1f | |
1027 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1028 | BEGIN_FTR_SECTION_NESTED(69) | |
1029 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1030 | * transaction), go do TM stuff | |
1031 | */ | |
1032 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1033 | bne- 2f | |
1034 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1035 | #endif | |
1036 | bl load_up_altivec | |
1037 | b fast_exception_return | |
1038 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1039 | 2: /* User process was in a transaction */ | |
1040 | bl save_nvgprs | |
1041 | RECONCILE_IRQ_STATE(r10, r11) | |
1042 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1043 | bl altivec_unavailable_tm | |
1044 | b ret_from_except | |
1045 | #endif | |
1046 | 1: | |
1047 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1048 | #endif | |
1049 | bl save_nvgprs | |
1050 | RECONCILE_IRQ_STATE(r10, r11) | |
1051 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1052 | bl altivec_unavailable_exception | |
1053 | b ret_from_except | |
1054 | ||
0ebc4cda | 1055 | |
1a6822d1 NP |
1056 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) |
1057 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) | |
792cbddd NP |
1058 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1059 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
1060 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1061 | #ifdef CONFIG_VSX | |
1062 | BEGIN_FTR_SECTION | |
1063 | beq 1f | |
1064 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1065 | BEGIN_FTR_SECTION_NESTED(69) | |
1066 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1067 | * transaction), go do TM stuff | |
1068 | */ | |
1069 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1070 | bne- 2f | |
1071 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1072 | #endif | |
1073 | b load_up_vsx | |
1074 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1075 | 2: /* User process was in a transaction */ | |
1076 | bl save_nvgprs | |
1077 | RECONCILE_IRQ_STATE(r10, r11) | |
1078 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1079 | bl vsx_unavailable_tm | |
1080 | b ret_from_except | |
1081 | #endif | |
1082 | 1: | |
1083 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1084 | #endif | |
1085 | bl save_nvgprs | |
1086 | RECONCILE_IRQ_STATE(r10, r11) | |
1087 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1088 | bl vsx_unavailable_exception | |
1089 | b ret_from_except | |
1090 | ||
da2bc464 | 1091 | |
1a6822d1 NP |
1092 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) |
1093 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) | |
1134713c NP |
1094 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1095 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1096 | ||
da2bc464 | 1097 | |
1a6822d1 NP |
1098 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) |
1099 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) | |
14b0072c NP |
1100 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1101 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1102 | ||
da2bc464 | 1103 | |
1a6822d1 NP |
1104 | EXC_REAL_NONE(0xfa0, 0x20) |
1105 | EXC_VIRT_NONE(0x4fa0, 0x20) | |
1106 | EXC_REAL_NONE(0xfc0, 0x20) | |
1107 | EXC_VIRT_NONE(0x4fc0, 0x20) | |
1108 | EXC_REAL_NONE(0xfe0, 0x20) | |
1109 | EXC_VIRT_NONE(0x4fe0, 0x20) | |
1110 | ||
1111 | EXC_REAL_NONE(0x1000, 0x100) | |
1112 | EXC_VIRT_NONE(0x5000, 0x100) | |
1113 | EXC_REAL_NONE(0x1100, 0x100) | |
1114 | EXC_VIRT_NONE(0x5100, 0x100) | |
d0c0c9a1 | 1115 | |
0ebc4cda | 1116 | #ifdef CONFIG_CBE_RAS |
1a6822d1 NP |
1117 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) |
1118 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1119 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1120 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1121 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1122 | EXC_REAL_NONE(0x1200, 0x100) |
1123 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1124 | #endif |
b01c8b54 | 1125 | |
ff1b3206 | 1126 | |
1a6822d1 NP |
1127 | EXC_REAL(instruction_breakpoint, 0x1300, 0x100) |
1128 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) | |
da2bc464 | 1129 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1130 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1131 | ||
1a6822d1 NP |
1132 | EXC_REAL_NONE(0x1400, 0x100) |
1133 | EXC_VIRT_NONE(0x5400, 0x100) | |
da2bc464 | 1134 | |
1a6822d1 | 1135 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) |
b92a66a6 | 1136 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 1137 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 1138 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
1139 | |
1140 | #ifdef CONFIG_PPC_DENORMALISATION | |
1141 | mfspr r10,SPRN_HSRR1 | |
1142 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
afcf0095 NP |
1143 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
1144 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
1145 | bne+ denorm_assist | |
1146 | #endif | |
1e9b4507 | 1147 | |
afcf0095 NP |
1148 | KVMTEST_PR(0x1500) |
1149 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) | |
1a6822d1 | 1150 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) |
a74599a5 | 1151 | |
d7e89849 | 1152 | #ifdef CONFIG_PPC_DENORMALISATION |
1a6822d1 | 1153 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1154 | b exc_real_0x1500_denorm_exception_hv |
1a6822d1 | 1155 | EXC_VIRT_END(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1156 | #else |
1a6822d1 | 1157 | EXC_VIRT_NONE(0x5500, 0x100) |
afcf0095 NP |
1158 | #endif |
1159 | ||
d7e89849 | 1160 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) |
b01c8b54 | 1161 | |
b92a66a6 | 1162 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1163 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1164 | BEGIN_FTR_SECTION |
1165 | /* | |
1166 | * To denormalise we need to move a copy of the register to itself. | |
1167 | * For POWER6 do that here for all FP regs. | |
1168 | */ | |
1169 | mfmsr r10 | |
1170 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
1171 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
1172 | mtmsrd r10 | |
1173 | sync | |
d7c67fb1 MN |
1174 | |
1175 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
1176 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
1177 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
1178 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
1179 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
1180 | FMR32(0) | |
1181 | ||
b92a66a6 MN |
1182 | FTR_SECTION_ELSE |
1183 | /* | |
1184 | * To denormalise we need to move a copy of the register to itself. | |
1185 | * For POWER7 do that here for the first 32 VSX registers only. | |
1186 | */ | |
1187 | mfmsr r10 | |
1188 | oris r10,r10,MSR_VSX@h | |
1189 | mtmsrd r10 | |
1190 | sync | |
d7c67fb1 MN |
1191 | |
1192 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
1193 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
1194 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
1195 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
1196 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
1197 | XVCPSGNDP32(0) | |
1198 | ||
b92a66a6 | 1199 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1200 | |
1201 | BEGIN_FTR_SECTION | |
1202 | b denorm_done | |
1203 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1204 | /* | |
1205 | * To denormalise we need to move a copy of the register to itself. | |
1206 | * For POWER8 we need to do that for all 64 VSX registers | |
1207 | */ | |
1208 | XVCPSGNDP32(32) | |
1209 | denorm_done: | |
b92a66a6 MN |
1210 | mtspr SPRN_HSRR0,r11 |
1211 | mtcrf 0x80,r9 | |
1212 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1213 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1214 | BEGIN_FTR_SECTION |
1215 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1216 | mtspr SPRN_CFAR,r10 | |
1217 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1218 | ld r10,PACA_EXGEN+EX_R10(r13) |
1219 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1220 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1221 | ld r13,PACA_EXGEN+EX_R13(r13) | |
1222 | HRFID | |
1223 | b . | |
1224 | #endif | |
1225 | ||
d7e89849 NP |
1226 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
1227 | ||
1228 | ||
1229 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1230 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) |
1231 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 | 1232 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 1233 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 | 1234 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1235 | EXC_REAL_NONE(0x1600, 0x100) |
1236 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 NP |
1237 | #endif |
1238 | ||
69a79344 | 1239 | |
1a6822d1 NP |
1240 | EXC_REAL(altivec_assist, 0x1700, 0x100) |
1241 | EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) | |
d7e89849 | 1242 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
1243 | #ifdef CONFIG_ALTIVEC |
1244 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
1245 | #else | |
1246 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
1247 | #endif | |
1248 | ||
d7e89849 NP |
1249 | |
1250 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1251 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) |
1252 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 | 1253 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 1254 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 | 1255 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1256 | EXC_REAL_NONE(0x1800, 0x100) |
1257 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 NP |
1258 | #endif |
1259 | ||
1260 | ||
0ebc4cda | 1261 | /* |
fe9e1d54 IM |
1262 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
1263 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
1264 | * - If it was a doorbell we return immediately since doorbells are edge | |
1265 | * triggered and won't automatically refire. | |
0869b6fd MS |
1266 | * - If it was a HMI we return immediately since we handled it in realmode |
1267 | * and it won't refire. | |
fe9e1d54 IM |
1268 | * - else we hard disable and return. |
1269 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 1270 | */ |
7230c564 BH |
1271 | #define MASKED_INTERRUPT(_H) \ |
1272 | masked_##_H##interrupt: \ | |
1273 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
1274 | lbz r11,PACAIRQHAPPENED(r13); \ | |
1275 | or r11,r11,r10; \ | |
1276 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
1277 | cmpwi r10,PACA_IRQ_DEC; \ |
1278 | bne 1f; \ | |
7230c564 BH |
1279 | lis r10,0x7fff; \ |
1280 | ori r10,r10,0xffff; \ | |
1281 | mtspr SPRN_DEC,r10; \ | |
1282 | b 2f; \ | |
fe9e1d54 | 1283 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
0869b6fd MS |
1284 | beq 2f; \ |
1285 | cmpwi r10,PACA_IRQ_HMI; \ | |
fe9e1d54 IM |
1286 | beq 2f; \ |
1287 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
1288 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
1289 | rotldi r10,r10,16; \ | |
1290 | mtspr SPRN_##_H##SRR1,r10; \ | |
1291 | 2: mtcrf 0x80,r9; \ | |
1292 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
1293 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
1294 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
1295 | GET_SCRATCH0(r13); \ | |
1296 | ##_H##rfid; \ | |
0ebc4cda | 1297 | b . |
57f26649 NP |
1298 | |
1299 | /* | |
1300 | * Real mode exceptions actually use this too, but alternate | |
1301 | * instruction code patches (which end up in the common .text area) | |
1302 | * cannot reach these if they are put there. | |
1303 | */ | |
1304 | USE_FIXED_SECTION(virt_trampolines) | |
7230c564 BH |
1305 | MASKED_INTERRUPT() |
1306 | MASKED_INTERRUPT(H) | |
0ebc4cda | 1307 | |
4f6c11db | 1308 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 1309 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
1310 | /* |
1311 | * Here all GPRs are unchanged from when the interrupt happened | |
1312 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1313 | */ | |
1314 | mfspr r13, SPRN_SRR0 | |
1315 | addi r13, r13, 4 | |
1316 | mtspr SPRN_SRR0, r13 | |
1317 | GET_SCRATCH0(r13) | |
1318 | rfid | |
1319 | b . | |
1320 | ||
da2bc464 | 1321 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
1322 | /* |
1323 | * Here all GPRs are unchanged from when the interrupt happened | |
1324 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1325 | */ | |
1326 | mfspr r13, SPRN_HSRR0 | |
1327 | addi r13, r13, 4 | |
1328 | mtspr SPRN_HSRR0, r13 | |
1329 | GET_SCRATCH0(r13) | |
1330 | hrfid | |
1331 | b . | |
1332 | #endif | |
1333 | ||
0ebc4cda | 1334 | /* |
057b6d7e HB |
1335 | * Ensure that any handlers that get invoked from the exception prologs |
1336 | * above are below the first 64KB (0x10000) of the kernel image because | |
1337 | * the prologs assemble the addresses of these handlers using the | |
1338 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
1339 | */ |
1340 | ||
1341 | /*** Common interrupt handlers ***/ | |
1342 | ||
0ebc4cda | 1343 | |
c1fb6816 MN |
1344 | /* |
1345 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
1346 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
1347 | * it. Addresses are the same as the original interrupt addresses, but | |
1348 | * offset by 0xc000000000004000. | |
1349 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
1350 | * KVM: None of these traps are from the guest ; anything that escalated | |
1351 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
1352 | */ | |
1353 | ||
1354 | /* | |
1355 | * This uses the standard macro, since the original 0x300 vector | |
1356 | * only has extra guff for STAB-based processors -- which never | |
1357 | * come here. | |
1358 | */ | |
da2bc464 | 1359 | |
57f26649 | 1360 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 1361 | b __ppc64_runlatch_on |
fe1952fc | 1362 | |
57f26649 | 1363 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1364 | /* |
1365 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1366 | * handlers, so that they are copied to real address 0x100 when running | |
1367 | * a relocatable kernel. This ensures they can be reached from the short | |
1368 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1369 | * directly, without using LOAD_HANDLER(). | |
1370 | */ | |
1371 | .align 7 | |
1372 | .globl __end_interrupts | |
1373 | __end_interrupts: | |
57f26649 | 1374 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1375 | |
087aa036 | 1376 | #ifdef CONFIG_PPC_970_NAP |
7c8cb4b5 | 1377 | EXC_COMMON_BEGIN(power4_fixup_nap) |
087aa036 CG |
1378 | andc r9,r9,r10 |
1379 | std r9,TI_LOCAL_FLAGS(r11) | |
1380 | ld r10,_LINK(r1) /* make idle task do the */ | |
1381 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1382 | blr | |
1383 | #endif | |
1384 | ||
57f26649 NP |
1385 | CLOSE_FIXED_SECTION(real_vectors); |
1386 | CLOSE_FIXED_SECTION(real_trampolines); | |
1387 | CLOSE_FIXED_SECTION(virt_vectors); | |
1388 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1389 | ||
1390 | USE_TEXT_SECTION() | |
1391 | ||
0ebc4cda BH |
1392 | /* |
1393 | * Hash table stuff | |
1394 | */ | |
f4329f2e | 1395 | .balign IFETCH_ALIGN_BYTES |
6a3bab90 | 1396 | do_hash_page: |
caca285e | 1397 | #ifdef CONFIG_PPC_STD_MMU_64 |
9c7cc234 | 1398 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1399 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1400 | andis. r0,r4,DSISR_DABRMATCH@h |
1401 | bne- handle_dabr_fault | |
9778b696 | 1402 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1403 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1404 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1405 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1406 | |
1407 | /* | |
1408 | * r3 contains the faulting address | |
106713a1 | 1409 | * r4 msr |
0ebc4cda | 1410 | * r5 contains the trap number |
aefa5688 | 1411 | * r6 contains dsisr |
0ebc4cda | 1412 | * |
7230c564 | 1413 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1414 | */ |
106713a1 | 1415 | mr r4,r12 |
aefa5688 | 1416 | ld r6,_DSISR(r1) |
106713a1 AK |
1417 | bl __hash_page /* build HPTE if possible */ |
1418 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1419 | |
7230c564 | 1420 | /* Success */ |
0ebc4cda | 1421 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1422 | |
7230c564 BH |
1423 | /* Error */ |
1424 | blt- 13f | |
caca285e | 1425 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
9c7cc234 | 1426 | |
0ebc4cda BH |
1427 | /* Here we have a page fault that hash_page can't handle. */ |
1428 | handle_page_fault: | |
0ebc4cda BH |
1429 | 11: ld r4,_DAR(r1) |
1430 | ld r5,_DSISR(r1) | |
1431 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1432 | bl do_page_fault |
0ebc4cda | 1433 | cmpdi r3,0 |
a546498f | 1434 | beq+ 12f |
b1576fec | 1435 | bl save_nvgprs |
0ebc4cda BH |
1436 | mr r5,r3 |
1437 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1438 | lwz r4,_DAR(r1) | |
b1576fec AB |
1439 | bl bad_page_fault |
1440 | b ret_from_except | |
0ebc4cda | 1441 | |
a546498f BH |
1442 | /* We have a data breakpoint exception - handle it */ |
1443 | handle_dabr_fault: | |
b1576fec | 1444 | bl save_nvgprs |
a546498f BH |
1445 | ld r4,_DAR(r1) |
1446 | ld r5,_DSISR(r1) | |
1447 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1448 | bl do_break |
1449 | 12: b ret_from_except_lite | |
a546498f | 1450 | |
0ebc4cda | 1451 | |
caca285e | 1452 | #ifdef CONFIG_PPC_STD_MMU_64 |
0ebc4cda BH |
1453 | /* We have a page fault that hash_page could handle but HV refused |
1454 | * the PTE insertion | |
1455 | */ | |
b1576fec | 1456 | 13: bl save_nvgprs |
0ebc4cda BH |
1457 | mr r5,r3 |
1458 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1459 | ld r4,_DAR(r1) | |
b1576fec AB |
1460 | bl low_hash_fault |
1461 | b ret_from_except | |
caca285e | 1462 | #endif |
0ebc4cda | 1463 | |
9c1e1052 PM |
1464 | /* |
1465 | * We come here as a result of a DSI at a point where we don't want | |
1466 | * to call hash_page, such as when we are accessing memory (possibly | |
1467 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1468 | * were soft-disabled. We want to invoke the exception handler for | |
1469 | * the access, or panic if there isn't a handler. | |
1470 | */ | |
b1576fec | 1471 | 77: bl save_nvgprs |
9c1e1052 PM |
1472 | mr r4,r3 |
1473 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1474 | li r5,SIGSEGV | |
b1576fec AB |
1475 | bl bad_page_fault |
1476 | b ret_from_except | |
4e2bf01b ME |
1477 | |
1478 | /* | |
1479 | * Here we have detected that the kernel stack pointer is bad. | |
1480 | * R9 contains the saved CR, r13 points to the paca, | |
1481 | * r10 contains the (bad) kernel stack pointer, | |
1482 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1483 | * We switch to using an emergency stack, save the registers there, | |
1484 | * and call kernel_bad_stack(), which panics. | |
1485 | */ | |
1486 | bad_stack: | |
1487 | ld r1,PACAEMERGSP(r13) | |
1488 | subi r1,r1,64+INT_FRAME_SIZE | |
1489 | std r9,_CCR(r1) | |
1490 | std r10,GPR1(r1) | |
1491 | std r11,_NIP(r1) | |
1492 | std r12,_MSR(r1) | |
1493 | mfspr r11,SPRN_DAR | |
1494 | mfspr r12,SPRN_DSISR | |
1495 | std r11,_DAR(r1) | |
1496 | std r12,_DSISR(r1) | |
1497 | mflr r10 | |
1498 | mfctr r11 | |
1499 | mfxer r12 | |
1500 | std r10,_LINK(r1) | |
1501 | std r11,_CTR(r1) | |
1502 | std r12,_XER(r1) | |
1503 | SAVE_GPR(0,r1) | |
1504 | SAVE_GPR(2,r1) | |
1505 | ld r10,EX_R3(r3) | |
1506 | std r10,GPR3(r1) | |
1507 | SAVE_GPR(4,r1) | |
1508 | SAVE_4GPRS(5,r1) | |
1509 | ld r9,EX_R9(r3) | |
1510 | ld r10,EX_R10(r3) | |
1511 | SAVE_2GPRS(9,r1) | |
1512 | ld r9,EX_R11(r3) | |
1513 | ld r10,EX_R12(r3) | |
1514 | ld r11,EX_R13(r3) | |
1515 | std r9,GPR11(r1) | |
1516 | std r10,GPR12(r1) | |
1517 | std r11,GPR13(r1) | |
1518 | BEGIN_FTR_SECTION | |
1519 | ld r10,EX_CFAR(r3) | |
1520 | std r10,ORIG_GPR3(r1) | |
1521 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1522 | SAVE_8GPRS(14,r1) | |
1523 | SAVE_10GPRS(22,r1) | |
1524 | lhz r12,PACA_TRAP_SAVE(r13) | |
1525 | std r12,_TRAP(r1) | |
1526 | addi r11,r1,INT_FRAME_SIZE | |
1527 | std r11,0(r1) | |
1528 | li r12,0 | |
1529 | std r12,0(r11) | |
1530 | ld r2,PACATOC(r13) | |
1531 | ld r11,exception_marker@toc(r2) | |
1532 | std r12,RESULT(r1) | |
1533 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1534 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1535 | bl kernel_bad_stack | |
1536 | b 1b | |
0f0c6ca1 NP |
1537 | |
1538 | /* | |
1539 | * Called from arch_local_irq_enable when an interrupt needs | |
1540 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
1541 | * which kind of interrupt. MSR:EE is already off. We generate a | |
1542 | * stackframe like if a real interrupt had happened. | |
1543 | * | |
1544 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
1545 | * in the generated frame has EE set to 1 or the exception | |
1546 | * handler will not properly re-enable them. | |
1547 | */ | |
1548 | _GLOBAL(__replay_interrupt) | |
1549 | /* We are going to jump to the exception common code which | |
1550 | * will retrieve various register values from the PACA which | |
1551 | * we don't give a damn about, so we don't bother storing them. | |
1552 | */ | |
1553 | mfmsr r12 | |
1554 | mflr r11 | |
1555 | mfcr r9 | |
1556 | ori r12,r12,MSR_EE | |
1557 | cmpwi r3,0x900 | |
1558 | beq decrementer_common | |
1559 | cmpwi r3,0x500 | |
1560 | beq hardware_interrupt_common | |
1561 | BEGIN_FTR_SECTION | |
1562 | cmpwi r3,0xe80 | |
1563 | beq h_doorbell_common | |
1564 | cmpwi r3,0xea0 | |
1565 | beq h_virt_irq_common | |
1566 | cmpwi r3,0xe60 | |
1567 | beq hmi_exception_common | |
1568 | FTR_SECTION_ELSE | |
1569 | cmpwi r3,0xa00 | |
1570 | beq doorbell_super_common | |
1571 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1572 | blr |