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Commit | Line | Data |
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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
8aa34ab8 | 18 | |
0ebc4cda BH |
19 | /* |
20 | * We layout physical memory as follows: | |
21 | * 0x0000 - 0x00ff : Secondary processor spin code | |
c1fb6816 MN |
22 | * 0x0100 - 0x17ff : pSeries Interrupt prologs |
23 | * 0x1800 - 0x4000 : interrupt support common interrupt prologs | |
24 | * 0x4000 - 0x5fff : pSeries interrupts with IR=1,DR=1 | |
25 | * 0x6000 - 0x6fff : more interrupt support including for IR=1,DR=1 | |
0ebc4cda | 26 | * 0x7000 - 0x7fff : FWNMI data area |
c1fb6816 MN |
27 | * 0x8000 - 0x8fff : Initial (CPU0) segment table |
28 | * 0x9000 - : Early init and support code | |
0ebc4cda | 29 | */ |
742415d6 MN |
30 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ |
31 | #define SYSCALL_PSERIES_1 \ | |
32 | BEGIN_FTR_SECTION \ | |
33 | cmpdi r0,0x1ebe ; \ | |
34 | beq- 1f ; \ | |
35 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
36 | mr r9,r13 ; \ | |
37 | GET_PACA(r13) ; \ | |
38 | mfspr r11,SPRN_SRR0 ; \ | |
39 | 0: | |
40 | ||
41 | #define SYSCALL_PSERIES_2_RFID \ | |
42 | mfspr r12,SPRN_SRR1 ; \ | |
43 | ld r10,PACAKBASE(r13) ; \ | |
44 | LOAD_HANDLER(r10, system_call_entry) ; \ | |
45 | mtspr SPRN_SRR0,r10 ; \ | |
46 | ld r10,PACAKMSR(r13) ; \ | |
47 | mtspr SPRN_SRR1,r10 ; \ | |
48 | rfid ; \ | |
49 | b . ; /* prevent speculative execution */ | |
50 | ||
51 | #define SYSCALL_PSERIES_3 \ | |
52 | /* Fast LE/BE switch system call */ \ | |
53 | 1: mfspr r12,SPRN_SRR1 ; \ | |
54 | xori r12,r12,MSR_LE ; \ | |
55 | mtspr SPRN_SRR1,r12 ; \ | |
56 | rfid ; /* return to userspace */ \ | |
742415d6 MN |
57 | b . ; /* prevent speculative execution */ |
58 | ||
4700dfaf MN |
59 | #if defined(CONFIG_RELOCATABLE) |
60 | /* | |
61 | * We can't branch directly; in the direct case we use LR | |
62 | * and system_call_entry restores LR. (We thus need to move | |
63 | * LR to r10 in the RFID case too.) | |
64 | */ | |
65 | #define SYSCALL_PSERIES_2_DIRECT \ | |
66 | mflr r10 ; \ | |
67 | ld r12,PACAKBASE(r13) ; \ | |
68 | LOAD_HANDLER(r12, system_call_entry_direct) ; \ | |
6a404806 | 69 | mtctr r12 ; \ |
4700dfaf MN |
70 | mfspr r12,SPRN_SRR1 ; \ |
71 | /* Re-use of r13... No spare regs to do this */ \ | |
72 | li r13,MSR_RI ; \ | |
73 | mtmsrd r13,1 ; \ | |
74 | GET_PACA(r13) ; /* get r13 back */ \ | |
6a404806 | 75 | bctr ; |
4700dfaf MN |
76 | #else |
77 | /* We can branch directly */ | |
78 | #define SYSCALL_PSERIES_2_DIRECT \ | |
79 | mfspr r12,SPRN_SRR1 ; \ | |
80 | li r10,MSR_RI ; \ | |
81 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
82 | b system_call_entry_direct ; | |
83 | #endif | |
0ebc4cda | 84 | |
0ebc4cda BH |
85 | /* |
86 | * This is the start of the interrupt handlers for pSeries | |
87 | * This code runs with relocation off. | |
88 | * Code from here to __end_interrupts gets copied down to real | |
89 | * address 0x100 when we are running a relocatable kernel. | |
90 | * Therefore any relative branches in this section must only | |
91 | * branch to labels in this section. | |
92 | */ | |
93 | . = 0x100 | |
94 | .globl __start_interrupts | |
95 | __start_interrupts: | |
96 | ||
948cf67c BH |
97 | .globl system_reset_pSeries; |
98 | system_reset_pSeries: | |
44e9309f | 99 | HMT_MEDIUM_PPR_DISCARD |
948cf67c BH |
100 | SET_SCRATCH0(r13) |
101 | #ifdef CONFIG_PPC_P7_NAP | |
102 | BEGIN_FTR_SECTION | |
103 | /* Running native on arch 2.06 or later, check if we are | |
104 | * waking up from nap. We only handle no state loss and | |
105 | * supervisor state loss. We do -not- handle hypervisor | |
106 | * state loss at this time. | |
107 | */ | |
108 | mfspr r13,SPRN_SRR1 | |
371fefd6 PM |
109 | rlwinm. r13,r13,47-31,30,31 |
110 | beq 9f | |
111 | ||
112 | /* waking up from powersave (nap) state */ | |
113 | cmpwi cr1,r13,2 | |
948cf67c BH |
114 | /* Total loss of HV state is fatal, we could try to use the |
115 | * PIR to locate a PACA, then use an emergency stack etc... | |
aca79d2b VS |
116 | * OPAL v3 based powernv platforms have new idle states |
117 | * which fall in this catagory. | |
948cf67c | 118 | */ |
aca79d2b | 119 | bgt cr1,8f |
371fefd6 PM |
120 | GET_PACA(r13) |
121 | ||
3a167bea | 122 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
f0888f70 PM |
123 | li r0,KVM_HWTHREAD_IN_KERNEL |
124 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
125 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
126 | sync | |
127 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
128 | cmpwi r0,0 | |
129 | beq 1f | |
371fefd6 PM |
130 | b kvm_start_guest |
131 | 1: | |
132 | #endif | |
133 | ||
134 | beq cr1,2f | |
b1576fec AB |
135 | b power7_wakeup_noloss |
136 | 2: b power7_wakeup_loss | |
aca79d2b VS |
137 | |
138 | /* Fast Sleep wakeup on PowerNV */ | |
139 | 8: GET_PACA(r13) | |
b1576fec | 140 | b power7_wakeup_tb_loss |
aca79d2b | 141 | |
371fefd6 | 142 | 9: |
969391c5 | 143 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
948cf67c | 144 | #endif /* CONFIG_PPC_P7_NAP */ |
b01c8b54 PM |
145 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
146 | NOTEST, 0x100) | |
0ebc4cda BH |
147 | |
148 | . = 0x200 | |
b01c8b54 PM |
149 | machine_check_pSeries_1: |
150 | /* This is moved out of line as it can be patched by FW, but | |
151 | * some code path might still want to branch into the original | |
152 | * vector | |
153 | */ | |
1707dd16 PM |
154 | HMT_MEDIUM_PPR_DISCARD |
155 | SET_SCRATCH0(r13) /* save r13 */ | |
1c51089f MS |
156 | #ifdef CONFIG_PPC_P7_NAP |
157 | BEGIN_FTR_SECTION | |
158 | /* Running native on arch 2.06 or later, check if we are | |
159 | * waking up from nap. We only handle no state loss and | |
160 | * supervisor state loss. We do -not- handle hypervisor | |
161 | * state loss at this time. | |
162 | */ | |
163 | mfspr r13,SPRN_SRR1 | |
164 | rlwinm. r13,r13,47-31,30,31 | |
d410ae21 | 165 | OPT_GET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR) |
1c51089f MS |
166 | beq 9f |
167 | ||
d410ae21 MS |
168 | mfspr r13,SPRN_SRR1 |
169 | rlwinm. r13,r13,47-31,30,31 | |
1c51089f MS |
170 | /* waking up from powersave (nap) state */ |
171 | cmpwi cr1,r13,2 | |
172 | /* Total loss of HV state is fatal. let's just stay stuck here */ | |
d410ae21 | 173 | OPT_GET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR) |
1c51089f MS |
174 | bgt cr1,. |
175 | 9: | |
d410ae21 | 176 | OPT_SET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR) |
1c51089f MS |
177 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
178 | #endif /* CONFIG_PPC_P7_NAP */ | |
1707dd16 | 179 | EXCEPTION_PROLOG_0(PACA_EXMC) |
1e9b4507 MS |
180 | BEGIN_FTR_SECTION |
181 | b machine_check_pSeries_early | |
182 | FTR_SECTION_ELSE | |
1707dd16 | 183 | b machine_check_pSeries_0 |
1e9b4507 | 184 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
0ebc4cda BH |
185 | |
186 | . = 0x300 | |
187 | .globl data_access_pSeries | |
188 | data_access_pSeries: | |
44e9309f | 189 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 190 | SET_SCRATCH0(r13) |
b01c8b54 | 191 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD, |
697d3899 | 192 | KVMTEST, 0x300) |
0ebc4cda BH |
193 | |
194 | . = 0x380 | |
195 | .globl data_access_slb_pSeries | |
196 | data_access_slb_pSeries: | |
44e9309f | 197 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 198 | SET_SCRATCH0(r13) |
1707dd16 | 199 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
697d3899 | 200 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST, 0x380) |
0ebc4cda BH |
201 | std r3,PACA_EXSLB+EX_R3(r13) |
202 | mfspr r3,SPRN_DAR | |
0ebc4cda BH |
203 | #ifdef __DISABLED__ |
204 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
205 | cmpdi r3,0 | |
206 | bge slb_miss_user_pseries | |
207 | #endif /* __DISABLED__ */ | |
b01c8b54 | 208 | mfspr r12,SPRN_SRR1 |
0ebc4cda | 209 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 210 | b slb_miss_realmode |
0ebc4cda BH |
211 | #else |
212 | /* | |
ad0289e4 | 213 | * We can't just use a direct branch to slb_miss_realmode |
0ebc4cda BH |
214 | * because the distance from here to there depends on where |
215 | * the kernel ends up being put. | |
216 | */ | |
217 | mfctr r11 | |
218 | ld r10,PACAKBASE(r13) | |
ad0289e4 | 219 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
220 | mtctr r10 |
221 | bctr | |
222 | #endif | |
223 | ||
b3e6b5df | 224 | STD_EXCEPTION_PSERIES(0x400, 0x400, instruction_access) |
0ebc4cda BH |
225 | |
226 | . = 0x480 | |
227 | .globl instruction_access_slb_pSeries | |
228 | instruction_access_slb_pSeries: | |
44e9309f | 229 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 230 | SET_SCRATCH0(r13) |
1707dd16 | 231 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
de56a948 | 232 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
233 | std r3,PACA_EXSLB+EX_R3(r13) |
234 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
0ebc4cda BH |
235 | #ifdef __DISABLED__ |
236 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
237 | cmpdi r3,0 | |
238 | bge slb_miss_user_pseries | |
239 | #endif /* __DISABLED__ */ | |
b01c8b54 | 240 | mfspr r12,SPRN_SRR1 |
0ebc4cda | 241 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 242 | b slb_miss_realmode |
0ebc4cda BH |
243 | #else |
244 | mfctr r11 | |
245 | ld r10,PACAKBASE(r13) | |
ad0289e4 | 246 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
247 | mtctr r10 |
248 | bctr | |
249 | #endif | |
250 | ||
b3e6b5df BH |
251 | /* We open code these as we can't have a ". = x" (even with |
252 | * x = "." within a feature section | |
253 | */ | |
a5d4f3ad | 254 | . = 0x500; |
b3e6b5df BH |
255 | .globl hardware_interrupt_pSeries; |
256 | .globl hardware_interrupt_hv; | |
a5d4f3ad | 257 | hardware_interrupt_pSeries: |
b3e6b5df | 258 | hardware_interrupt_hv: |
a485c709 | 259 | HMT_MEDIUM_PPR_DISCARD |
a5d4f3ad | 260 | BEGIN_FTR_SECTION |
b01c8b54 PM |
261 | _MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt, |
262 | EXC_HV, SOFTEN_TEST_HV) | |
263 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) | |
de56a948 PM |
264 | FTR_SECTION_ELSE |
265 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, | |
9e368f29 | 266 | EXC_STD, SOFTEN_TEST_HV_201) |
de56a948 | 267 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
969391c5 | 268 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
a5d4f3ad | 269 | |
b3e6b5df | 270 | STD_EXCEPTION_PSERIES(0x600, 0x600, alignment) |
de56a948 | 271 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x600) |
b01c8b54 | 272 | |
b3e6b5df | 273 | STD_EXCEPTION_PSERIES(0x700, 0x700, program_check) |
de56a948 | 274 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x700) |
b01c8b54 | 275 | |
b3e6b5df | 276 | STD_EXCEPTION_PSERIES(0x800, 0x800, fp_unavailable) |
de56a948 | 277 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x800) |
a5d4f3ad | 278 | |
a485c709 PM |
279 | . = 0x900 |
280 | .globl decrementer_pSeries | |
281 | decrementer_pSeries: | |
282 | _MASKABLE_EXCEPTION_PSERIES(0x900, decrementer, EXC_STD, SOFTEN_TEST_PR) | |
283 | ||
dabe859e | 284 | STD_EXCEPTION_HV(0x980, 0x982, hdecrementer) |
a5d4f3ad | 285 | |
1dbdafec | 286 | MASKABLE_EXCEPTION_PSERIES(0xa00, 0xa00, doorbell_super) |
de56a948 | 287 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xa00) |
b01c8b54 | 288 | |
b3e6b5df | 289 | STD_EXCEPTION_PSERIES(0xb00, 0xb00, trap_0b) |
de56a948 | 290 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xb00) |
0ebc4cda BH |
291 | |
292 | . = 0xc00 | |
293 | .globl system_call_pSeries | |
294 | system_call_pSeries: | |
295 | HMT_MEDIUM | |
b01c8b54 PM |
296 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
297 | SET_SCRATCH0(r13) | |
298 | GET_PACA(r13) | |
299 | std r9,PACA_EXGEN+EX_R9(r13) | |
300 | std r10,PACA_EXGEN+EX_R10(r13) | |
301 | mfcr r9 | |
302 | KVMTEST(0xc00) | |
303 | GET_SCRATCH0(r13) | |
304 | #endif | |
742415d6 MN |
305 | SYSCALL_PSERIES_1 |
306 | SYSCALL_PSERIES_2_RFID | |
307 | SYSCALL_PSERIES_3 | |
b01c8b54 PM |
308 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) |
309 | ||
b3e6b5df | 310 | STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step) |
de56a948 | 311 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xd00) |
b3e6b5df BH |
312 | |
313 | /* At 0xe??? we have a bunch of hypervisor exceptions, we branch | |
314 | * out of line to handle them | |
315 | */ | |
316 | . = 0xe00 | |
d671ddd6 | 317 | hv_data_storage_trampoline: |
1707dd16 PM |
318 | SET_SCRATCH0(r13) |
319 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 320 | b h_data_storage_hv |
1707dd16 | 321 | |
b3e6b5df | 322 | . = 0xe20 |
d671ddd6 | 323 | hv_instr_storage_trampoline: |
1707dd16 PM |
324 | SET_SCRATCH0(r13) |
325 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 326 | b h_instr_storage_hv |
1707dd16 | 327 | |
b3e6b5df | 328 | . = 0xe40 |
d671ddd6 | 329 | emulation_assist_trampoline: |
1707dd16 PM |
330 | SET_SCRATCH0(r13) |
331 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 332 | b emulation_assist_hv |
1707dd16 | 333 | |
b3e6b5df | 334 | . = 0xe60 |
d671ddd6 | 335 | hv_exception_trampoline: |
1707dd16 PM |
336 | SET_SCRATCH0(r13) |
337 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 338 | b hmi_exception_hv |
1707dd16 | 339 | |
655bb3f4 | 340 | . = 0xe80 |
d671ddd6 | 341 | hv_doorbell_trampoline: |
1707dd16 PM |
342 | SET_SCRATCH0(r13) |
343 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
655bb3f4 | 344 | b h_doorbell_hv |
0ebc4cda BH |
345 | |
346 | /* We need to deal with the Altivec unavailable exception | |
347 | * here which is at 0xf20, thus in the middle of the | |
348 | * prolog code of the PerformanceMonitor one. A little | |
349 | * trickery is thus necessary | |
350 | */ | |
351 | . = 0xf00 | |
fa111f1f | 352 | performance_monitor_pseries_trampoline: |
1707dd16 PM |
353 | SET_SCRATCH0(r13) |
354 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
0ebc4cda BH |
355 | b performance_monitor_pSeries |
356 | ||
357 | . = 0xf20 | |
fa111f1f | 358 | altivec_unavailable_pseries_trampoline: |
1707dd16 PM |
359 | SET_SCRATCH0(r13) |
360 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
0ebc4cda BH |
361 | b altivec_unavailable_pSeries |
362 | ||
363 | . = 0xf40 | |
fa111f1f | 364 | vsx_unavailable_pseries_trampoline: |
1707dd16 PM |
365 | SET_SCRATCH0(r13) |
366 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
0ebc4cda BH |
367 | b vsx_unavailable_pSeries |
368 | ||
d0c0c9a1 | 369 | . = 0xf60 |
fa111f1f | 370 | facility_unavailable_trampoline: |
d0c0c9a1 MN |
371 | SET_SCRATCH0(r13) |
372 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
021424a1 | 373 | b facility_unavailable_pSeries |
d0c0c9a1 | 374 | |
b14b6260 | 375 | . = 0xf80 |
fa111f1f | 376 | hv_facility_unavailable_trampoline: |
b14b6260 ME |
377 | SET_SCRATCH0(r13) |
378 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
379 | b facility_unavailable_hv | |
380 | ||
0ebc4cda | 381 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 382 | STD_EXCEPTION_HV(0x1200, 0x1202, cbe_system_error) |
5ccf55dd | 383 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1202) |
0ebc4cda | 384 | #endif /* CONFIG_CBE_RAS */ |
b01c8b54 | 385 | |
b3e6b5df | 386 | STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint) |
de56a948 | 387 | KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x1300) |
b01c8b54 | 388 | |
b92a66a6 | 389 | . = 0x1500 |
51cf2b30 | 390 | .global denorm_exception_hv |
b92a66a6 | 391 | denorm_exception_hv: |
44e9309f | 392 | HMT_MEDIUM_PPR_DISCARD |
b92a66a6 | 393 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 394 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 395 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
396 | |
397 | #ifdef CONFIG_PPC_DENORMALISATION | |
398 | mfspr r10,SPRN_HSRR1 | |
399 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
400 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ | |
401 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
402 | bne+ denorm_assist | |
403 | #endif | |
404 | ||
630573c1 | 405 | KVMTEST(0x1500) |
b92a66a6 MN |
406 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) |
407 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x1500) | |
408 | ||
0ebc4cda | 409 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 410 | STD_EXCEPTION_HV(0x1600, 0x1602, cbe_maintenance) |
5ccf55dd | 411 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1602) |
0ebc4cda | 412 | #endif /* CONFIG_CBE_RAS */ |
b01c8b54 | 413 | |
b3e6b5df | 414 | STD_EXCEPTION_PSERIES(0x1700, 0x1700, altivec_assist) |
de56a948 | 415 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x1700) |
b01c8b54 | 416 | |
0ebc4cda | 417 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 418 | STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal) |
5ccf55dd | 419 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1802) |
faab4dd2 MN |
420 | #else |
421 | . = 0x1800 | |
0ebc4cda BH |
422 | #endif /* CONFIG_CBE_RAS */ |
423 | ||
0ebc4cda | 424 | |
b3e6b5df BH |
425 | /*** Out of line interrupts support ***/ |
426 | ||
faab4dd2 | 427 | .align 7 |
b01c8b54 | 428 | /* moved from 0x200 */ |
1e9b4507 MS |
429 | machine_check_pSeries_early: |
430 | BEGIN_FTR_SECTION | |
431 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) | |
432 | /* | |
433 | * Register contents: | |
434 | * R13 = PACA | |
435 | * R9 = CR | |
436 | * Original R9 to R13 is saved on PACA_EXMC | |
437 | * | |
e75ad93a MS |
438 | * Switch to mc_emergency stack and handle re-entrancy (we limit |
439 | * the nested MCE upto level 4 to avoid stack overflow). | |
440 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
1e9b4507 MS |
441 | * |
442 | * We use paca->in_mce to check whether this is the first entry or | |
443 | * nested machine check. We increment paca->in_mce to track nested | |
444 | * machine checks. | |
445 | * | |
446 | * If this is the first entry then set stack pointer to | |
447 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
448 | * stack frame on mc_emergency stack. | |
449 | * | |
450 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
451 | * checkstop if we get another machine check exception before we do | |
452 | * rfid with MSR_ME=1. | |
453 | */ | |
454 | mr r11,r1 /* Save r1 */ | |
455 | lhz r10,PACA_IN_MCE(r13) | |
456 | cmpwi r10,0 /* Are we in nested machine check */ | |
457 | bne 0f /* Yes, we are. */ | |
458 | /* First machine check entry */ | |
459 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
460 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
461 | addi r10,r10,1 /* increment paca->in_mce */ | |
462 | sth r10,PACA_IN_MCE(r13) | |
e75ad93a MS |
463 | /* Limit nested MCE to level 4 to avoid stack overflow */ |
464 | cmpwi r10,4 | |
465 | bgt 2f /* Check if we hit limit of 4 */ | |
1e9b4507 MS |
466 | std r11,GPR1(r1) /* Save r1 on the stack. */ |
467 | std r11,0(r1) /* make stack chain pointer */ | |
468 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
469 | std r11,_NIP(r1) | |
470 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
471 | std r11,_MSR(r1) | |
472 | mfspr r11,SPRN_DAR /* Save DAR */ | |
473 | std r11,_DAR(r1) | |
474 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
475 | std r11,_DSISR(r1) | |
476 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
477 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
478 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
479 | mfmsr r11 /* get MSR value */ | |
480 | ori r11,r11,MSR_ME /* turn on ME bit */ | |
481 | ori r11,r11,MSR_RI /* turn on RI bit */ | |
482 | ld r12,PACAKBASE(r13) /* get high part of &label */ | |
483 | LOAD_HANDLER(r12, machine_check_handle_early) | |
e75ad93a | 484 | 1: mtspr SPRN_SRR0,r12 |
1e9b4507 MS |
485 | mtspr SPRN_SRR1,r11 |
486 | rfid | |
487 | b . /* prevent speculative execution */ | |
e75ad93a MS |
488 | 2: |
489 | /* Stack overflow. Stay on emergency stack and panic. | |
490 | * Keep the ME bit off while panic-ing, so that if we hit | |
491 | * another machine check we checkstop. | |
492 | */ | |
493 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
494 | ld r11,PACAKMSR(r13) | |
495 | ld r12,PACAKBASE(r13) | |
496 | LOAD_HANDLER(r12, unrecover_mce) | |
497 | li r10,MSR_ME | |
498 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
499 | b 1b | |
500 | b . /* prevent speculative execution */ | |
1e9b4507 MS |
501 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
502 | ||
b01c8b54 PM |
503 | machine_check_pSeries: |
504 | .globl machine_check_fwnmi | |
505 | machine_check_fwnmi: | |
44e9309f | 506 | HMT_MEDIUM_PPR_DISCARD |
b01c8b54 | 507 | SET_SCRATCH0(r13) /* save r13 */ |
1707dd16 PM |
508 | EXCEPTION_PROLOG_0(PACA_EXMC) |
509 | machine_check_pSeries_0: | |
510 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST, 0x200) | |
511 | EXCEPTION_PROLOG_PSERIES_1(machine_check_common, EXC_STD) | |
b01c8b54 | 512 | KVM_HANDLER_SKIP(PACA_EXMC, EXC_STD, 0x200) |
697d3899 PM |
513 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x300) |
514 | KVM_HANDLER_SKIP(PACA_EXSLB, EXC_STD, 0x380) | |
de56a948 PM |
515 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x400) |
516 | KVM_HANDLER_PR(PACA_EXSLB, EXC_STD, 0x480) | |
517 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x900) | |
b01c8b54 PM |
518 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x982) |
519 | ||
b92a66a6 MN |
520 | #ifdef CONFIG_PPC_DENORMALISATION |
521 | denorm_assist: | |
522 | BEGIN_FTR_SECTION | |
523 | /* | |
524 | * To denormalise we need to move a copy of the register to itself. | |
525 | * For POWER6 do that here for all FP regs. | |
526 | */ | |
527 | mfmsr r10 | |
528 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
529 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
530 | mtmsrd r10 | |
531 | sync | |
d7c67fb1 MN |
532 | |
533 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
534 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
535 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
536 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
537 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
538 | FMR32(0) | |
539 | ||
b92a66a6 MN |
540 | FTR_SECTION_ELSE |
541 | /* | |
542 | * To denormalise we need to move a copy of the register to itself. | |
543 | * For POWER7 do that here for the first 32 VSX registers only. | |
544 | */ | |
545 | mfmsr r10 | |
546 | oris r10,r10,MSR_VSX@h | |
547 | mtmsrd r10 | |
548 | sync | |
d7c67fb1 MN |
549 | |
550 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
551 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
552 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
553 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
554 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
555 | XVCPSGNDP32(0) | |
556 | ||
b92a66a6 | 557 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
558 | |
559 | BEGIN_FTR_SECTION | |
560 | b denorm_done | |
561 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
562 | /* | |
563 | * To denormalise we need to move a copy of the register to itself. | |
564 | * For POWER8 we need to do that for all 64 VSX registers | |
565 | */ | |
566 | XVCPSGNDP32(32) | |
567 | denorm_done: | |
b92a66a6 MN |
568 | mtspr SPRN_HSRR0,r11 |
569 | mtcrf 0x80,r9 | |
570 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 571 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
572 | BEGIN_FTR_SECTION |
573 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
574 | mtspr SPRN_CFAR,r10 | |
575 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
576 | ld r10,PACA_EXGEN+EX_R10(r13) |
577 | ld r11,PACA_EXGEN+EX_R11(r13) | |
578 | ld r12,PACA_EXGEN+EX_R12(r13) | |
579 | ld r13,PACA_EXGEN+EX_R13(r13) | |
580 | HRFID | |
581 | b . | |
582 | #endif | |
583 | ||
b01c8b54 | 584 | .align 7 |
b3e6b5df | 585 | /* moved from 0xe00 */ |
1707dd16 | 586 | STD_EXCEPTION_HV_OOL(0xe02, h_data_storage) |
b01c8b54 | 587 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0xe02) |
1707dd16 | 588 | STD_EXCEPTION_HV_OOL(0xe22, h_instr_storage) |
b01c8b54 | 589 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe22) |
1707dd16 | 590 | STD_EXCEPTION_HV_OOL(0xe42, emulation_assist) |
b01c8b54 | 591 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe42) |
1707dd16 | 592 | STD_EXCEPTION_HV_OOL(0xe62, hmi_exception) /* need to flush cache ? */ |
b01c8b54 | 593 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe62) |
1707dd16 | 594 | MASKABLE_EXCEPTION_HV_OOL(0xe82, h_doorbell) |
655bb3f4 | 595 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe82) |
0ebc4cda BH |
596 | |
597 | /* moved from 0xf00 */ | |
1707dd16 | 598 | STD_EXCEPTION_PSERIES_OOL(0xf00, performance_monitor) |
de56a948 | 599 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf00) |
1707dd16 | 600 | STD_EXCEPTION_PSERIES_OOL(0xf20, altivec_unavailable) |
de56a948 | 601 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf20) |
1707dd16 | 602 | STD_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable) |
de56a948 | 603 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf40) |
021424a1 | 604 | STD_EXCEPTION_PSERIES_OOL(0xf60, facility_unavailable) |
d0c0c9a1 | 605 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf60) |
b14b6260 ME |
606 | STD_EXCEPTION_HV_OOL(0xf82, facility_unavailable) |
607 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xf82) | |
0ebc4cda BH |
608 | |
609 | /* | |
fe9e1d54 IM |
610 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
611 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
612 | * - If it was a doorbell we return immediately since doorbells are edge | |
613 | * triggered and won't automatically refire. | |
614 | * - else we hard disable and return. | |
615 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 616 | */ |
7230c564 BH |
617 | #define MASKED_INTERRUPT(_H) \ |
618 | masked_##_H##interrupt: \ | |
619 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
620 | lbz r11,PACAIRQHAPPENED(r13); \ | |
621 | or r11,r11,r10; \ | |
622 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
623 | cmpwi r10,PACA_IRQ_DEC; \ |
624 | bne 1f; \ | |
7230c564 BH |
625 | lis r10,0x7fff; \ |
626 | ori r10,r10,0xffff; \ | |
627 | mtspr SPRN_DEC,r10; \ | |
628 | b 2f; \ | |
fe9e1d54 IM |
629 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
630 | beq 2f; \ | |
631 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
632 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
633 | rotldi r10,r10,16; \ | |
634 | mtspr SPRN_##_H##SRR1,r10; \ | |
635 | 2: mtcrf 0x80,r9; \ | |
636 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
637 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
638 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
639 | GET_SCRATCH0(r13); \ | |
640 | ##_H##rfid; \ | |
0ebc4cda | 641 | b . |
7230c564 BH |
642 | |
643 | MASKED_INTERRUPT() | |
644 | MASKED_INTERRUPT(H) | |
0ebc4cda | 645 | |
7230c564 BH |
646 | /* |
647 | * Called from arch_local_irq_enable when an interrupt needs | |
fe9e1d54 IM |
648 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate |
649 | * which kind of interrupt. MSR:EE is already off. We generate a | |
7230c564 BH |
650 | * stackframe like if a real interrupt had happened. |
651 | * | |
652 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
653 | * in the generated frame has EE set to 1 or the exception | |
654 | * handler will not properly re-enable them. | |
655 | */ | |
656 | _GLOBAL(__replay_interrupt) | |
657 | /* We are going to jump to the exception common code which | |
658 | * will retrieve various register values from the PACA which | |
659 | * we don't give a damn about, so we don't bother storing them. | |
660 | */ | |
661 | mfmsr r12 | |
662 | mflr r11 | |
663 | mfcr r9 | |
664 | ori r12,r12,MSR_EE | |
fe9e1d54 IM |
665 | cmpwi r3,0x900 |
666 | beq decrementer_common | |
667 | cmpwi r3,0x500 | |
668 | beq hardware_interrupt_common | |
669 | BEGIN_FTR_SECTION | |
670 | cmpwi r3,0xe80 | |
671 | beq h_doorbell_common | |
672 | FTR_SECTION_ELSE | |
673 | cmpwi r3,0xa00 | |
674 | beq doorbell_super_common | |
675 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
676 | blr | |
a5d4f3ad | 677 | |
0ebc4cda BH |
678 | #ifdef CONFIG_PPC_PSERIES |
679 | /* | |
680 | * Vectors for the FWNMI option. Share common code. | |
681 | */ | |
682 | .globl system_reset_fwnmi | |
683 | .align 7 | |
684 | system_reset_fwnmi: | |
44e9309f | 685 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 686 | SET_SCRATCH0(r13) /* save r13 */ |
b01c8b54 PM |
687 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
688 | NOTEST, 0x100) | |
0ebc4cda BH |
689 | |
690 | #endif /* CONFIG_PPC_PSERIES */ | |
691 | ||
692 | #ifdef __DISABLED__ | |
693 | /* | |
694 | * This is used for when the SLB miss handler has to go virtual, | |
695 | * which doesn't happen for now anymore but will once we re-implement | |
696 | * dynamic VSIDs for shared page tables | |
697 | */ | |
698 | slb_miss_user_pseries: | |
699 | std r10,PACA_EXGEN+EX_R10(r13) | |
700 | std r11,PACA_EXGEN+EX_R11(r13) | |
701 | std r12,PACA_EXGEN+EX_R12(r13) | |
673b189a | 702 | GET_SCRATCH0(r10) |
0ebc4cda BH |
703 | ld r11,PACA_EXSLB+EX_R9(r13) |
704 | ld r12,PACA_EXSLB+EX_R3(r13) | |
705 | std r10,PACA_EXGEN+EX_R13(r13) | |
706 | std r11,PACA_EXGEN+EX_R9(r13) | |
707 | std r12,PACA_EXGEN+EX_R3(r13) | |
708 | clrrdi r12,r13,32 | |
709 | mfmsr r10 | |
710 | mfspr r11,SRR0 /* save SRR0 */ | |
711 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
712 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
713 | mtspr SRR0,r12 | |
714 | mfspr r12,SRR1 /* and SRR1 */ | |
715 | mtspr SRR1,r10 | |
716 | rfid | |
717 | b . /* prevent spec. execution */ | |
718 | #endif /* __DISABLED__ */ | |
719 | ||
4f6c11db PM |
720 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
721 | kvmppc_skip_interrupt: | |
722 | /* | |
723 | * Here all GPRs are unchanged from when the interrupt happened | |
724 | * except for r13, which is saved in SPRG_SCRATCH0. | |
725 | */ | |
726 | mfspr r13, SPRN_SRR0 | |
727 | addi r13, r13, 4 | |
728 | mtspr SPRN_SRR0, r13 | |
729 | GET_SCRATCH0(r13) | |
730 | rfid | |
731 | b . | |
732 | ||
733 | kvmppc_skip_Hinterrupt: | |
734 | /* | |
735 | * Here all GPRs are unchanged from when the interrupt happened | |
736 | * except for r13, which is saved in SPRG_SCRATCH0. | |
737 | */ | |
738 | mfspr r13, SPRN_HSRR0 | |
739 | addi r13, r13, 4 | |
740 | mtspr SPRN_HSRR0, r13 | |
741 | GET_SCRATCH0(r13) | |
742 | hrfid | |
743 | b . | |
744 | #endif | |
745 | ||
0ebc4cda BH |
746 | /* |
747 | * Code from here down to __end_handlers is invoked from the | |
748 | * exception prologs above. Because the prologs assemble the | |
749 | * addresses of these handlers using the LOAD_HANDLER macro, | |
61e2390e MN |
750 | * which uses an ori instruction, these handlers must be in |
751 | * the first 64k of the kernel image. | |
0ebc4cda BH |
752 | */ |
753 | ||
754 | /*** Common interrupt handlers ***/ | |
755 | ||
35425501 | 756 | STD_EXCEPTION_COMMON(0x100, system_reset, system_reset_exception) |
0ebc4cda | 757 | |
7450f6f0 | 758 | STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt, do_IRQ) |
35425501 AB |
759 | STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, timer_interrupt) |
760 | STD_EXCEPTION_COMMON(0x980, hdecrementer, hdec_interrupt) | |
1dbdafec | 761 | #ifdef CONFIG_PPC_DOORBELL |
35425501 | 762 | STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, doorbell_exception) |
1dbdafec | 763 | #else |
35425501 | 764 | STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, unknown_exception) |
1dbdafec | 765 | #endif |
35425501 AB |
766 | STD_EXCEPTION_COMMON(0xb00, trap_0b, unknown_exception) |
767 | STD_EXCEPTION_COMMON(0xd00, single_step, single_step_exception) | |
768 | STD_EXCEPTION_COMMON(0xe00, trap_0e, unknown_exception) | |
769 | STD_EXCEPTION_COMMON(0xe40, emulation_assist, emulation_assist_interrupt) | |
770 | STD_EXCEPTION_COMMON(0xe60, hmi_exception, unknown_exception) | |
655bb3f4 | 771 | #ifdef CONFIG_PPC_DOORBELL |
35425501 | 772 | STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, doorbell_exception) |
655bb3f4 | 773 | #else |
35425501 | 774 | STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, unknown_exception) |
655bb3f4 | 775 | #endif |
35425501 AB |
776 | STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, performance_monitor_exception) |
777 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, instruction_breakpoint_exception) | |
778 | STD_EXCEPTION_COMMON(0x1502, denorm, unknown_exception) | |
0ebc4cda | 779 | #ifdef CONFIG_ALTIVEC |
35425501 | 780 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, altivec_assist_exception) |
0ebc4cda | 781 | #else |
35425501 | 782 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, unknown_exception) |
0ebc4cda BH |
783 | #endif |
784 | #ifdef CONFIG_CBE_RAS | |
35425501 AB |
785 | STD_EXCEPTION_COMMON(0x1200, cbe_system_error, cbe_system_error_exception) |
786 | STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, cbe_maintenance_exception) | |
787 | STD_EXCEPTION_COMMON(0x1800, cbe_thermal, cbe_thermal_exception) | |
0ebc4cda BH |
788 | #endif /* CONFIG_CBE_RAS */ |
789 | ||
c1fb6816 MN |
790 | /* |
791 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
792 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
793 | * it. Addresses are the same as the original interrupt addresses, but | |
794 | * offset by 0xc000000000004000. | |
795 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
796 | * KVM: None of these traps are from the guest ; anything that escalated | |
797 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
798 | */ | |
799 | ||
800 | /* | |
801 | * This uses the standard macro, since the original 0x300 vector | |
802 | * only has extra guff for STAB-based processors -- which never | |
803 | * come here. | |
804 | */ | |
805 | STD_RELON_EXCEPTION_PSERIES(0x4300, 0x300, data_access) | |
806 | . = 0x4380 | |
807 | .globl data_access_slb_relon_pSeries | |
808 | data_access_slb_relon_pSeries: | |
c1fb6816 | 809 | SET_SCRATCH0(r13) |
1707dd16 | 810 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
811 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) |
812 | std r3,PACA_EXSLB+EX_R3(r13) | |
813 | mfspr r3,SPRN_DAR | |
814 | mfspr r12,SPRN_SRR1 | |
815 | #ifndef CONFIG_RELOCATABLE | |
b1576fec | 816 | b slb_miss_realmode |
c1fb6816 MN |
817 | #else |
818 | /* | |
ad0289e4 | 819 | * We can't just use a direct branch to slb_miss_realmode |
c1fb6816 MN |
820 | * because the distance from here to there depends on where |
821 | * the kernel ends up being put. | |
822 | */ | |
823 | mfctr r11 | |
824 | ld r10,PACAKBASE(r13) | |
ad0289e4 | 825 | LOAD_HANDLER(r10, slb_miss_realmode) |
c1fb6816 MN |
826 | mtctr r10 |
827 | bctr | |
828 | #endif | |
829 | ||
830 | STD_RELON_EXCEPTION_PSERIES(0x4400, 0x400, instruction_access) | |
831 | . = 0x4480 | |
832 | .globl instruction_access_slb_relon_pSeries | |
833 | instruction_access_slb_relon_pSeries: | |
c1fb6816 | 834 | SET_SCRATCH0(r13) |
1707dd16 | 835 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
836 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) |
837 | std r3,PACA_EXSLB+EX_R3(r13) | |
838 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
839 | mfspr r12,SPRN_SRR1 | |
840 | #ifndef CONFIG_RELOCATABLE | |
b1576fec | 841 | b slb_miss_realmode |
c1fb6816 MN |
842 | #else |
843 | mfctr r11 | |
844 | ld r10,PACAKBASE(r13) | |
ad0289e4 | 845 | LOAD_HANDLER(r10, slb_miss_realmode) |
c1fb6816 MN |
846 | mtctr r10 |
847 | bctr | |
848 | #endif | |
849 | ||
850 | . = 0x4500 | |
851 | .globl hardware_interrupt_relon_pSeries; | |
852 | .globl hardware_interrupt_relon_hv; | |
853 | hardware_interrupt_relon_pSeries: | |
854 | hardware_interrupt_relon_hv: | |
855 | BEGIN_FTR_SECTION | |
856 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV, SOFTEN_TEST_HV) | |
857 | FTR_SECTION_ELSE | |
858 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD, SOFTEN_TEST_PR) | |
3e96ca7f | 859 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
c1fb6816 MN |
860 | STD_RELON_EXCEPTION_PSERIES(0x4600, 0x600, alignment) |
861 | STD_RELON_EXCEPTION_PSERIES(0x4700, 0x700, program_check) | |
862 | STD_RELON_EXCEPTION_PSERIES(0x4800, 0x800, fp_unavailable) | |
863 | MASKABLE_RELON_EXCEPTION_PSERIES(0x4900, 0x900, decrementer) | |
864 | STD_RELON_EXCEPTION_HV(0x4980, 0x982, hdecrementer) | |
1dbdafec | 865 | MASKABLE_RELON_EXCEPTION_PSERIES(0x4a00, 0xa00, doorbell_super) |
c1fb6816 MN |
866 | STD_RELON_EXCEPTION_PSERIES(0x4b00, 0xb00, trap_0b) |
867 | ||
868 | . = 0x4c00 | |
869 | .globl system_call_relon_pSeries | |
870 | system_call_relon_pSeries: | |
871 | HMT_MEDIUM | |
872 | SYSCALL_PSERIES_1 | |
873 | SYSCALL_PSERIES_2_DIRECT | |
874 | SYSCALL_PSERIES_3 | |
875 | ||
876 | STD_RELON_EXCEPTION_PSERIES(0x4d00, 0xd00, single_step) | |
877 | ||
878 | . = 0x4e00 | |
1d567cb4 | 879 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ |
c1fb6816 MN |
880 | |
881 | . = 0x4e20 | |
1d567cb4 | 882 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ |
c1fb6816 MN |
883 | |
884 | . = 0x4e40 | |
d671ddd6 | 885 | emulation_assist_relon_trampoline: |
1707dd16 PM |
886 | SET_SCRATCH0(r13) |
887 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
888 | b emulation_assist_relon_hv |
889 | ||
c1fb6816 | 890 | . = 0x4e60 |
1d567cb4 | 891 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ |
c1fb6816 | 892 | |
655bb3f4 | 893 | . = 0x4e80 |
d671ddd6 | 894 | h_doorbell_relon_trampoline: |
1707dd16 PM |
895 | SET_SCRATCH0(r13) |
896 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
655bb3f4 | 897 | b h_doorbell_relon_hv |
c1fb6816 | 898 | |
c1fb6816 | 899 | . = 0x4f00 |
fa111f1f | 900 | performance_monitor_relon_pseries_trampoline: |
1707dd16 PM |
901 | SET_SCRATCH0(r13) |
902 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
903 | b performance_monitor_relon_pSeries |
904 | ||
c1fb6816 | 905 | . = 0x4f20 |
fa111f1f | 906 | altivec_unavailable_relon_pseries_trampoline: |
1707dd16 PM |
907 | SET_SCRATCH0(r13) |
908 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
909 | b altivec_unavailable_relon_pSeries |
910 | ||
c1fb6816 | 911 | . = 0x4f40 |
fa111f1f | 912 | vsx_unavailable_relon_pseries_trampoline: |
1707dd16 PM |
913 | SET_SCRATCH0(r13) |
914 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
915 | b vsx_unavailable_relon_pSeries |
916 | ||
d0c0c9a1 | 917 | . = 0x4f60 |
fa111f1f | 918 | facility_unavailable_relon_trampoline: |
d0c0c9a1 MN |
919 | SET_SCRATCH0(r13) |
920 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
021424a1 | 921 | b facility_unavailable_relon_pSeries |
d0c0c9a1 | 922 | |
b14b6260 | 923 | . = 0x4f80 |
fa111f1f | 924 | hv_facility_unavailable_relon_trampoline: |
b14b6260 ME |
925 | SET_SCRATCH0(r13) |
926 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
88f09412 | 927 | b hv_facility_unavailable_relon_hv |
b14b6260 | 928 | |
c1fb6816 MN |
929 | STD_RELON_EXCEPTION_PSERIES(0x5300, 0x1300, instruction_breakpoint) |
930 | #ifdef CONFIG_PPC_DENORMALISATION | |
931 | . = 0x5500 | |
932 | b denorm_exception_hv | |
933 | #endif | |
c1fb6816 | 934 | STD_RELON_EXCEPTION_PSERIES(0x5700, 0x1700, altivec_assist) |
c1fb6816 MN |
935 | |
936 | /* Other future vectors */ | |
937 | .align 7 | |
938 | .globl __end_interrupts | |
939 | __end_interrupts: | |
940 | ||
0ebc4cda | 941 | .align 7 |
c1fb6816 MN |
942 | system_call_entry_direct: |
943 | #if defined(CONFIG_RELOCATABLE) | |
944 | /* The first level prologue may have used LR to get here, saving | |
945 | * orig in r10. To save hacking/ifdeffing common code, restore here. | |
946 | */ | |
947 | mtlr r10 | |
948 | #endif | |
0ebc4cda BH |
949 | system_call_entry: |
950 | b system_call_common | |
951 | ||
fe1952fc | 952 | ppc64_runlatch_on_trampoline: |
b1576fec | 953 | b __ppc64_runlatch_on |
fe1952fc | 954 | |
0ebc4cda BH |
955 | /* |
956 | * Here r13 points to the paca, r9 contains the saved CR, | |
957 | * SRR0 and SRR1 are saved in r11 and r12, | |
958 | * r9 - r13 are saved in paca->exgen. | |
959 | */ | |
960 | .align 7 | |
961 | .globl data_access_common | |
962 | data_access_common: | |
963 | mfspr r10,SPRN_DAR | |
964 | std r10,PACA_EXGEN+EX_DAR(r13) | |
965 | mfspr r10,SPRN_DSISR | |
966 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
967 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
a546498f BH |
968 | DISABLE_INTS |
969 | ld r12,_MSR(r1) | |
0ebc4cda BH |
970 | ld r3,PACA_EXGEN+EX_DAR(r13) |
971 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
972 | li r5,0x300 | |
b1576fec | 973 | b do_hash_page /* Try to handle as hpte fault */ |
0ebc4cda | 974 | |
b3e6b5df | 975 | .align 7 |
278a6cdc | 976 | .globl h_data_storage_common |
b3e6b5df | 977 | h_data_storage_common: |
278a6cdc MN |
978 | mfspr r10,SPRN_HDAR |
979 | std r10,PACA_EXGEN+EX_DAR(r13) | |
980 | mfspr r10,SPRN_HDSISR | |
981 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
982 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
b1576fec | 983 | bl save_nvgprs |
a546498f | 984 | DISABLE_INTS |
278a6cdc | 985 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
986 | bl unknown_exception |
987 | b ret_from_except | |
b3e6b5df | 988 | |
0ebc4cda BH |
989 | .align 7 |
990 | .globl instruction_access_common | |
991 | instruction_access_common: | |
992 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
a546498f BH |
993 | DISABLE_INTS |
994 | ld r12,_MSR(r1) | |
0ebc4cda BH |
995 | ld r3,_NIP(r1) |
996 | andis. r4,r12,0x5820 | |
997 | li r5,0x400 | |
b1576fec | 998 | b do_hash_page /* Try to handle as hpte fault */ |
0ebc4cda | 999 | |
35425501 | 1000 | STD_EXCEPTION_COMMON(0xe20, h_instr_storage, unknown_exception) |
b3e6b5df | 1001 | |
0ebc4cda BH |
1002 | /* |
1003 | * Here is the common SLB miss user that is used when going to virtual | |
1004 | * mode for SLB misses, that is currently not used | |
1005 | */ | |
1006 | #ifdef __DISABLED__ | |
1007 | .align 7 | |
1008 | .globl slb_miss_user_common | |
1009 | slb_miss_user_common: | |
1010 | mflr r10 | |
1011 | std r3,PACA_EXGEN+EX_DAR(r13) | |
1012 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
1013 | std r10,PACA_EXGEN+EX_LR(r13) | |
1014 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
b1576fec | 1015 | bl slb_allocate_user |
0ebc4cda BH |
1016 | |
1017 | ld r10,PACA_EXGEN+EX_LR(r13) | |
1018 | ld r3,PACA_EXGEN+EX_R3(r13) | |
1019 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
1020 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
1021 | mtlr r10 | |
1022 | beq- slb_miss_fault | |
1023 | ||
1024 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
1025 | beq- unrecov_user_slb | |
1026 | mfmsr r10 | |
1027 | ||
1028 | .machine push | |
1029 | .machine "power4" | |
1030 | mtcrf 0x80,r9 | |
1031 | .machine pop | |
1032 | ||
1033 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
1034 | mtmsrd r10,1 | |
1035 | ||
1036 | mtspr SRR0,r11 | |
1037 | mtspr SRR1,r12 | |
1038 | ||
1039 | ld r9,PACA_EXGEN+EX_R9(r13) | |
1040 | ld r10,PACA_EXGEN+EX_R10(r13) | |
1041 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1042 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1043 | ld r13,PACA_EXGEN+EX_R13(r13) | |
1044 | rfid | |
1045 | b . | |
1046 | ||
1047 | slb_miss_fault: | |
1048 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
1049 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
1050 | li r5,0 | |
1051 | std r4,_DAR(r1) | |
1052 | std r5,_DSISR(r1) | |
1053 | b handle_page_fault | |
1054 | ||
1055 | unrecov_user_slb: | |
1056 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
1057 | DISABLE_INTS | |
b1576fec | 1058 | bl save_nvgprs |
0ebc4cda | 1059 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 1060 | bl unrecoverable_exception |
0ebc4cda BH |
1061 | b 1b |
1062 | ||
1063 | #endif /* __DISABLED__ */ | |
1064 | ||
1065 | ||
4e243b79 MS |
1066 | /* |
1067 | * Machine check is different because we use a different | |
1068 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
1069 | */ | |
1070 | .align 7 | |
1071 | .globl machine_check_common | |
1072 | machine_check_common: | |
1073 | ||
1074 | mfspr r10,SPRN_DAR | |
1075 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1076 | mfspr r10,SPRN_DSISR | |
1077 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
1078 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
1079 | FINISH_NAP | |
1080 | DISABLE_INTS | |
1081 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1082 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1083 | std r3,_DAR(r1) | |
1084 | std r4,_DSISR(r1) | |
b1576fec | 1085 | bl save_nvgprs |
4e243b79 | 1086 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1087 | bl machine_check_exception |
1088 | b ret_from_except | |
4e243b79 | 1089 | |
0ebc4cda BH |
1090 | .align 7 |
1091 | .globl alignment_common | |
1092 | alignment_common: | |
1093 | mfspr r10,SPRN_DAR | |
1094 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1095 | mfspr r10,SPRN_DSISR | |
1096 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
1097 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
1098 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1099 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1100 | std r3,_DAR(r1) | |
1101 | std r4,_DSISR(r1) | |
b1576fec | 1102 | bl save_nvgprs |
a3512b2d | 1103 | DISABLE_INTS |
0ebc4cda | 1104 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1105 | bl alignment_exception |
1106 | b ret_from_except | |
0ebc4cda BH |
1107 | |
1108 | .align 7 | |
1109 | .globl program_check_common | |
1110 | program_check_common: | |
1111 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
b1576fec | 1112 | bl save_nvgprs |
54321242 | 1113 | DISABLE_INTS |
922b9f86 | 1114 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1115 | bl program_check_exception |
1116 | b ret_from_except | |
0ebc4cda BH |
1117 | |
1118 | .align 7 | |
1119 | .globl fp_unavailable_common | |
1120 | fp_unavailable_common: | |
1121 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
1122 | bne 1f /* if from user, just load it up */ | |
b1576fec | 1123 | bl save_nvgprs |
9f2f79e3 | 1124 | DISABLE_INTS |
0ebc4cda | 1125 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 1126 | bl kernel_fp_unavailable_exception |
0ebc4cda | 1127 | BUG_OPCODE |
bc2a9408 MN |
1128 | 1: |
1129 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1130 | BEGIN_FTR_SECTION | |
1131 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1132 | * transaction), go do TM stuff | |
1133 | */ | |
1134 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1135 | bne- 2f | |
1136 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
1137 | #endif | |
b1576fec | 1138 | bl load_up_fpu |
0ebc4cda | 1139 | b fast_exception_return |
bc2a9408 MN |
1140 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1141 | 2: /* User process was in a transaction */ | |
b1576fec | 1142 | bl save_nvgprs |
bc2a9408 MN |
1143 | DISABLE_INTS |
1144 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1145 | bl fp_unavailable_tm |
1146 | b ret_from_except | |
bc2a9408 | 1147 | #endif |
0ebc4cda BH |
1148 | .align 7 |
1149 | .globl altivec_unavailable_common | |
1150 | altivec_unavailable_common: | |
1151 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1152 | #ifdef CONFIG_ALTIVEC | |
1153 | BEGIN_FTR_SECTION | |
1154 | beq 1f | |
bc2a9408 MN |
1155 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1156 | BEGIN_FTR_SECTION_NESTED(69) | |
1157 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1158 | * transaction), go do TM stuff | |
1159 | */ | |
1160 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1161 | bne- 2f | |
1162 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1163 | #endif | |
b1576fec | 1164 | bl load_up_altivec |
0ebc4cda | 1165 | b fast_exception_return |
bc2a9408 MN |
1166 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1167 | 2: /* User process was in a transaction */ | |
b1576fec | 1168 | bl save_nvgprs |
bc2a9408 MN |
1169 | DISABLE_INTS |
1170 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1171 | bl altivec_unavailable_tm |
1172 | b ret_from_except | |
bc2a9408 | 1173 | #endif |
0ebc4cda BH |
1174 | 1: |
1175 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1176 | #endif | |
b1576fec | 1177 | bl save_nvgprs |
9f2f79e3 | 1178 | DISABLE_INTS |
0ebc4cda | 1179 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1180 | bl altivec_unavailable_exception |
1181 | b ret_from_except | |
0ebc4cda BH |
1182 | |
1183 | .align 7 | |
1184 | .globl vsx_unavailable_common | |
1185 | vsx_unavailable_common: | |
1186 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1187 | #ifdef CONFIG_VSX | |
1188 | BEGIN_FTR_SECTION | |
7230c564 | 1189 | beq 1f |
bc2a9408 MN |
1190 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1191 | BEGIN_FTR_SECTION_NESTED(69) | |
1192 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1193 | * transaction), go do TM stuff | |
1194 | */ | |
1195 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1196 | bne- 2f | |
1197 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1198 | #endif | |
b1576fec | 1199 | b load_up_vsx |
bc2a9408 MN |
1200 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1201 | 2: /* User process was in a transaction */ | |
b1576fec | 1202 | bl save_nvgprs |
bc2a9408 MN |
1203 | DISABLE_INTS |
1204 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1205 | bl vsx_unavailable_tm |
1206 | b ret_from_except | |
bc2a9408 | 1207 | #endif |
0ebc4cda BH |
1208 | 1: |
1209 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1210 | #endif | |
b1576fec | 1211 | bl save_nvgprs |
9f2f79e3 | 1212 | DISABLE_INTS |
0ebc4cda | 1213 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1214 | bl vsx_unavailable_exception |
1215 | b ret_from_except | |
0ebc4cda | 1216 | |
35425501 AB |
1217 | STD_EXCEPTION_COMMON(0xf60, facility_unavailable, facility_unavailable_exception) |
1218 | STD_EXCEPTION_COMMON(0xf80, hv_facility_unavailable, facility_unavailable_exception) | |
d0c0c9a1 | 1219 | |
0ebc4cda BH |
1220 | .align 7 |
1221 | .globl __end_handlers | |
1222 | __end_handlers: | |
1223 | ||
61383407 | 1224 | /* Equivalents to the above handlers for relocation-on interrupt vectors */ |
1707dd16 | 1225 | STD_RELON_EXCEPTION_HV_OOL(0xe40, emulation_assist) |
1707dd16 | 1226 | MASKABLE_RELON_EXCEPTION_HV_OOL(0xe80, h_doorbell) |
61383407 | 1227 | |
1707dd16 PM |
1228 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf00, performance_monitor) |
1229 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf20, altivec_unavailable) | |
1230 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable) | |
021424a1 | 1231 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf60, facility_unavailable) |
88f09412 | 1232 | STD_RELON_EXCEPTION_HV_OOL(0xf80, hv_facility_unavailable) |
61383407 BH |
1233 | |
1234 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
1235 | /* | |
1236 | * Data area reserved for FWNMI option. | |
1237 | * This address (0x7000) is fixed by the RPA. | |
1238 | */ | |
1239 | .= 0x7000 | |
1240 | .globl fwnmi_data_area | |
1241 | fwnmi_data_area: | |
1242 | ||
1243 | /* pseries and powernv need to keep the whole page from | |
1244 | * 0x7000 to 0x8000 free for use by the firmware | |
1245 | */ | |
1246 | . = 0x8000 | |
1247 | #endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */ | |
1248 | ||
61383407 BH |
1249 | #ifdef CONFIG_PPC_POWERNV |
1250 | _GLOBAL(opal_mc_secondary_handler) | |
1251 | HMT_MEDIUM_PPR_DISCARD | |
1252 | SET_SCRATCH0(r13) | |
1253 | GET_PACA(r13) | |
1254 | clrldi r3,r3,2 | |
1255 | tovirt(r3,r3) | |
1256 | std r3,PACA_OPAL_MC_EVT(r13) | |
1257 | ld r13,OPAL_MC_SRR0(r3) | |
1258 | mtspr SPRN_SRR0,r13 | |
1259 | ld r13,OPAL_MC_SRR1(r3) | |
1260 | mtspr SPRN_SRR1,r13 | |
1261 | ld r3,OPAL_MC_GPR3(r3) | |
1262 | GET_SCRATCH0(r13) | |
1263 | b machine_check_pSeries | |
1264 | #endif /* CONFIG_PPC_POWERNV */ | |
1265 | ||
1266 | ||
4e243b79 MS |
1267 | #define MACHINE_CHECK_HANDLER_WINDUP \ |
1268 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
1269 | li r0,MSR_RI; \ | |
1270 | mfmsr r9; /* get MSR value */ \ | |
1271 | andc r9,r9,r0; \ | |
1272 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
1273 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
1274 | ld r9,_MSR(r1); \ | |
1275 | mtspr SPRN_SRR1,r9; \ | |
1276 | ld r3,_NIP(r1); \ | |
1277 | mtspr SPRN_SRR0,r3; \ | |
1278 | ld r9,_CTR(r1); \ | |
1279 | mtctr r9; \ | |
1280 | ld r9,_XER(r1); \ | |
1281 | mtxer r9; \ | |
1282 | ld r9,_LINK(r1); \ | |
1283 | mtlr r9; \ | |
1284 | REST_GPR(0, r1); \ | |
1285 | REST_8GPRS(2, r1); \ | |
1286 | REST_GPR(10, r1); \ | |
1287 | ld r11,_CCR(r1); \ | |
1288 | mtcr r11; \ | |
1289 | /* Decrement paca->in_mce. */ \ | |
1290 | lhz r12,PACA_IN_MCE(r13); \ | |
1291 | subi r12,r12,1; \ | |
1292 | sth r12,PACA_IN_MCE(r13); \ | |
1293 | REST_GPR(11, r1); \ | |
1294 | REST_2GPRS(12, r1); \ | |
1295 | /* restore original r1. */ \ | |
1296 | ld r1,GPR1(r1) | |
1297 | ||
1298 | /* | |
1299 | * Handle machine check early in real mode. We come here with | |
1300 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
1301 | */ | |
1302 | .align 7 | |
1303 | .globl machine_check_handle_early | |
1304 | machine_check_handle_early: | |
1305 | std r0,GPR0(r1) /* Save r0 */ | |
1306 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
b1576fec | 1307 | bl save_nvgprs |
4e243b79 | 1308 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 1309 | bl machine_check_early |
2749a2f2 | 1310 | std r3,RESULT(r1) /* Save result */ |
4e243b79 MS |
1311 | ld r12,_MSR(r1) |
1312 | #ifdef CONFIG_PPC_P7_NAP | |
1313 | /* | |
1314 | * Check if thread was in power saving mode. We come here when any | |
1315 | * of the following is true: | |
1316 | * a. thread wasn't in power saving mode | |
1317 | * b. thread was in power saving mode with no state loss or | |
1318 | * supervisor state loss | |
1319 | * | |
1320 | * Go back to nap again if (b) is true. | |
1321 | */ | |
1322 | rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ | |
1323 | beq 4f /* No, it wasn;t */ | |
1324 | /* Thread was in power saving mode. Go back to nap again. */ | |
1325 | cmpwi r11,2 | |
1326 | bne 3f | |
1327 | /* Supervisor state loss */ | |
1328 | li r0,1 | |
1329 | stb r0,PACA_NAPSTATELOST(r13) | |
b1576fec | 1330 | 3: bl machine_check_queue_event |
4e243b79 MS |
1331 | MACHINE_CHECK_HANDLER_WINDUP |
1332 | GET_PACA(r13) | |
1333 | ld r1,PACAR1(r13) | |
b1576fec | 1334 | b power7_enter_nap_mode |
4e243b79 MS |
1335 | 4: |
1336 | #endif | |
1337 | /* | |
1338 | * Check if we are coming from hypervisor userspace. If yes then we | |
1339 | * continue in host kernel in V mode to deliver the MC event. | |
1340 | */ | |
1341 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
1342 | beq 5f | |
1343 | andi. r11,r12,MSR_PR /* See if coming from user. */ | |
1344 | bne 9f /* continue in V mode if we are. */ | |
1345 | ||
1346 | 5: | |
1347 | #ifdef CONFIG_KVM_BOOK3S_64_HV | |
1348 | /* | |
1349 | * We are coming from kernel context. Check if we are coming from | |
1350 | * guest. if yes, then we can continue. We will fall through | |
1351 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
1352 | */ | |
1353 | lbz r11,HSTATE_IN_GUEST(r13) | |
1354 | cmpwi r11,0 /* Check if coming from guest */ | |
1355 | bne 9f /* continue if we are. */ | |
1356 | #endif | |
1357 | /* | |
1358 | * At this point we are not sure about what context we come from. | |
1359 | * Queue up the MCE event and return from the interrupt. | |
1360 | * But before that, check if this is an un-recoverable exception. | |
1361 | * If yes, then stay on emergency stack and panic. | |
1362 | */ | |
1363 | andi. r11,r12,MSR_RI | |
1364 | bne 2f | |
2749a2f2 MS |
1365 | 1: mfspr r11,SPRN_SRR0 |
1366 | ld r10,PACAKBASE(r13) | |
1367 | LOAD_HANDLER(r10,unrecover_mce) | |
1368 | mtspr SPRN_SRR0,r10 | |
1369 | ld r10,PACAKMSR(r13) | |
1370 | /* | |
1371 | * We are going down. But there are chances that we might get hit by | |
1372 | * another MCE during panic path and we may run into unstable state | |
1373 | * with no way out. Hence, turn ME bit off while going down, so that | |
1374 | * when another MCE is hit during panic path, system will checkstop | |
1375 | * and hypervisor will get restarted cleanly by SP. | |
1376 | */ | |
1377 | li r3,MSR_ME | |
1378 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
1379 | mtspr SPRN_SRR1,r10 | |
1380 | rfid | |
1381 | b . | |
4e243b79 | 1382 | 2: |
2749a2f2 MS |
1383 | /* |
1384 | * Check if we have successfully handled/recovered from error, if not | |
1385 | * then stay on emergency stack and panic. | |
1386 | */ | |
1387 | ld r3,RESULT(r1) /* Load result */ | |
1388 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
1389 | ||
1390 | beq 1b /* if !handled then panic */ | |
4e243b79 MS |
1391 | /* |
1392 | * Return from MC interrupt. | |
1393 | * Queue up the MCE event so that we can log it later, while | |
1394 | * returning from kernel or opal call. | |
1395 | */ | |
b1576fec | 1396 | bl machine_check_queue_event |
4e243b79 MS |
1397 | MACHINE_CHECK_HANDLER_WINDUP |
1398 | rfid | |
1399 | 9: | |
1400 | /* Deliver the machine check to host kernel in V mode. */ | |
1401 | MACHINE_CHECK_HANDLER_WINDUP | |
1402 | b machine_check_pSeries | |
1403 | ||
2749a2f2 MS |
1404 | unrecover_mce: |
1405 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
1406 | addi r3,r1,STACK_FRAME_OVERHEAD | |
ad718622 | 1407 | bl machine_check_exception |
2749a2f2 MS |
1408 | /* |
1409 | * We will not reach here. Even if we did, there is no way out. Call | |
1410 | * unrecoverable_exception and die. | |
1411 | */ | |
1412 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
ad718622 | 1413 | bl unrecoverable_exception |
2749a2f2 | 1414 | b 1b |
087aa036 CG |
1415 | /* |
1416 | * r13 points to the PACA, r9 contains the saved CR, | |
1417 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
1418 | * r3 has the faulting address | |
1419 | * r9 - r13 are saved in paca->exslb. | |
1420 | * r3 is saved in paca->slb_r3 | |
1421 | * We assume we aren't going to take any exceptions during this procedure. | |
1422 | */ | |
ad0289e4 | 1423 | slb_miss_realmode: |
087aa036 CG |
1424 | mflr r10 |
1425 | #ifdef CONFIG_RELOCATABLE | |
1426 | mtctr r11 | |
1427 | #endif | |
1428 | ||
1429 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1430 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
1431 | ||
b1576fec | 1432 | bl slb_allocate_realmode |
087aa036 CG |
1433 | |
1434 | /* All done -- return from exception. */ | |
1435 | ||
1436 | ld r10,PACA_EXSLB+EX_LR(r13) | |
1437 | ld r3,PACA_EXSLB+EX_R3(r13) | |
1438 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1439 | ||
1440 | mtlr r10 | |
1441 | ||
1442 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
1443 | beq- 2f | |
1444 | ||
1445 | .machine push | |
1446 | .machine "power4" | |
1447 | mtcrf 0x80,r9 | |
1448 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
1449 | .machine pop | |
1450 | ||
1451 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
1452 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1453 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1454 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1455 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1456 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1457 | rfid | |
1458 | b . /* prevent speculative execution */ | |
1459 | ||
1460 | 2: mfspr r11,SPRN_SRR0 | |
1461 | ld r10,PACAKBASE(r13) | |
1462 | LOAD_HANDLER(r10,unrecov_slb) | |
1463 | mtspr SPRN_SRR0,r10 | |
1464 | ld r10,PACAKMSR(r13) | |
1465 | mtspr SPRN_SRR1,r10 | |
1466 | rfid | |
1467 | b . | |
1468 | ||
1469 | unrecov_slb: | |
1470 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
1471 | DISABLE_INTS | |
b1576fec | 1472 | bl save_nvgprs |
087aa036 | 1473 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 1474 | bl unrecoverable_exception |
087aa036 CG |
1475 | b 1b |
1476 | ||
1477 | ||
1478 | #ifdef CONFIG_PPC_970_NAP | |
1479 | power4_fixup_nap: | |
1480 | andc r9,r9,r10 | |
1481 | std r9,TI_LOCAL_FLAGS(r11) | |
1482 | ld r10,_LINK(r1) /* make idle task do the */ | |
1483 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1484 | blr | |
1485 | #endif | |
1486 | ||
0ebc4cda BH |
1487 | /* |
1488 | * Hash table stuff | |
1489 | */ | |
1490 | .align 7 | |
6a3bab90 | 1491 | do_hash_page: |
0ebc4cda BH |
1492 | std r3,_DAR(r1) |
1493 | std r4,_DSISR(r1) | |
1494 | ||
9c7cc234 | 1495 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1496 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1497 | andis. r0,r4,DSISR_DABRMATCH@h |
1498 | bne- handle_dabr_fault | |
9778b696 | 1499 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1500 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1501 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1502 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1503 | /* |
1504 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
1505 | * accessing a userspace segment (even from the kernel). We assume | |
1506 | * kernel addresses always have the high bit set. | |
1507 | */ | |
1508 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
1509 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
1510 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
1511 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
1512 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
1513 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
1514 | ||
1515 | /* | |
1516 | * r3 contains the faulting address | |
1517 | * r4 contains the required access permissions | |
1518 | * r5 contains the trap number | |
1519 | * | |
7230c564 | 1520 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1521 | */ |
b1576fec | 1522 | bl hash_page /* build HPTE if possible */ |
0ebc4cda BH |
1523 | cmpdi r3,0 /* see if hash_page succeeded */ |
1524 | ||
7230c564 | 1525 | /* Success */ |
0ebc4cda | 1526 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1527 | |
7230c564 BH |
1528 | /* Error */ |
1529 | blt- 13f | |
9c7cc234 | 1530 | |
0ebc4cda BH |
1531 | /* Here we have a page fault that hash_page can't handle. */ |
1532 | handle_page_fault: | |
0ebc4cda BH |
1533 | 11: ld r4,_DAR(r1) |
1534 | ld r5,_DSISR(r1) | |
1535 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1536 | bl do_page_fault |
0ebc4cda | 1537 | cmpdi r3,0 |
a546498f | 1538 | beq+ 12f |
b1576fec | 1539 | bl save_nvgprs |
0ebc4cda BH |
1540 | mr r5,r3 |
1541 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1542 | lwz r4,_DAR(r1) | |
b1576fec AB |
1543 | bl bad_page_fault |
1544 | b ret_from_except | |
0ebc4cda | 1545 | |
a546498f BH |
1546 | /* We have a data breakpoint exception - handle it */ |
1547 | handle_dabr_fault: | |
b1576fec | 1548 | bl save_nvgprs |
a546498f BH |
1549 | ld r4,_DAR(r1) |
1550 | ld r5,_DSISR(r1) | |
1551 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1552 | bl do_break |
1553 | 12: b ret_from_except_lite | |
a546498f | 1554 | |
0ebc4cda BH |
1555 | |
1556 | /* We have a page fault that hash_page could handle but HV refused | |
1557 | * the PTE insertion | |
1558 | */ | |
b1576fec | 1559 | 13: bl save_nvgprs |
0ebc4cda BH |
1560 | mr r5,r3 |
1561 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1562 | ld r4,_DAR(r1) | |
b1576fec AB |
1563 | bl low_hash_fault |
1564 | b ret_from_except | |
0ebc4cda | 1565 | |
9c1e1052 PM |
1566 | /* |
1567 | * We come here as a result of a DSI at a point where we don't want | |
1568 | * to call hash_page, such as when we are accessing memory (possibly | |
1569 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1570 | * were soft-disabled. We want to invoke the exception handler for | |
1571 | * the access, or panic if there isn't a handler. | |
1572 | */ | |
b1576fec | 1573 | 77: bl save_nvgprs |
9c1e1052 PM |
1574 | mr r4,r3 |
1575 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1576 | li r5,SIGSEGV | |
b1576fec AB |
1577 | bl bad_page_fault |
1578 | b ret_from_except | |
4e2bf01b ME |
1579 | |
1580 | /* | |
1581 | * Here we have detected that the kernel stack pointer is bad. | |
1582 | * R9 contains the saved CR, r13 points to the paca, | |
1583 | * r10 contains the (bad) kernel stack pointer, | |
1584 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1585 | * We switch to using an emergency stack, save the registers there, | |
1586 | * and call kernel_bad_stack(), which panics. | |
1587 | */ | |
1588 | bad_stack: | |
1589 | ld r1,PACAEMERGSP(r13) | |
1590 | subi r1,r1,64+INT_FRAME_SIZE | |
1591 | std r9,_CCR(r1) | |
1592 | std r10,GPR1(r1) | |
1593 | std r11,_NIP(r1) | |
1594 | std r12,_MSR(r1) | |
1595 | mfspr r11,SPRN_DAR | |
1596 | mfspr r12,SPRN_DSISR | |
1597 | std r11,_DAR(r1) | |
1598 | std r12,_DSISR(r1) | |
1599 | mflr r10 | |
1600 | mfctr r11 | |
1601 | mfxer r12 | |
1602 | std r10,_LINK(r1) | |
1603 | std r11,_CTR(r1) | |
1604 | std r12,_XER(r1) | |
1605 | SAVE_GPR(0,r1) | |
1606 | SAVE_GPR(2,r1) | |
1607 | ld r10,EX_R3(r3) | |
1608 | std r10,GPR3(r1) | |
1609 | SAVE_GPR(4,r1) | |
1610 | SAVE_4GPRS(5,r1) | |
1611 | ld r9,EX_R9(r3) | |
1612 | ld r10,EX_R10(r3) | |
1613 | SAVE_2GPRS(9,r1) | |
1614 | ld r9,EX_R11(r3) | |
1615 | ld r10,EX_R12(r3) | |
1616 | ld r11,EX_R13(r3) | |
1617 | std r9,GPR11(r1) | |
1618 | std r10,GPR12(r1) | |
1619 | std r11,GPR13(r1) | |
1620 | BEGIN_FTR_SECTION | |
1621 | ld r10,EX_CFAR(r3) | |
1622 | std r10,ORIG_GPR3(r1) | |
1623 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1624 | SAVE_8GPRS(14,r1) | |
1625 | SAVE_10GPRS(22,r1) | |
1626 | lhz r12,PACA_TRAP_SAVE(r13) | |
1627 | std r12,_TRAP(r1) | |
1628 | addi r11,r1,INT_FRAME_SIZE | |
1629 | std r11,0(r1) | |
1630 | li r12,0 | |
1631 | std r12,0(r11) | |
1632 | ld r2,PACATOC(r13) | |
1633 | ld r11,exception_marker@toc(r2) | |
1634 | std r12,RESULT(r1) | |
1635 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1636 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1637 | bl kernel_bad_stack | |
1638 | b 1b |