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14cf11af 1/*
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2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
4 *
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
7 *
8 * PowerPC version
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
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17#include <linux/errno.h>
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/mm.h>
21#include <linux/smp.h>
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22#include <linux/stddef.h>
23#include <linux/unistd.h>
24#include <linux/ptrace.h>
25#include <linux/slab.h>
26#include <linux/user.h>
27#include <linux/elf.h>
28#include <linux/init.h>
29#include <linux/prctl.h>
30#include <linux/init_task.h>
31#include <linux/module.h>
32#include <linux/kallsyms.h>
33#include <linux/mqueue.h>
34#include <linux/hardirq.h>
06d67d54 35#include <linux/utsname.h>
6794c782 36#include <linux/ftrace.h>
79741dd3 37#include <linux/kernel_stat.h>
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38#include <linux/personality.h>
39#include <linux/random.h>
5aae8a53 40#include <linux/hw_breakpoint.h>
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41
42#include <asm/pgtable.h>
43#include <asm/uaccess.h>
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/processor.h>
47#include <asm/mmu.h>
48#include <asm/prom.h>
76032de8 49#include <asm/machdep.h>
c6622f63 50#include <asm/time.h>
a7f31841 51#include <asm/syscalls.h>
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52#ifdef CONFIG_PPC64
53#include <asm/firmware.h>
06d67d54 54#endif
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55#include <linux/kprobes.h>
56#include <linux/kdebug.h>
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57
58extern unsigned long _get_SP(void);
59
60#ifndef CONFIG_SMP
61struct task_struct *last_task_used_math = NULL;
62struct task_struct *last_task_used_altivec = NULL;
ce48b210 63struct task_struct *last_task_used_vsx = NULL;
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64struct task_struct *last_task_used_spe = NULL;
65#endif
66
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67/*
68 * Make sure the floating-point register state in the
69 * the thread_struct is up to date for task tsk.
70 */
71void flush_fp_to_thread(struct task_struct *tsk)
72{
73 if (tsk->thread.regs) {
74 /*
75 * We need to disable preemption here because if we didn't,
76 * another process could get scheduled after the regs->msr
77 * test but before we have finished saving the FP registers
78 * to the thread_struct. That process could take over the
79 * FPU, and then when we get scheduled again we would store
80 * bogus values for the remaining FP registers.
81 */
82 preempt_disable();
83 if (tsk->thread.regs->msr & MSR_FP) {
84#ifdef CONFIG_SMP
85 /*
86 * This should only ever be called for current or
87 * for a stopped child process. Since we save away
88 * the FP register state on context switch on SMP,
89 * there is something wrong if a stopped child appears
90 * to still have its FP state in the CPU registers.
91 */
92 BUG_ON(tsk != current);
93#endif
0ee6c15e 94 giveup_fpu(tsk);
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95 }
96 preempt_enable();
97 }
98}
99
100void enable_kernel_fp(void)
101{
102 WARN_ON(preemptible());
103
104#ifdef CONFIG_SMP
105 if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
106 giveup_fpu(current);
107 else
108 giveup_fpu(NULL); /* just enables FP for kernel */
109#else
110 giveup_fpu(last_task_used_math);
111#endif /* CONFIG_SMP */
112}
113EXPORT_SYMBOL(enable_kernel_fp);
114
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115#ifdef CONFIG_ALTIVEC
116void enable_kernel_altivec(void)
117{
118 WARN_ON(preemptible());
119
120#ifdef CONFIG_SMP
121 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
122 giveup_altivec(current);
123 else
124 giveup_altivec(NULL); /* just enable AltiVec for kernel - force */
125#else
126 giveup_altivec(last_task_used_altivec);
127#endif /* CONFIG_SMP */
128}
129EXPORT_SYMBOL(enable_kernel_altivec);
130
131/*
132 * Make sure the VMX/Altivec register state in the
133 * the thread_struct is up to date for task tsk.
134 */
135void flush_altivec_to_thread(struct task_struct *tsk)
136{
137 if (tsk->thread.regs) {
138 preempt_disable();
139 if (tsk->thread.regs->msr & MSR_VEC) {
140#ifdef CONFIG_SMP
141 BUG_ON(tsk != current);
142#endif
0ee6c15e 143 giveup_altivec(tsk);
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144 }
145 preempt_enable();
146 }
147}
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148#endif /* CONFIG_ALTIVEC */
149
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150#ifdef CONFIG_VSX
151#if 0
152/* not currently used, but some crazy RAID module might want to later */
153void enable_kernel_vsx(void)
154{
155 WARN_ON(preemptible());
156
157#ifdef CONFIG_SMP
158 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
159 giveup_vsx(current);
160 else
161 giveup_vsx(NULL); /* just enable vsx for kernel - force */
162#else
163 giveup_vsx(last_task_used_vsx);
164#endif /* CONFIG_SMP */
165}
166EXPORT_SYMBOL(enable_kernel_vsx);
167#endif
168
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169void giveup_vsx(struct task_struct *tsk)
170{
171 giveup_fpu(tsk);
172 giveup_altivec(tsk);
173 __giveup_vsx(tsk);
174}
175
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176void flush_vsx_to_thread(struct task_struct *tsk)
177{
178 if (tsk->thread.regs) {
179 preempt_disable();
180 if (tsk->thread.regs->msr & MSR_VSX) {
181#ifdef CONFIG_SMP
182 BUG_ON(tsk != current);
183#endif
184 giveup_vsx(tsk);
185 }
186 preempt_enable();
187 }
188}
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189#endif /* CONFIG_VSX */
190
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191#ifdef CONFIG_SPE
192
193void enable_kernel_spe(void)
194{
195 WARN_ON(preemptible());
196
197#ifdef CONFIG_SMP
198 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
199 giveup_spe(current);
200 else
201 giveup_spe(NULL); /* just enable SPE for kernel - force */
202#else
203 giveup_spe(last_task_used_spe);
204#endif /* __SMP __ */
205}
206EXPORT_SYMBOL(enable_kernel_spe);
207
208void flush_spe_to_thread(struct task_struct *tsk)
209{
210 if (tsk->thread.regs) {
211 preempt_disable();
212 if (tsk->thread.regs->msr & MSR_SPE) {
213#ifdef CONFIG_SMP
214 BUG_ON(tsk != current);
215#endif
0ee6c15e 216 giveup_spe(tsk);
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217 }
218 preempt_enable();
219 }
220}
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221#endif /* CONFIG_SPE */
222
5388fb10 223#ifndef CONFIG_SMP
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224/*
225 * If we are doing lazy switching of CPU state (FP, altivec or SPE),
226 * and the current task has some state, discard it.
227 */
5388fb10 228void discard_lazy_cpu_state(void)
48abec07 229{
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230 preempt_disable();
231 if (last_task_used_math == current)
232 last_task_used_math = NULL;
233#ifdef CONFIG_ALTIVEC
234 if (last_task_used_altivec == current)
235 last_task_used_altivec = NULL;
236#endif /* CONFIG_ALTIVEC */
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237#ifdef CONFIG_VSX
238 if (last_task_used_vsx == current)
239 last_task_used_vsx = NULL;
240#endif /* CONFIG_VSX */
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241#ifdef CONFIG_SPE
242 if (last_task_used_spe == current)
243 last_task_used_spe = NULL;
244#endif
245 preempt_enable();
48abec07 246}
5388fb10 247#endif /* CONFIG_SMP */
48abec07 248
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249#ifdef CONFIG_PPC_ADV_DEBUG_REGS
250void do_send_trap(struct pt_regs *regs, unsigned long address,
251 unsigned long error_code, int signal_code, int breakpt)
252{
253 siginfo_t info;
254
255 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
256 11, SIGSEGV) == NOTIFY_STOP)
257 return;
258
259 /* Deliver the signal to userspace */
260 info.si_signo = SIGTRAP;
261 info.si_errno = breakpt; /* breakpoint or watchpoint id */
262 info.si_code = signal_code;
263 info.si_addr = (void __user *)address;
264 force_sig_info(SIGTRAP, &info, current);
265}
266#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
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267void do_dabr(struct pt_regs *regs, unsigned long address,
268 unsigned long error_code)
269{
270 siginfo_t info;
271
272 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
273 11, SIGSEGV) == NOTIFY_STOP)
274 return;
275
276 if (debugger_dabr_match(regs))
277 return;
278
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279 /* Clear the DABR */
280 set_dabr(0);
281
282 /* Deliver the signal to userspace */
283 info.si_signo = SIGTRAP;
284 info.si_errno = 0;
285 info.si_code = TRAP_HWBKPT;
286 info.si_addr = (void __user *)address;
287 force_sig_info(SIGTRAP, &info, current);
288}
3bffb652 289#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
d6a61bfc 290
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291static DEFINE_PER_CPU(unsigned long, current_dabr);
292
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293#ifdef CONFIG_PPC_ADV_DEBUG_REGS
294/*
295 * Set the debug registers back to their default "safe" values.
296 */
297static void set_debug_reg_defaults(struct thread_struct *thread)
298{
299 thread->iac1 = thread->iac2 = 0;
300#if CONFIG_PPC_ADV_DEBUG_IACS > 2
301 thread->iac3 = thread->iac4 = 0;
302#endif
303 thread->dac1 = thread->dac2 = 0;
304#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
305 thread->dvc1 = thread->dvc2 = 0;
306#endif
307 thread->dbcr0 = 0;
308#ifdef CONFIG_BOOKE
309 /*
310 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
311 */
312 thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
313 DBCR1_IAC3US | DBCR1_IAC4US;
314 /*
315 * Force Data Address Compare User/Supervisor bits to be User-only
316 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
317 */
318 thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
319#else
320 thread->dbcr1 = 0;
321#endif
322}
323
324static void prime_debug_regs(struct thread_struct *thread)
325{
326 mtspr(SPRN_IAC1, thread->iac1);
327 mtspr(SPRN_IAC2, thread->iac2);
328#if CONFIG_PPC_ADV_DEBUG_IACS > 2
329 mtspr(SPRN_IAC3, thread->iac3);
330 mtspr(SPRN_IAC4, thread->iac4);
331#endif
332 mtspr(SPRN_DAC1, thread->dac1);
333 mtspr(SPRN_DAC2, thread->dac2);
334#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
335 mtspr(SPRN_DVC1, thread->dvc1);
336 mtspr(SPRN_DVC2, thread->dvc2);
337#endif
338 mtspr(SPRN_DBCR0, thread->dbcr0);
339 mtspr(SPRN_DBCR1, thread->dbcr1);
340#ifdef CONFIG_BOOKE
341 mtspr(SPRN_DBCR2, thread->dbcr2);
342#endif
343}
344/*
345 * Unless neither the old or new thread are making use of the
346 * debug registers, set the debug registers from the values
347 * stored in the new thread.
348 */
349static void switch_booke_debug_regs(struct thread_struct *new_thread)
350{
351 if ((current->thread.dbcr0 & DBCR0_IDM)
352 || (new_thread->dbcr0 & DBCR0_IDM))
353 prime_debug_regs(new_thread);
354}
355#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
356static void set_debug_reg_defaults(struct thread_struct *thread)
357{
358 if (thread->dabr) {
359 thread->dabr = 0;
360 set_dabr(0);
361 }
362}
363#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
364
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365int set_dabr(unsigned long dabr)
366{
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367 __get_cpu_var(current_dabr) = dabr;
368
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369 if (ppc_md.set_dabr)
370 return ppc_md.set_dabr(dabr);
14cf11af 371
791cc501 372 /* XXX should we have a CPU_FTR_HAS_DABR ? */
172ae2e7 373#ifdef CONFIG_PPC_ADV_DEBUG_REGS
d6a61bfc 374 mtspr(SPRN_DAC1, dabr);
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375#ifdef CONFIG_PPC_47x
376 isync();
377#endif
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378#elif defined(CONFIG_PPC_BOOK3S)
379 mtspr(SPRN_DABR, dabr);
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380#endif
381
c6c9eace 382
cab0af98 383 return 0;
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384}
385
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386#ifdef CONFIG_PPC64
387DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
06d67d54 388#endif
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389
390struct task_struct *__switch_to(struct task_struct *prev,
391 struct task_struct *new)
392{
393 struct thread_struct *new_thread, *old_thread;
394 unsigned long flags;
395 struct task_struct *last;
396
397#ifdef CONFIG_SMP
398 /* avoid complexity of lazy save/restore of fpu
399 * by just saving it every time we switch out if
400 * this task used the fpu during the last quantum.
401 *
402 * If it tries to use the fpu again, it'll trap and
403 * reload its fp regs. So we don't have to do a restore
404 * every switch, just a save.
405 * -- Cort
406 */
407 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
408 giveup_fpu(prev);
409#ifdef CONFIG_ALTIVEC
410 /*
411 * If the previous thread used altivec in the last quantum
412 * (thus changing altivec regs) then save them.
413 * We used to check the VRSAVE register but not all apps
414 * set it, so we don't rely on it now (and in fact we need
415 * to save & restore VSCR even if VRSAVE == 0). -- paulus
416 *
417 * On SMP we always save/restore altivec regs just to avoid the
418 * complexity of changing processors.
419 * -- Cort
420 */
421 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
422 giveup_altivec(prev);
14cf11af 423#endif /* CONFIG_ALTIVEC */
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424#ifdef CONFIG_VSX
425 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
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426 /* VMX and FPU registers are already save here */
427 __giveup_vsx(prev);
ce48b210 428#endif /* CONFIG_VSX */
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429#ifdef CONFIG_SPE
430 /*
431 * If the previous thread used spe in the last quantum
432 * (thus changing spe regs) then save them.
433 *
434 * On SMP we always save/restore spe regs just to avoid the
435 * complexity of changing processors.
436 */
437 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
438 giveup_spe(prev);
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439#endif /* CONFIG_SPE */
440
441#else /* CONFIG_SMP */
442#ifdef CONFIG_ALTIVEC
443 /* Avoid the trap. On smp this this never happens since
444 * we don't set last_task_used_altivec -- Cort
445 */
446 if (new->thread.regs && last_task_used_altivec == new)
447 new->thread.regs->msr |= MSR_VEC;
448#endif /* CONFIG_ALTIVEC */
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449#ifdef CONFIG_VSX
450 if (new->thread.regs && last_task_used_vsx == new)
451 new->thread.regs->msr |= MSR_VSX;
452#endif /* CONFIG_VSX */
c0c0d996 453#ifdef CONFIG_SPE
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454 /* Avoid the trap. On smp this this never happens since
455 * we don't set last_task_used_spe
456 */
457 if (new->thread.regs && last_task_used_spe == new)
458 new->thread.regs->msr |= MSR_SPE;
459#endif /* CONFIG_SPE */
c0c0d996 460
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461#endif /* CONFIG_SMP */
462
172ae2e7 463#ifdef CONFIG_PPC_ADV_DEBUG_REGS
3bffb652 464 switch_booke_debug_regs(&new->thread);
c6c9eace 465#else
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466/*
467 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
468 * schedule DABR
469 */
470#ifndef CONFIG_HAVE_HW_BREAKPOINT
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471 if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
472 set_dabr(new->thread.dabr);
5aae8a53 473#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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474#endif
475
c6c9eace 476
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477 new_thread = &new->thread;
478 old_thread = &current->thread;
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479
480#ifdef CONFIG_PPC64
481 /*
482 * Collect processor utilization data per process
483 */
484 if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
485 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
486 long unsigned start_tb, current_tb;
487 start_tb = old_thread->start_tb;
488 cu->current_tb = current_tb = mfspr(SPRN_PURR);
489 old_thread->accum_tb += (current_tb - start_tb);
490 new_thread->start_tb = current_tb;
491 }
492#endif
493
14cf11af 494 local_irq_save(flags);
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495
496 account_system_vtime(current);
81a3843f 497 account_process_vtime(current);
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498 calculate_steal_time();
499
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500 /*
501 * We can't take a PMU exception inside _switch() since there is a
502 * window where the kernel stack SLB and the kernel stack are out
503 * of sync. Hard disable here.
504 */
505 hard_irq_disable();
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506 last = _switch(old_thread, new_thread);
507
508 local_irq_restore(flags);
509
510 return last;
511}
512
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513static int instructions_to_print = 16;
514
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515static void show_instructions(struct pt_regs *regs)
516{
517 int i;
518 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
519 sizeof(int));
520
521 printk("Instruction dump:");
522
523 for (i = 0; i < instructions_to_print; i++) {
524 int instr;
525
526 if (!(i % 8))
527 printk("\n");
528
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529#if !defined(CONFIG_BOOKE)
530 /* If executing with the IMMU off, adjust pc rather
531 * than print XXXXXXXX.
532 */
533 if (!(regs->msr & MSR_IR))
534 pc = (unsigned long)phys_to_virt(pc);
535#endif
536
af308377
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537 /* We use __get_user here *only* to avoid an OOPS on a
538 * bad address because the pc *should* only be a
539 * kernel address.
540 */
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541 if (!__kernel_text_address(pc) ||
542 __get_user(instr, (unsigned int __user *)pc)) {
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543 printk("XXXXXXXX ");
544 } else {
545 if (regs->nip == pc)
546 printk("<%08x> ", instr);
547 else
548 printk("%08x ", instr);
549 }
550
551 pc += sizeof(int);
552 }
553
554 printk("\n");
555}
556
557static struct regbit {
558 unsigned long bit;
559 const char *name;
560} msr_bits[] = {
561 {MSR_EE, "EE"},
562 {MSR_PR, "PR"},
563 {MSR_FP, "FP"},
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564 {MSR_VEC, "VEC"},
565 {MSR_VSX, "VSX"},
06d67d54 566 {MSR_ME, "ME"},
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567 {MSR_CE, "CE"},
568 {MSR_DE, "DE"},
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569 {MSR_IR, "IR"},
570 {MSR_DR, "DR"},
571 {0, NULL}
572};
573
574static void printbits(unsigned long val, struct regbit *bits)
575{
576 const char *sep = "";
577
578 printk("<");
579 for (; bits->bit; ++bits)
580 if (val & bits->bit) {
581 printk("%s%s", sep, bits->name);
582 sep = ",";
583 }
584 printk(">");
585}
586
587#ifdef CONFIG_PPC64
f6f7dde3 588#define REG "%016lx"
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589#define REGS_PER_LINE 4
590#define LAST_VOLATILE 13
591#else
f6f7dde3 592#define REG "%08lx"
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593#define REGS_PER_LINE 8
594#define LAST_VOLATILE 12
595#endif
596
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597void show_regs(struct pt_regs * regs)
598{
599 int i, trap;
600
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601 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
602 regs->nip, regs->link, regs->ctr);
603 printk("REGS: %p TRAP: %04lx %s (%s)\n",
96b644bd 604 regs, regs->trap, print_tainted(), init_utsname()->release);
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605 printk("MSR: "REG" ", regs->msr);
606 printbits(regs->msr, msr_bits);
f6f7dde3 607 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
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608 trap = TRAP(regs);
609 if (trap == 0x300 || trap == 0x600)
172ae2e7 610#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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611 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
612#else
06d67d54 613 printk("DAR: "REG", DSISR: "REG"\n", regs->dar, regs->dsisr);
14170789 614#endif
06d67d54 615 printk("TASK = %p[%d] '%s' THREAD: %p",
19c5870c 616 current, task_pid_nr(current), current->comm, task_thread_info(current));
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617
618#ifdef CONFIG_SMP
79ccd1be 619 printk(" CPU: %d", raw_smp_processor_id());
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620#endif /* CONFIG_SMP */
621
622 for (i = 0; i < 32; i++) {
06d67d54 623 if ((i % REGS_PER_LINE) == 0)
a2367194 624 printk("\nGPR%02d: ", i);
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625 printk(REG " ", regs->gpr[i]);
626 if (i == LAST_VOLATILE && !FULL_REGS(regs))
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627 break;
628 }
629 printk("\n");
630#ifdef CONFIG_KALLSYMS
631 /*
632 * Lookup NIP late so we have the best change of getting the
633 * above info out without failing
634 */
058c78f4
BH
635 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
636 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
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637#endif
638 show_stack(current, (unsigned long *) regs->gpr[1]);
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639 if (!user_mode(regs))
640 show_instructions(regs);
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641}
642
643void exit_thread(void)
644{
48abec07 645 discard_lazy_cpu_state();
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646}
647
648void flush_thread(void)
649{
48abec07 650 discard_lazy_cpu_state();
14cf11af 651
5aae8a53
P
652#ifdef CONFIG_HAVE_HW_BREAKPOINTS
653 flush_ptrace_hw_breakpoint(current);
654#else /* CONFIG_HAVE_HW_BREAKPOINTS */
3bffb652 655 set_debug_reg_defaults(&current->thread);
5aae8a53 656#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
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657}
658
659void
660release_thread(struct task_struct *t)
661{
662}
663
664/*
665 * This gets called before we allocate a new thread and copy
666 * the current task into it.
667 */
668void prepare_to_copy(struct task_struct *tsk)
669{
670 flush_fp_to_thread(current);
671 flush_altivec_to_thread(current);
ce48b210 672 flush_vsx_to_thread(current);
14cf11af 673 flush_spe_to_thread(current);
5aae8a53
P
674#ifdef CONFIG_HAVE_HW_BREAKPOINT
675 flush_ptrace_hw_breakpoint(tsk);
676#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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677}
678
679/*
680 * Copy a thread..
681 */
6f2c55b8 682int copy_thread(unsigned long clone_flags, unsigned long usp,
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683 unsigned long unused, struct task_struct *p,
684 struct pt_regs *regs)
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685{
686 struct pt_regs *childregs, *kregs;
687 extern void ret_from_fork(void);
0cec6fd1 688 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
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689
690 CHECK_FULL_REGS(regs);
691 /* Copy registers */
692 sp -= sizeof(struct pt_regs);
693 childregs = (struct pt_regs *) sp;
694 *childregs = *regs;
695 if ((childregs->msr & MSR_PR) == 0) {
696 /* for kernel thread, set `current' and stackptr in new task */
697 childregs->gpr[1] = sp + sizeof(struct pt_regs);
06d67d54 698#ifdef CONFIG_PPC32
14cf11af 699 childregs->gpr[2] = (unsigned long) p;
06d67d54 700#else
b5e2fc1c 701 clear_tsk_thread_flag(p, TIF_32BIT);
06d67d54 702#endif
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703 p->thread.regs = NULL; /* no user register state */
704 } else {
705 childregs->gpr[1] = usp;
706 p->thread.regs = childregs;
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707 if (clone_flags & CLONE_SETTLS) {
708#ifdef CONFIG_PPC64
709 if (!test_thread_flag(TIF_32BIT))
710 childregs->gpr[13] = childregs->gpr[6];
711 else
712#endif
713 childregs->gpr[2] = childregs->gpr[6];
714 }
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715 }
716 childregs->gpr[3] = 0; /* Result from fork() */
717 sp -= STACK_FRAME_OVERHEAD;
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718
719 /*
720 * The way this works is that at some point in the future
721 * some task will call _switch to switch to the new task.
722 * That will pop off the stack frame created below and start
723 * the new task running at ret_from_fork. The new task will
724 * do some house keeping and then return from the fork or clone
725 * system call, using the stack frame created above.
726 */
727 sp -= sizeof(struct pt_regs);
728 kregs = (struct pt_regs *) sp;
729 sp -= STACK_FRAME_OVERHEAD;
730 p->thread.ksp = sp;
85218827
KG
731 p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
732 _ALIGN_UP(sizeof(struct thread_info), 16);
14cf11af 733
94491685 734#ifdef CONFIG_PPC_STD_MMU_64
06d67d54 735 if (cpu_has_feature(CPU_FTR_SLB)) {
1189be65 736 unsigned long sp_vsid;
3c726f8d 737 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
06d67d54 738
1189be65
PM
739 if (cpu_has_feature(CPU_FTR_1T_SEGMENT))
740 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
741 << SLB_VSID_SHIFT_1T;
742 else
743 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
744 << SLB_VSID_SHIFT;
3c726f8d 745 sp_vsid |= SLB_VSID_KERNEL | llp;
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746 p->thread.ksp_vsid = sp_vsid;
747 }
747bea91 748#endif /* CONFIG_PPC_STD_MMU_64 */
06d67d54
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749
750 /*
751 * The PPC64 ABI makes use of a TOC to contain function
752 * pointers. The function (ret_from_except) is actually a pointer
753 * to the TOC entry. The first entry is a pointer to the actual
754 * function.
755 */
747bea91 756#ifdef CONFIG_PPC64
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757 kregs->nip = *((unsigned long *)ret_from_fork);
758#else
759 kregs->nip = (unsigned long)ret_from_fork;
06d67d54 760#endif
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761
762 return 0;
763}
764
765/*
766 * Set up a thread for executing a new program
767 */
06d67d54 768void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
14cf11af 769{
90eac727
ME
770#ifdef CONFIG_PPC64
771 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
772#endif
773
14cf11af 774 set_fs(USER_DS);
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775
776 /*
777 * If we exec out of a kernel thread then thread.regs will not be
778 * set. Do it now.
779 */
780 if (!current->thread.regs) {
0cec6fd1
AV
781 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
782 current->thread.regs = regs - 1;
06d67d54
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783 }
784
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785 memset(regs->gpr, 0, sizeof(regs->gpr));
786 regs->ctr = 0;
787 regs->link = 0;
788 regs->xer = 0;
789 regs->ccr = 0;
14cf11af 790 regs->gpr[1] = sp;
06d67d54 791
474f8196
RM
792 /*
793 * We have just cleared all the nonvolatile GPRs, so make
794 * FULL_REGS(regs) return true. This is necessary to allow
795 * ptrace to examine the thread immediately after exec.
796 */
797 regs->trap &= ~1UL;
798
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799#ifdef CONFIG_PPC32
800 regs->mq = 0;
801 regs->nip = start;
14cf11af 802 regs->msr = MSR_USER;
06d67d54 803#else
d4bf9a78 804 if (!test_thread_flag(TIF_32BIT)) {
90eac727 805 unsigned long entry, toc;
06d67d54
PM
806
807 /* start is a relocated pointer to the function descriptor for
808 * the elf _start routine. The first entry in the function
809 * descriptor is the entry address of _start and the second
810 * entry is the TOC value we need to use.
811 */
812 __get_user(entry, (unsigned long __user *)start);
813 __get_user(toc, (unsigned long __user *)start+1);
814
815 /* Check whether the e_entry function descriptor entries
816 * need to be relocated before we can use them.
817 */
818 if (load_addr != 0) {
819 entry += load_addr;
820 toc += load_addr;
821 }
822 regs->nip = entry;
823 regs->gpr[2] = toc;
824 regs->msr = MSR_USER64;
d4bf9a78
SR
825 } else {
826 regs->nip = start;
827 regs->gpr[2] = 0;
828 regs->msr = MSR_USER32;
06d67d54
PM
829 }
830#endif
831
48abec07 832 discard_lazy_cpu_state();
ce48b210
MN
833#ifdef CONFIG_VSX
834 current->thread.used_vsr = 0;
835#endif
14cf11af 836 memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
25c8a78b 837 current->thread.fpscr.val = 0;
14cf11af
PM
838#ifdef CONFIG_ALTIVEC
839 memset(current->thread.vr, 0, sizeof(current->thread.vr));
840 memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
06d67d54 841 current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */
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PM
842 current->thread.vrsave = 0;
843 current->thread.used_vr = 0;
844#endif /* CONFIG_ALTIVEC */
845#ifdef CONFIG_SPE
846 memset(current->thread.evr, 0, sizeof(current->thread.evr));
847 current->thread.acc = 0;
848 current->thread.spefscr = 0;
849 current->thread.used_spe = 0;
850#endif /* CONFIG_SPE */
851}
852
853#define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
854 | PR_FP_EXC_RES | PR_FP_EXC_INV)
855
856int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
857{
858 struct pt_regs *regs = tsk->thread.regs;
859
860 /* This is a bit hairy. If we are an SPE enabled processor
861 * (have embedded fp) we store the IEEE exception enable flags in
862 * fpexc_mode. fpexc_mode is also used for setting FP exception
863 * mode (asyn, precise, disabled) for 'Classic' FP. */
864 if (val & PR_FP_EXC_SW_ENABLE) {
865#ifdef CONFIG_SPE
5e14d21e
KG
866 if (cpu_has_feature(CPU_FTR_SPE)) {
867 tsk->thread.fpexc_mode = val &
868 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
869 return 0;
870 } else {
871 return -EINVAL;
872 }
14cf11af
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873#else
874 return -EINVAL;
875#endif
14cf11af 876 }
06d67d54
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877
878 /* on a CONFIG_SPE this does not hurt us. The bits that
879 * __pack_fe01 use do not overlap with bits used for
880 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
881 * on CONFIG_SPE implementations are reserved so writing to
882 * them does not change anything */
883 if (val > PR_FP_EXC_PRECISE)
884 return -EINVAL;
885 tsk->thread.fpexc_mode = __pack_fe01(val);
886 if (regs != NULL && (regs->msr & MSR_FP) != 0)
887 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
888 | tsk->thread.fpexc_mode;
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889 return 0;
890}
891
892int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
893{
894 unsigned int val;
895
896 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
897#ifdef CONFIG_SPE
5e14d21e
KG
898 if (cpu_has_feature(CPU_FTR_SPE))
899 val = tsk->thread.fpexc_mode;
900 else
901 return -EINVAL;
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902#else
903 return -EINVAL;
904#endif
905 else
906 val = __unpack_fe01(tsk->thread.fpexc_mode);
907 return put_user(val, (unsigned int __user *) adr);
908}
909
fab5db97
PM
910int set_endian(struct task_struct *tsk, unsigned int val)
911{
912 struct pt_regs *regs = tsk->thread.regs;
913
914 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
915 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
916 return -EINVAL;
917
918 if (regs == NULL)
919 return -EINVAL;
920
921 if (val == PR_ENDIAN_BIG)
922 regs->msr &= ~MSR_LE;
923 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
924 regs->msr |= MSR_LE;
925 else
926 return -EINVAL;
927
928 return 0;
929}
930
931int get_endian(struct task_struct *tsk, unsigned long adr)
932{
933 struct pt_regs *regs = tsk->thread.regs;
934 unsigned int val;
935
936 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
937 !cpu_has_feature(CPU_FTR_REAL_LE))
938 return -EINVAL;
939
940 if (regs == NULL)
941 return -EINVAL;
942
943 if (regs->msr & MSR_LE) {
944 if (cpu_has_feature(CPU_FTR_REAL_LE))
945 val = PR_ENDIAN_LITTLE;
946 else
947 val = PR_ENDIAN_PPC_LITTLE;
948 } else
949 val = PR_ENDIAN_BIG;
950
951 return put_user(val, (unsigned int __user *)adr);
952}
953
e9370ae1
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954int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
955{
956 tsk->thread.align_ctl = val;
957 return 0;
958}
959
960int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
961{
962 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
963}
964
06d67d54
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965#define TRUNC_PTR(x) ((typeof(x))(((unsigned long)(x)) & 0xffffffff))
966
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967int sys_clone(unsigned long clone_flags, unsigned long usp,
968 int __user *parent_tidp, void __user *child_threadptr,
969 int __user *child_tidp, int p6,
970 struct pt_regs *regs)
971{
972 CHECK_FULL_REGS(regs);
973 if (usp == 0)
974 usp = regs->gpr[1]; /* stack pointer for child */
06d67d54
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975#ifdef CONFIG_PPC64
976 if (test_thread_flag(TIF_32BIT)) {
977 parent_tidp = TRUNC_PTR(parent_tidp);
978 child_tidp = TRUNC_PTR(child_tidp);
979 }
980#endif
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981 return do_fork(clone_flags, usp, regs, 0, parent_tidp, child_tidp);
982}
983
984int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
985 unsigned long p4, unsigned long p5, unsigned long p6,
986 struct pt_regs *regs)
987{
988 CHECK_FULL_REGS(regs);
989 return do_fork(SIGCHLD, regs->gpr[1], regs, 0, NULL, NULL);
990}
991
992int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
993 unsigned long p4, unsigned long p5, unsigned long p6,
994 struct pt_regs *regs)
995{
996 CHECK_FULL_REGS(regs);
997 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->gpr[1],
998 regs, 0, NULL, NULL);
999}
1000
1001int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
1002 unsigned long a3, unsigned long a4, unsigned long a5,
1003 struct pt_regs *regs)
1004{
1005 int error;
06d67d54 1006 char *filename;
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1007
1008 filename = getname((char __user *) a0);
1009 error = PTR_ERR(filename);
1010 if (IS_ERR(filename))
1011 goto out;
1012 flush_fp_to_thread(current);
1013 flush_altivec_to_thread(current);
1014 flush_spe_to_thread(current);
20c8c210
PM
1015 error = do_execve(filename, (char __user * __user *) a1,
1016 (char __user * __user *) a2, regs);
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1017 putname(filename);
1018out:
1019 return error;
1020}
1021
bb72c481
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1022static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1023 unsigned long nbytes)
1024{
1025 unsigned long stack_page;
1026 unsigned long cpu = task_cpu(p);
1027
1028 /*
1029 * Avoid crashing if the stack has overflowed and corrupted
1030 * task_cpu(p), which is in the thread_info struct.
1031 */
1032 if (cpu < NR_CPUS && cpu_possible(cpu)) {
1033 stack_page = (unsigned long) hardirq_ctx[cpu];
1034 if (sp >= stack_page + sizeof(struct thread_struct)
1035 && sp <= stack_page + THREAD_SIZE - nbytes)
1036 return 1;
1037
1038 stack_page = (unsigned long) softirq_ctx[cpu];
1039 if (sp >= stack_page + sizeof(struct thread_struct)
1040 && sp <= stack_page + THREAD_SIZE - nbytes)
1041 return 1;
1042 }
1043 return 0;
1044}
1045
2f25194d 1046int validate_sp(unsigned long sp, struct task_struct *p,
14cf11af
PM
1047 unsigned long nbytes)
1048{
0cec6fd1 1049 unsigned long stack_page = (unsigned long)task_stack_page(p);
14cf11af
PM
1050
1051 if (sp >= stack_page + sizeof(struct thread_struct)
1052 && sp <= stack_page + THREAD_SIZE - nbytes)
1053 return 1;
1054
bb72c481 1055 return valid_irq_stack(sp, p, nbytes);
14cf11af
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1056}
1057
2f25194d
AB
1058EXPORT_SYMBOL(validate_sp);
1059
14cf11af
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1060unsigned long get_wchan(struct task_struct *p)
1061{
1062 unsigned long ip, sp;
1063 int count = 0;
1064
1065 if (!p || p == current || p->state == TASK_RUNNING)
1066 return 0;
1067
1068 sp = p->thread.ksp;
ec2b36b9 1069 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
14cf11af
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1070 return 0;
1071
1072 do {
1073 sp = *(unsigned long *)sp;
ec2b36b9 1074 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
14cf11af
PM
1075 return 0;
1076 if (count > 0) {
ec2b36b9 1077 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
14cf11af
PM
1078 if (!in_sched_functions(ip))
1079 return ip;
1080 }
1081 } while (count++ < 16);
1082 return 0;
1083}
06d67d54 1084
c4d04be1 1085static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
06d67d54
PM
1086
1087void show_stack(struct task_struct *tsk, unsigned long *stack)
1088{
1089 unsigned long sp, ip, lr, newsp;
1090 int count = 0;
1091 int firstframe = 1;
6794c782
SR
1092#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1093 int curr_frame = current->curr_ret_stack;
1094 extern void return_to_handler(void);
9135c3cc
SR
1095 unsigned long rth = (unsigned long)return_to_handler;
1096 unsigned long mrth = -1;
6794c782 1097#ifdef CONFIG_PPC64
9135c3cc
SR
1098 extern void mod_return_to_handler(void);
1099 rth = *(unsigned long *)rth;
1100 mrth = (unsigned long)mod_return_to_handler;
1101 mrth = *(unsigned long *)mrth;
6794c782
SR
1102#endif
1103#endif
06d67d54
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1104
1105 sp = (unsigned long) stack;
1106 if (tsk == NULL)
1107 tsk = current;
1108 if (sp == 0) {
1109 if (tsk == current)
1110 asm("mr %0,1" : "=r" (sp));
1111 else
1112 sp = tsk->thread.ksp;
1113 }
1114
1115 lr = 0;
1116 printk("Call Trace:\n");
1117 do {
ec2b36b9 1118 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
06d67d54
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1119 return;
1120
1121 stack = (unsigned long *) sp;
1122 newsp = stack[0];
ec2b36b9 1123 ip = stack[STACK_FRAME_LR_SAVE];
06d67d54 1124 if (!firstframe || ip != lr) {
058c78f4 1125 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
6794c782 1126#ifdef CONFIG_FUNCTION_GRAPH_TRACER
9135c3cc 1127 if ((ip == rth || ip == mrth) && curr_frame >= 0) {
6794c782
SR
1128 printk(" (%pS)",
1129 (void *)current->ret_stack[curr_frame].ret);
1130 curr_frame--;
1131 }
1132#endif
06d67d54
PM
1133 if (firstframe)
1134 printk(" (unreliable)");
1135 printk("\n");
1136 }
1137 firstframe = 0;
1138
1139 /*
1140 * See if this is an exception frame.
1141 * We look for the "regshere" marker in the current frame.
1142 */
ec2b36b9
BH
1143 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1144 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
06d67d54
PM
1145 struct pt_regs *regs = (struct pt_regs *)
1146 (sp + STACK_FRAME_OVERHEAD);
06d67d54 1147 lr = regs->link;
058c78f4
BH
1148 printk("--- Exception: %lx at %pS\n LR = %pS\n",
1149 regs->trap, (void *)regs->nip, (void *)lr);
06d67d54
PM
1150 firstframe = 1;
1151 }
1152
1153 sp = newsp;
1154 } while (count++ < kstack_depth_to_print);
1155}
1156
1157void dump_stack(void)
1158{
1159 show_stack(current, NULL);
1160}
1161EXPORT_SYMBOL(dump_stack);
cb2c9b27
AB
1162
1163#ifdef CONFIG_PPC64
1164void ppc64_runlatch_on(void)
1165{
1166 unsigned long ctrl;
1167
1168 if (cpu_has_feature(CPU_FTR_CTRL) && !test_thread_flag(TIF_RUNLATCH)) {
1169 HMT_medium();
1170
1171 ctrl = mfspr(SPRN_CTRLF);
1172 ctrl |= CTRL_RUNLATCH;
1173 mtspr(SPRN_CTRLT, ctrl);
1174
1175 set_thread_flag(TIF_RUNLATCH);
1176 }
1177}
1178
1179void ppc64_runlatch_off(void)
1180{
1181 unsigned long ctrl;
1182
1183 if (cpu_has_feature(CPU_FTR_CTRL) && test_thread_flag(TIF_RUNLATCH)) {
1184 HMT_medium();
1185
1186 clear_thread_flag(TIF_RUNLATCH);
1187
1188 ctrl = mfspr(SPRN_CTRLF);
1189 ctrl &= ~CTRL_RUNLATCH;
1190 mtspr(SPRN_CTRLT, ctrl);
1191 }
1192}
1193#endif
f6a61680
BH
1194
1195#if THREAD_SHIFT < PAGE_SHIFT
1196
1197static struct kmem_cache *thread_info_cache;
1198
1199struct thread_info *alloc_thread_info(struct task_struct *tsk)
1200{
1201 struct thread_info *ti;
1202
1203 ti = kmem_cache_alloc(thread_info_cache, GFP_KERNEL);
1204 if (unlikely(ti == NULL))
1205 return NULL;
1206#ifdef CONFIG_DEBUG_STACK_USAGE
1207 memset(ti, 0, THREAD_SIZE);
1208#endif
1209 return ti;
1210}
1211
1212void free_thread_info(struct thread_info *ti)
1213{
1214 kmem_cache_free(thread_info_cache, ti);
1215}
1216
1217void thread_info_cache_init(void)
1218{
1219 thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE,
1220 THREAD_SIZE, 0, NULL);
1221 BUG_ON(thread_info_cache == NULL);
1222}
1223
1224#endif /* THREAD_SHIFT < PAGE_SHIFT */
d839088c
AB
1225
1226unsigned long arch_align_stack(unsigned long sp)
1227{
1228 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1229 sp -= get_random_int() & ~PAGE_MASK;
1230 return sp & ~0xf;
1231}
912f9ee2
AB
1232
1233static inline unsigned long brk_rnd(void)
1234{
1235 unsigned long rnd = 0;
1236
1237 /* 8MB for 32bit, 1GB for 64bit */
1238 if (is_32bit_task())
1239 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1240 else
1241 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1242
1243 return rnd << PAGE_SHIFT;
1244}
1245
1246unsigned long arch_randomize_brk(struct mm_struct *mm)
1247{
8bbde7a7
AB
1248 unsigned long base = mm->brk;
1249 unsigned long ret;
1250
ce7a35c7 1251#ifdef CONFIG_PPC_STD_MMU_64
8bbde7a7
AB
1252 /*
1253 * If we are using 1TB segments and we are allowed to randomise
1254 * the heap, we can put it above 1TB so it is backed by a 1TB
1255 * segment. Otherwise the heap will be in the bottom 1TB
1256 * which always uses 256MB segments and this may result in a
1257 * performance penalty.
1258 */
1259 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1260 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1261#endif
1262
1263 ret = PAGE_ALIGN(base + brk_rnd());
912f9ee2
AB
1264
1265 if (ret < mm->brk)
1266 return mm->brk;
1267
1268 return ret;
1269}
501cb16d
AB
1270
1271unsigned long randomize_et_dyn(unsigned long base)
1272{
1273 unsigned long ret = PAGE_ALIGN(base + brk_rnd());
1274
1275 if (ret < base)
1276 return base;
1277
1278 return ret;
1279}