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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Derived from "arch/m68k/kernel/ptrace.c" | |
6 | * Copyright (C) 1994 by Hamish Macdonald | |
7 | * Taken from linux/kernel/ptrace.c and modified for M680x0. | |
8 | * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds | |
9 | * | |
10 | * Modified by Cort Dougan (cort@hq.fsmlabs.com) | |
b123923d | 11 | * and Paul Mackerras (paulus@samba.org). |
1da177e4 LT |
12 | * |
13 | * This file is subject to the terms and conditions of the GNU General | |
14 | * Public License. See the file README.legal in the main directory of | |
15 | * this archive for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/errno.h> |
23 | #include <linux/ptrace.h> | |
f65255e8 | 24 | #include <linux/regset.h> |
4f72c427 | 25 | #include <linux/tracehook.h> |
3caf06c6 | 26 | #include <linux/elf.h> |
1da177e4 LT |
27 | #include <linux/user.h> |
28 | #include <linux/security.h> | |
7ed20e1a | 29 | #include <linux/signal.h> |
ea9c102c DW |
30 | #include <linux/seccomp.h> |
31 | #include <linux/audit.h> | |
02424d89 | 32 | #include <trace/syscall.h> |
5aae8a53 P |
33 | #include <linux/hw_breakpoint.h> |
34 | #include <linux/perf_event.h> | |
22ecbe8d | 35 | #include <linux/context_tracking.h> |
1da177e4 LT |
36 | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/pgtable.h> | |
ae3a197e | 40 | #include <asm/switch_to.h> |
21a62902 | 41 | |
02424d89 IM |
42 | #define CREATE_TRACE_POINTS |
43 | #include <trace/events/syscalls.h> | |
44 | ||
359e4284 MS |
45 | /* |
46 | * The parameter save area on the stack is used to store arguments being passed | |
47 | * to callee function and is located at fixed offset from stack pointer. | |
48 | */ | |
49 | #ifdef CONFIG_PPC32 | |
50 | #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */ | |
51 | #else /* CONFIG_PPC32 */ | |
52 | #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */ | |
53 | #endif | |
54 | ||
55 | struct pt_regs_offset { | |
56 | const char *name; | |
57 | int offset; | |
58 | }; | |
59 | ||
60 | #define STR(s) #s /* convert to string */ | |
61 | #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} | |
62 | #define GPR_OFFSET_NAME(num) \ | |
343c3327 | 63 | {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \ |
359e4284 MS |
64 | {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])} |
65 | #define REG_OFFSET_END {.name = NULL, .offset = 0} | |
66 | ||
8c13f599 | 67 | #define TVSO(f) (offsetof(struct thread_vr_state, f)) |
9d3918f7 | 68 | #define TFSO(f) (offsetof(struct thread_fp_state, f)) |
08e1c01d | 69 | #define TSO(f) (offsetof(struct thread_struct, f)) |
8c13f599 | 70 | |
359e4284 MS |
71 | static const struct pt_regs_offset regoffset_table[] = { |
72 | GPR_OFFSET_NAME(0), | |
73 | GPR_OFFSET_NAME(1), | |
74 | GPR_OFFSET_NAME(2), | |
75 | GPR_OFFSET_NAME(3), | |
76 | GPR_OFFSET_NAME(4), | |
77 | GPR_OFFSET_NAME(5), | |
78 | GPR_OFFSET_NAME(6), | |
79 | GPR_OFFSET_NAME(7), | |
80 | GPR_OFFSET_NAME(8), | |
81 | GPR_OFFSET_NAME(9), | |
82 | GPR_OFFSET_NAME(10), | |
83 | GPR_OFFSET_NAME(11), | |
84 | GPR_OFFSET_NAME(12), | |
85 | GPR_OFFSET_NAME(13), | |
86 | GPR_OFFSET_NAME(14), | |
87 | GPR_OFFSET_NAME(15), | |
88 | GPR_OFFSET_NAME(16), | |
89 | GPR_OFFSET_NAME(17), | |
90 | GPR_OFFSET_NAME(18), | |
91 | GPR_OFFSET_NAME(19), | |
92 | GPR_OFFSET_NAME(20), | |
93 | GPR_OFFSET_NAME(21), | |
94 | GPR_OFFSET_NAME(22), | |
95 | GPR_OFFSET_NAME(23), | |
96 | GPR_OFFSET_NAME(24), | |
97 | GPR_OFFSET_NAME(25), | |
98 | GPR_OFFSET_NAME(26), | |
99 | GPR_OFFSET_NAME(27), | |
100 | GPR_OFFSET_NAME(28), | |
101 | GPR_OFFSET_NAME(29), | |
102 | GPR_OFFSET_NAME(30), | |
103 | GPR_OFFSET_NAME(31), | |
104 | REG_OFFSET_NAME(nip), | |
105 | REG_OFFSET_NAME(msr), | |
106 | REG_OFFSET_NAME(ctr), | |
107 | REG_OFFSET_NAME(link), | |
108 | REG_OFFSET_NAME(xer), | |
109 | REG_OFFSET_NAME(ccr), | |
110 | #ifdef CONFIG_PPC64 | |
111 | REG_OFFSET_NAME(softe), | |
112 | #else | |
113 | REG_OFFSET_NAME(mq), | |
114 | #endif | |
115 | REG_OFFSET_NAME(trap), | |
116 | REG_OFFSET_NAME(dar), | |
117 | REG_OFFSET_NAME(dsisr), | |
118 | REG_OFFSET_END, | |
119 | }; | |
120 | ||
121 | /** | |
122 | * regs_query_register_offset() - query register offset from its name | |
123 | * @name: the name of a register | |
124 | * | |
125 | * regs_query_register_offset() returns the offset of a register in struct | |
126 | * pt_regs from its name. If the name is invalid, this returns -EINVAL; | |
127 | */ | |
128 | int regs_query_register_offset(const char *name) | |
129 | { | |
130 | const struct pt_regs_offset *roff; | |
131 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
132 | if (!strcmp(roff->name, name)) | |
133 | return roff->offset; | |
134 | return -EINVAL; | |
135 | } | |
136 | ||
137 | /** | |
138 | * regs_query_register_name() - query register name from its offset | |
139 | * @offset: the offset of a register in struct pt_regs. | |
140 | * | |
141 | * regs_query_register_name() returns the name of a register from its | |
142 | * offset in struct pt_regs. If the @offset is invalid, this returns NULL; | |
143 | */ | |
144 | const char *regs_query_register_name(unsigned int offset) | |
145 | { | |
146 | const struct pt_regs_offset *roff; | |
147 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
148 | if (roff->offset == offset) | |
149 | return roff->name; | |
150 | return NULL; | |
151 | } | |
152 | ||
abd06505 BH |
153 | /* |
154 | * does not yet catch signals sent when the child dies. | |
155 | * in exit.c or in signal.c. | |
156 | */ | |
157 | ||
158 | /* | |
159 | * Set of msr bits that gdb can change on behalf of a process. | |
160 | */ | |
172ae2e7 | 161 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
abd06505 | 162 | #define MSR_DEBUGCHANGE 0 |
1da177e4 | 163 | #else |
abd06505 | 164 | #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) |
1da177e4 | 165 | #endif |
acd89828 | 166 | |
1da177e4 | 167 | /* |
abd06505 | 168 | * Max register writeable via put_reg |
1da177e4 | 169 | */ |
abd06505 BH |
170 | #ifdef CONFIG_PPC32 |
171 | #define PT_MAX_PUT_REG PT_MQ | |
172 | #else | |
173 | #define PT_MAX_PUT_REG PT_CCR | |
174 | #endif | |
1da177e4 | 175 | |
26f77130 RM |
176 | static unsigned long get_user_msr(struct task_struct *task) |
177 | { | |
178 | return task->thread.regs->msr | task->thread.fpexc_mode; | |
179 | } | |
180 | ||
181 | static int set_user_msr(struct task_struct *task, unsigned long msr) | |
182 | { | |
183 | task->thread.regs->msr &= ~MSR_DEBUGCHANGE; | |
184 | task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; | |
185 | return 0; | |
186 | } | |
187 | ||
25847fb1 AK |
188 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
189 | static unsigned long get_user_ckpt_msr(struct task_struct *task) | |
190 | { | |
191 | return task->thread.ckpt_regs.msr | task->thread.fpexc_mode; | |
192 | } | |
193 | ||
194 | static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr) | |
195 | { | |
196 | task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE; | |
197 | task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE; | |
198 | return 0; | |
199 | } | |
200 | ||
201 | static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap) | |
202 | { | |
203 | task->thread.ckpt_regs.trap = trap & 0xfff0; | |
204 | return 0; | |
205 | } | |
206 | #endif | |
207 | ||
1715a826 | 208 | #ifdef CONFIG_PPC64 |
ee4a3916 | 209 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 | 210 | { |
ee4a3916 AK |
211 | *data = task->thread.dscr; |
212 | return 0; | |
1715a826 AK |
213 | } |
214 | ||
215 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
216 | { | |
217 | task->thread.dscr = dscr; | |
218 | task->thread.dscr_inherit = 1; | |
219 | return 0; | |
220 | } | |
221 | #else | |
ee4a3916 | 222 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 AK |
223 | { |
224 | return -EIO; | |
225 | } | |
226 | ||
227 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
228 | { | |
229 | return -EIO; | |
230 | } | |
231 | #endif | |
232 | ||
26f77130 RM |
233 | /* |
234 | * We prevent mucking around with the reserved area of trap | |
235 | * which are used internally by the kernel. | |
236 | */ | |
237 | static int set_user_trap(struct task_struct *task, unsigned long trap) | |
238 | { | |
239 | task->thread.regs->trap = trap & 0xfff0; | |
240 | return 0; | |
241 | } | |
242 | ||
865418d8 BH |
243 | /* |
244 | * Get contents of register REGNO in task TASK. | |
245 | */ | |
ee4a3916 | 246 | int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data) |
865418d8 | 247 | { |
ee4a3916 | 248 | if ((task->thread.regs == NULL) || !data) |
865418d8 BH |
249 | return -EIO; |
250 | ||
ee4a3916 AK |
251 | if (regno == PT_MSR) { |
252 | *data = get_user_msr(task); | |
253 | return 0; | |
254 | } | |
865418d8 | 255 | |
1715a826 | 256 | if (regno == PT_DSCR) |
ee4a3916 | 257 | return get_user_dscr(task, data); |
1715a826 | 258 | |
ee4a3916 AK |
259 | if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) { |
260 | *data = ((unsigned long *)task->thread.regs)[regno]; | |
261 | return 0; | |
262 | } | |
865418d8 BH |
263 | |
264 | return -EIO; | |
265 | } | |
266 | ||
267 | /* | |
268 | * Write contents of register REGNO in task TASK. | |
269 | */ | |
270 | int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data) | |
271 | { | |
272 | if (task->thread.regs == NULL) | |
273 | return -EIO; | |
274 | ||
26f77130 RM |
275 | if (regno == PT_MSR) |
276 | return set_user_msr(task, data); | |
277 | if (regno == PT_TRAP) | |
278 | return set_user_trap(task, data); | |
1715a826 AK |
279 | if (regno == PT_DSCR) |
280 | return set_user_dscr(task, data); | |
26f77130 RM |
281 | |
282 | if (regno <= PT_MAX_PUT_REG) { | |
865418d8 BH |
283 | ((unsigned long *)task->thread.regs)[regno] = data; |
284 | return 0; | |
285 | } | |
286 | return -EIO; | |
287 | } | |
288 | ||
44dd3f50 RM |
289 | static int gpr_get(struct task_struct *target, const struct user_regset *regset, |
290 | unsigned int pos, unsigned int count, | |
291 | void *kbuf, void __user *ubuf) | |
292 | { | |
a71f5d5d | 293 | int i, ret; |
44dd3f50 RM |
294 | |
295 | if (target->thread.regs == NULL) | |
296 | return -EIO; | |
297 | ||
a71f5d5d MW |
298 | if (!FULL_REGS(target->thread.regs)) { |
299 | /* We have a partial register set. Fill 14-31 with bogus values */ | |
300 | for (i = 14; i < 32; i++) | |
301 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
302 | } | |
44dd3f50 RM |
303 | |
304 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
305 | target->thread.regs, | |
306 | 0, offsetof(struct pt_regs, msr)); | |
307 | if (!ret) { | |
308 | unsigned long msr = get_user_msr(target); | |
309 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
310 | offsetof(struct pt_regs, msr), | |
311 | offsetof(struct pt_regs, msr) + | |
312 | sizeof(msr)); | |
313 | } | |
314 | ||
315 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
316 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
317 | ||
318 | if (!ret) | |
319 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
320 | &target->thread.regs->orig_gpr3, | |
321 | offsetof(struct pt_regs, orig_gpr3), | |
322 | sizeof(struct pt_regs)); | |
323 | if (!ret) | |
324 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
325 | sizeof(struct pt_regs), -1); | |
326 | ||
327 | return ret; | |
328 | } | |
329 | ||
330 | static int gpr_set(struct task_struct *target, const struct user_regset *regset, | |
331 | unsigned int pos, unsigned int count, | |
332 | const void *kbuf, const void __user *ubuf) | |
333 | { | |
334 | unsigned long reg; | |
335 | int ret; | |
336 | ||
337 | if (target->thread.regs == NULL) | |
338 | return -EIO; | |
339 | ||
340 | CHECK_FULL_REGS(target->thread.regs); | |
341 | ||
342 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
343 | target->thread.regs, | |
344 | 0, PT_MSR * sizeof(reg)); | |
345 | ||
346 | if (!ret && count > 0) { | |
347 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
348 | PT_MSR * sizeof(reg), | |
349 | (PT_MSR + 1) * sizeof(reg)); | |
350 | if (!ret) | |
351 | ret = set_user_msr(target, reg); | |
352 | } | |
353 | ||
354 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
355 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
356 | ||
357 | if (!ret) | |
358 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
359 | &target->thread.regs->orig_gpr3, | |
360 | PT_ORIG_R3 * sizeof(reg), | |
361 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
362 | ||
363 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
364 | ret = user_regset_copyin_ignore( | |
365 | &pos, &count, &kbuf, &ubuf, | |
366 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
367 | PT_TRAP * sizeof(reg)); | |
368 | ||
369 | if (!ret && count > 0) { | |
370 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
371 | PT_TRAP * sizeof(reg), | |
372 | (PT_TRAP + 1) * sizeof(reg)); | |
373 | if (!ret) | |
374 | ret = set_user_trap(target, reg); | |
375 | } | |
376 | ||
377 | if (!ret) | |
378 | ret = user_regset_copyin_ignore( | |
379 | &pos, &count, &kbuf, &ubuf, | |
380 | (PT_TRAP + 1) * sizeof(reg), -1); | |
381 | ||
382 | return ret; | |
383 | } | |
865418d8 | 384 | |
1ec8549d AK |
385 | /* |
386 | * When the transaction is active, 'transact_fp' holds the current running | |
387 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
388 | * value of all FPR registers for the current transaction. When transaction | |
389 | * is not active 'fp_state' holds the current running state of all the FPR | |
390 | * registers. So this function which returns the current running values of | |
391 | * all the FPR registers, needs to know whether any transaction is active | |
392 | * or not. | |
393 | * | |
394 | * Userspace interface buffer layout: | |
395 | * | |
396 | * struct data { | |
397 | * u64 fpr[32]; | |
398 | * u64 fpscr; | |
399 | * }; | |
400 | * | |
401 | * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM | |
402 | * which determines the final code in this function. All the combinations of | |
403 | * these two config options are possible except the one below as transactional | |
404 | * memory config pulls in CONFIG_VSX automatically. | |
405 | * | |
406 | * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
407 | */ | |
f65255e8 RM |
408 | static int fpr_get(struct task_struct *target, const struct user_regset *regset, |
409 | unsigned int pos, unsigned int count, | |
410 | void *kbuf, void __user *ubuf) | |
411 | { | |
c6e6771b | 412 | #ifdef CONFIG_VSX |
de79f7b9 | 413 | u64 buf[33]; |
c6e6771b MN |
414 | int i; |
415 | #endif | |
f65255e8 RM |
416 | flush_fp_to_thread(target); |
417 | ||
1ec8549d AK |
418 | #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
419 | /* copy to local buffer then write that out */ | |
420 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
421 | flush_altivec_to_thread(target); | |
422 | flush_tmregs_to_thread(target); | |
423 | for (i = 0; i < 32 ; i++) | |
424 | buf[i] = target->thread.TS_TRANS_FPR(i); | |
425 | buf[32] = target->thread.transact_fp.fpscr; | |
426 | } else { | |
427 | for (i = 0; i < 32 ; i++) | |
428 | buf[i] = target->thread.TS_FPR(i); | |
429 | buf[32] = target->thread.fp_state.fpscr; | |
430 | } | |
431 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
432 | #endif | |
433 | ||
434 | #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
c6e6771b MN |
435 | /* copy to local buffer then write that out */ |
436 | for (i = 0; i < 32 ; i++) | |
437 | buf[i] = target->thread.TS_FPR(i); | |
de79f7b9 | 438 | buf[32] = target->thread.fp_state.fpscr; |
c6e6771b | 439 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); |
1ec8549d | 440 | #endif |
c6e6771b | 441 | |
1ec8549d | 442 | #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
de79f7b9 | 443 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 444 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
445 | |
446 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 447 | &target->thread.fp_state, 0, -1); |
c6e6771b | 448 | #endif |
f65255e8 RM |
449 | } |
450 | ||
1ec8549d AK |
451 | /* |
452 | * When the transaction is active, 'transact_fp' holds the current running | |
453 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
454 | * value of all FPR registers for the current transaction. When transaction | |
455 | * is not active 'fp_state' holds the current running state of all the FPR | |
456 | * registers. So this function which setss the current running values of | |
457 | * all the FPR registers, needs to know whether any transaction is active | |
458 | * or not. | |
459 | * | |
460 | * Userspace interface buffer layout: | |
461 | * | |
462 | * struct data { | |
463 | * u64 fpr[32]; | |
464 | * u64 fpscr; | |
465 | * }; | |
466 | * | |
467 | * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM | |
468 | * which determines the final code in this function. All the combinations of | |
469 | * these two config options are possible except the one below as transactional | |
470 | * memory config pulls in CONFIG_VSX automatically. | |
471 | * | |
472 | * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
473 | */ | |
f65255e8 RM |
474 | static int fpr_set(struct task_struct *target, const struct user_regset *regset, |
475 | unsigned int pos, unsigned int count, | |
476 | const void *kbuf, const void __user *ubuf) | |
477 | { | |
c6e6771b | 478 | #ifdef CONFIG_VSX |
de79f7b9 | 479 | u64 buf[33]; |
c6e6771b MN |
480 | int i; |
481 | #endif | |
f65255e8 RM |
482 | flush_fp_to_thread(target); |
483 | ||
1ec8549d AK |
484 | #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
485 | /* copy to local buffer then write that out */ | |
486 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
487 | if (i) | |
488 | return i; | |
489 | ||
490 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
491 | flush_altivec_to_thread(target); | |
492 | flush_tmregs_to_thread(target); | |
493 | for (i = 0; i < 32 ; i++) | |
494 | target->thread.TS_TRANS_FPR(i) = buf[i]; | |
495 | target->thread.transact_fp.fpscr = buf[32]; | |
496 | } else { | |
497 | for (i = 0; i < 32 ; i++) | |
498 | target->thread.TS_FPR(i) = buf[i]; | |
499 | target->thread.fp_state.fpscr = buf[32]; | |
500 | } | |
501 | return 0; | |
502 | #endif | |
503 | ||
504 | #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
c6e6771b MN |
505 | /* copy to local buffer then write that out */ |
506 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
507 | if (i) | |
508 | return i; | |
509 | for (i = 0; i < 32 ; i++) | |
510 | target->thread.TS_FPR(i) = buf[i]; | |
de79f7b9 | 511 | target->thread.fp_state.fpscr = buf[32]; |
c6e6771b | 512 | return 0; |
1ec8549d AK |
513 | #endif |
514 | ||
515 | #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
de79f7b9 | 516 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 517 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
518 | |
519 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 520 | &target->thread.fp_state, 0, -1); |
c6e6771b | 521 | #endif |
f65255e8 RM |
522 | } |
523 | ||
865418d8 BH |
524 | #ifdef CONFIG_ALTIVEC |
525 | /* | |
526 | * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. | |
527 | * The transfer totals 34 quadword. Quadwords 0-31 contain the | |
528 | * corresponding vector registers. Quadword 32 contains the vscr as the | |
529 | * last word (offset 12) within that quadword. Quadword 33 contains the | |
530 | * vrsave as the first word (offset 0) within the quadword. | |
531 | * | |
532 | * This definition of the VMX state is compatible with the current PPC32 | |
533 | * ptrace interface. This allows signal handling and ptrace to use the | |
534 | * same structures. This also simplifies the implementation of a bi-arch | |
535 | * (combined (32- and 64-bit) gdb. | |
536 | */ | |
537 | ||
3caf06c6 RM |
538 | static int vr_active(struct task_struct *target, |
539 | const struct user_regset *regset) | |
540 | { | |
541 | flush_altivec_to_thread(target); | |
542 | return target->thread.used_vr ? regset->n : 0; | |
543 | } | |
544 | ||
d844e279 AK |
545 | /* |
546 | * When the transaction is active, 'transact_vr' holds the current running | |
547 | * value of all the VMX registers and 'vr_state' holds the last checkpointed | |
548 | * value of all the VMX registers for the current transaction to fall back | |
549 | * on in case it aborts. When transaction is not active 'vr_state' holds | |
550 | * the current running state of all the VMX registers. So this function which | |
551 | * gets the current running values of all the VMX registers, needs to know | |
552 | * whether any transaction is active or not. | |
553 | * | |
554 | * Userspace interface buffer layout: | |
555 | * | |
556 | * struct data { | |
557 | * vector128 vr[32]; | |
558 | * vector128 vscr; | |
559 | * vector128 vrsave; | |
560 | * }; | |
561 | */ | |
3caf06c6 RM |
562 | static int vr_get(struct task_struct *target, const struct user_regset *regset, |
563 | unsigned int pos, unsigned int count, | |
564 | void *kbuf, void __user *ubuf) | |
565 | { | |
d844e279 | 566 | struct thread_vr_state *addr; |
3caf06c6 RM |
567 | int ret; |
568 | ||
569 | flush_altivec_to_thread(target); | |
570 | ||
de79f7b9 PM |
571 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
572 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 | 573 | |
d844e279 AK |
574 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
575 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
576 | flush_fp_to_thread(target); | |
577 | flush_tmregs_to_thread(target); | |
578 | addr = &target->thread.transact_vr; | |
579 | } else { | |
580 | addr = &target->thread.vr_state; | |
581 | } | |
582 | #else | |
583 | addr = &target->thread.vr_state; | |
584 | #endif | |
3caf06c6 | 585 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
d844e279 | 586 | addr, 0, |
3caf06c6 RM |
587 | 33 * sizeof(vector128)); |
588 | if (!ret) { | |
589 | /* | |
590 | * Copy out only the low-order word of vrsave. | |
591 | */ | |
592 | union { | |
593 | elf_vrreg_t reg; | |
594 | u32 word; | |
595 | } vrsave; | |
596 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 AK |
597 | |
598 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
599 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
600 | vrsave.word = target->thread.transact_vrsave; | |
601 | else | |
602 | vrsave.word = target->thread.vrsave; | |
603 | #else | |
3caf06c6 | 604 | vrsave.word = target->thread.vrsave; |
d844e279 AK |
605 | #endif |
606 | ||
3caf06c6 RM |
607 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, |
608 | 33 * sizeof(vector128), -1); | |
609 | } | |
610 | ||
611 | return ret; | |
612 | } | |
613 | ||
d844e279 AK |
614 | /* |
615 | * When the transaction is active, 'transact_vr' holds the current running | |
616 | * value of all the VMX registers and 'vr_state' holds the last checkpointed | |
617 | * value of all the VMX registers for the current transaction to fall back | |
618 | * on in case it aborts. When transaction is not active 'vr_state' holds | |
619 | * the current running state of all the VMX registers. So this function which | |
620 | * sets the current running values of all the VMX registers, needs to know | |
621 | * whether any transaction is active or not. | |
622 | * | |
623 | * Userspace interface buffer layout: | |
624 | * | |
625 | * struct data { | |
626 | * vector128 vr[32]; | |
627 | * vector128 vscr; | |
628 | * vector128 vrsave; | |
629 | * }; | |
630 | */ | |
3caf06c6 RM |
631 | static int vr_set(struct task_struct *target, const struct user_regset *regset, |
632 | unsigned int pos, unsigned int count, | |
633 | const void *kbuf, const void __user *ubuf) | |
634 | { | |
d844e279 | 635 | struct thread_vr_state *addr; |
3caf06c6 RM |
636 | int ret; |
637 | ||
638 | flush_altivec_to_thread(target); | |
639 | ||
de79f7b9 PM |
640 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
641 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 | 642 | |
d844e279 AK |
643 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
644 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
645 | flush_fp_to_thread(target); | |
646 | flush_tmregs_to_thread(target); | |
647 | addr = &target->thread.transact_vr; | |
648 | } else { | |
649 | addr = &target->thread.vr_state; | |
650 | } | |
651 | #else | |
652 | addr = &target->thread.vr_state; | |
653 | #endif | |
3caf06c6 | 654 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
d844e279 | 655 | addr, 0, |
de79f7b9 | 656 | 33 * sizeof(vector128)); |
3caf06c6 RM |
657 | if (!ret && count > 0) { |
658 | /* | |
659 | * We use only the first word of vrsave. | |
660 | */ | |
661 | union { | |
662 | elf_vrreg_t reg; | |
663 | u32 word; | |
664 | } vrsave; | |
665 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 AK |
666 | |
667 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
668 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
669 | vrsave.word = target->thread.transact_vrsave; | |
670 | else | |
671 | vrsave.word = target->thread.vrsave; | |
672 | #else | |
3caf06c6 | 673 | vrsave.word = target->thread.vrsave; |
d844e279 | 674 | #endif |
3caf06c6 RM |
675 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, |
676 | 33 * sizeof(vector128), -1); | |
d844e279 AK |
677 | if (!ret) { |
678 | ||
679 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
680 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
681 | target->thread.transact_vrsave = vrsave.word; | |
682 | else | |
683 | target->thread.vrsave = vrsave.word; | |
684 | #else | |
3caf06c6 | 685 | target->thread.vrsave = vrsave.word; |
d844e279 AK |
686 | #endif |
687 | } | |
3caf06c6 RM |
688 | } |
689 | ||
690 | return ret; | |
691 | } | |
865418d8 BH |
692 | #endif /* CONFIG_ALTIVEC */ |
693 | ||
ce48b210 MN |
694 | #ifdef CONFIG_VSX |
695 | /* | |
696 | * Currently to set and and get all the vsx state, you need to call | |
25985edc | 697 | * the fp and VMX calls as well. This only get/sets the lower 32 |
ce48b210 MN |
698 | * 128bit VSX registers. |
699 | */ | |
700 | ||
701 | static int vsr_active(struct task_struct *target, | |
702 | const struct user_regset *regset) | |
703 | { | |
704 | flush_vsx_to_thread(target); | |
705 | return target->thread.used_vsr ? regset->n : 0; | |
706 | } | |
707 | ||
94b7d361 AK |
708 | /* |
709 | * When the transaction is active, 'transact_fp' holds the current running | |
710 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
711 | * value of all FPR registers for the current transaction. When transaction | |
712 | * is not active 'fp_state' holds the current running state of all the FPR | |
713 | * registers. So this function which returns the current running values of | |
714 | * all the FPR registers, needs to know whether any transaction is active | |
715 | * or not. | |
716 | * | |
717 | * Userspace interface buffer layout: | |
718 | * | |
719 | * struct data { | |
720 | * u64 vsx[32]; | |
721 | * }; | |
722 | */ | |
ce48b210 MN |
723 | static int vsr_get(struct task_struct *target, const struct user_regset *regset, |
724 | unsigned int pos, unsigned int count, | |
725 | void *kbuf, void __user *ubuf) | |
726 | { | |
de79f7b9 | 727 | u64 buf[32]; |
f3e909c2 | 728 | int ret, i; |
ce48b210 | 729 | |
94b7d361 AK |
730 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
731 | flush_fp_to_thread(target); | |
732 | flush_altivec_to_thread(target); | |
733 | flush_tmregs_to_thread(target); | |
734 | #endif | |
ce48b210 MN |
735 | flush_vsx_to_thread(target); |
736 | ||
94b7d361 AK |
737 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
738 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
739 | for (i = 0; i < 32 ; i++) | |
740 | buf[i] = target->thread. | |
741 | transact_fp.fpr[i][TS_VSRLOWOFFSET]; | |
742 | } else { | |
743 | for (i = 0; i < 32 ; i++) | |
744 | buf[i] = target->thread. | |
745 | fp_state.fpr[i][TS_VSRLOWOFFSET]; | |
746 | } | |
747 | #else | |
f3e909c2 | 748 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 749 | buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET]; |
94b7d361 | 750 | #endif |
ce48b210 | 751 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
f3e909c2 | 752 | buf, 0, 32 * sizeof(double)); |
ce48b210 MN |
753 | |
754 | return ret; | |
755 | } | |
756 | ||
94b7d361 AK |
757 | /* |
758 | * When the transaction is active, 'transact_fp' holds the current running | |
759 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
760 | * value of all FPR registers for the current transaction. When transaction | |
761 | * is not active 'fp_state' holds the current running state of all the FPR | |
762 | * registers. So this function which sets the current running values of all | |
763 | * the FPR registers, needs to know whether any transaction is active or not. | |
764 | * | |
765 | * Userspace interface buffer layout: | |
766 | * | |
767 | * struct data { | |
768 | * u64 vsx[32]; | |
769 | * }; | |
770 | */ | |
ce48b210 MN |
771 | static int vsr_set(struct task_struct *target, const struct user_regset *regset, |
772 | unsigned int pos, unsigned int count, | |
773 | const void *kbuf, const void __user *ubuf) | |
774 | { | |
de79f7b9 | 775 | u64 buf[32]; |
f3e909c2 | 776 | int ret,i; |
ce48b210 | 777 | |
94b7d361 AK |
778 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
779 | flush_fp_to_thread(target); | |
780 | flush_altivec_to_thread(target); | |
781 | flush_tmregs_to_thread(target); | |
782 | #endif | |
ce48b210 MN |
783 | flush_vsx_to_thread(target); |
784 | ||
785 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
f3e909c2 | 786 | buf, 0, 32 * sizeof(double)); |
94b7d361 AK |
787 | |
788 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
789 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
790 | for (i = 0; i < 32 ; i++) | |
791 | target->thread.transact_fp. | |
792 | fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
793 | } else { | |
794 | for (i = 0; i < 32 ; i++) | |
795 | target->thread.fp_state. | |
796 | fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
797 | } | |
798 | #else | |
f3e909c2 | 799 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 800 | target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i]; |
94b7d361 | 801 | #endif |
f3e909c2 | 802 | |
ce48b210 MN |
803 | |
804 | return ret; | |
805 | } | |
806 | #endif /* CONFIG_VSX */ | |
807 | ||
865418d8 BH |
808 | #ifdef CONFIG_SPE |
809 | ||
810 | /* | |
811 | * For get_evrregs/set_evrregs functions 'data' has the following layout: | |
812 | * | |
813 | * struct { | |
814 | * u32 evr[32]; | |
815 | * u64 acc; | |
816 | * u32 spefscr; | |
817 | * } | |
818 | */ | |
819 | ||
a4e4b175 RM |
820 | static int evr_active(struct task_struct *target, |
821 | const struct user_regset *regset) | |
865418d8 | 822 | { |
a4e4b175 RM |
823 | flush_spe_to_thread(target); |
824 | return target->thread.used_spe ? regset->n : 0; | |
825 | } | |
865418d8 | 826 | |
a4e4b175 RM |
827 | static int evr_get(struct task_struct *target, const struct user_regset *regset, |
828 | unsigned int pos, unsigned int count, | |
829 | void *kbuf, void __user *ubuf) | |
830 | { | |
831 | int ret; | |
865418d8 | 832 | |
a4e4b175 | 833 | flush_spe_to_thread(target); |
865418d8 | 834 | |
a4e4b175 RM |
835 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
836 | &target->thread.evr, | |
837 | 0, sizeof(target->thread.evr)); | |
865418d8 | 838 | |
a4e4b175 RM |
839 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
840 | offsetof(struct thread_struct, spefscr)); | |
841 | ||
842 | if (!ret) | |
843 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
844 | &target->thread.acc, | |
845 | sizeof(target->thread.evr), -1); | |
846 | ||
847 | return ret; | |
848 | } | |
849 | ||
850 | static int evr_set(struct task_struct *target, const struct user_regset *regset, | |
851 | unsigned int pos, unsigned int count, | |
852 | const void *kbuf, const void __user *ubuf) | |
853 | { | |
854 | int ret; | |
855 | ||
856 | flush_spe_to_thread(target); | |
857 | ||
858 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
859 | &target->thread.evr, | |
860 | 0, sizeof(target->thread.evr)); | |
865418d8 | 861 | |
a4e4b175 RM |
862 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
863 | offsetof(struct thread_struct, spefscr)); | |
864 | ||
865 | if (!ret) | |
866 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
867 | &target->thread.acc, | |
868 | sizeof(target->thread.evr), -1); | |
869 | ||
870 | return ret; | |
865418d8 | 871 | } |
865418d8 BH |
872 | #endif /* CONFIG_SPE */ |
873 | ||
25847fb1 AK |
874 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
875 | /** | |
876 | * tm_cgpr_active - get active number of registers in CGPR | |
877 | * @target: The target task. | |
878 | * @regset: The user regset structure. | |
879 | * | |
880 | * This function checks for the active number of available | |
881 | * regisers in transaction checkpointed GPR category. | |
882 | */ | |
883 | static int tm_cgpr_active(struct task_struct *target, | |
884 | const struct user_regset *regset) | |
885 | { | |
886 | if (!cpu_has_feature(CPU_FTR_TM)) | |
887 | return -ENODEV; | |
888 | ||
889 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
890 | return 0; | |
891 | ||
892 | return regset->n; | |
893 | } | |
894 | ||
895 | /** | |
896 | * tm_cgpr_get - get CGPR registers | |
897 | * @target: The target task. | |
898 | * @regset: The user regset structure. | |
899 | * @pos: The buffer position. | |
900 | * @count: Number of bytes to copy. | |
901 | * @kbuf: Kernel buffer to copy from. | |
902 | * @ubuf: User buffer to copy into. | |
903 | * | |
904 | * This function gets transaction checkpointed GPR registers. | |
905 | * | |
906 | * When the transaction is active, 'ckpt_regs' holds all the checkpointed | |
907 | * GPR register values for the current transaction to fall back on if it | |
908 | * aborts in between. This function gets those checkpointed GPR registers. | |
909 | * The userspace interface buffer layout is as follows. | |
910 | * | |
911 | * struct data { | |
912 | * struct pt_regs ckpt_regs; | |
913 | * }; | |
914 | */ | |
915 | static int tm_cgpr_get(struct task_struct *target, | |
916 | const struct user_regset *regset, | |
917 | unsigned int pos, unsigned int count, | |
918 | void *kbuf, void __user *ubuf) | |
919 | { | |
920 | int ret; | |
921 | ||
922 | if (!cpu_has_feature(CPU_FTR_TM)) | |
923 | return -ENODEV; | |
924 | ||
925 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
926 | return -ENODATA; | |
927 | ||
928 | flush_fp_to_thread(target); | |
929 | flush_altivec_to_thread(target); | |
930 | flush_tmregs_to_thread(target); | |
931 | ||
932 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
933 | &target->thread.ckpt_regs, | |
934 | 0, offsetof(struct pt_regs, msr)); | |
935 | if (!ret) { | |
936 | unsigned long msr = get_user_ckpt_msr(target); | |
937 | ||
938 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
939 | offsetof(struct pt_regs, msr), | |
940 | offsetof(struct pt_regs, msr) + | |
941 | sizeof(msr)); | |
942 | } | |
943 | ||
944 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
945 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
946 | ||
947 | if (!ret) | |
948 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
949 | &target->thread.ckpt_regs.orig_gpr3, | |
950 | offsetof(struct pt_regs, orig_gpr3), | |
951 | sizeof(struct pt_regs)); | |
952 | if (!ret) | |
953 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
954 | sizeof(struct pt_regs), -1); | |
955 | ||
956 | return ret; | |
957 | } | |
958 | ||
959 | /* | |
960 | * tm_cgpr_set - set the CGPR registers | |
961 | * @target: The target task. | |
962 | * @regset: The user regset structure. | |
963 | * @pos: The buffer position. | |
964 | * @count: Number of bytes to copy. | |
965 | * @kbuf: Kernel buffer to copy into. | |
966 | * @ubuf: User buffer to copy from. | |
967 | * | |
968 | * This function sets in transaction checkpointed GPR registers. | |
969 | * | |
970 | * When the transaction is active, 'ckpt_regs' holds the checkpointed | |
971 | * GPR register values for the current transaction to fall back on if it | |
972 | * aborts in between. This function sets those checkpointed GPR registers. | |
973 | * The userspace interface buffer layout is as follows. | |
974 | * | |
975 | * struct data { | |
976 | * struct pt_regs ckpt_regs; | |
977 | * }; | |
978 | */ | |
979 | static int tm_cgpr_set(struct task_struct *target, | |
980 | const struct user_regset *regset, | |
981 | unsigned int pos, unsigned int count, | |
982 | const void *kbuf, const void __user *ubuf) | |
983 | { | |
984 | unsigned long reg; | |
985 | int ret; | |
986 | ||
987 | if (!cpu_has_feature(CPU_FTR_TM)) | |
988 | return -ENODEV; | |
989 | ||
990 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
991 | return -ENODATA; | |
992 | ||
993 | flush_fp_to_thread(target); | |
994 | flush_altivec_to_thread(target); | |
995 | flush_tmregs_to_thread(target); | |
996 | ||
997 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
998 | &target->thread.ckpt_regs, | |
999 | 0, PT_MSR * sizeof(reg)); | |
1000 | ||
1001 | if (!ret && count > 0) { | |
1002 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
1003 | PT_MSR * sizeof(reg), | |
1004 | (PT_MSR + 1) * sizeof(reg)); | |
1005 | if (!ret) | |
1006 | ret = set_user_ckpt_msr(target, reg); | |
1007 | } | |
1008 | ||
1009 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
1010 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
1011 | ||
1012 | if (!ret) | |
1013 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1014 | &target->thread.ckpt_regs.orig_gpr3, | |
1015 | PT_ORIG_R3 * sizeof(reg), | |
1016 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
1017 | ||
1018 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
1019 | ret = user_regset_copyin_ignore( | |
1020 | &pos, &count, &kbuf, &ubuf, | |
1021 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
1022 | PT_TRAP * sizeof(reg)); | |
1023 | ||
1024 | if (!ret && count > 0) { | |
1025 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
1026 | PT_TRAP * sizeof(reg), | |
1027 | (PT_TRAP + 1) * sizeof(reg)); | |
1028 | if (!ret) | |
1029 | ret = set_user_ckpt_trap(target, reg); | |
1030 | } | |
1031 | ||
1032 | if (!ret) | |
1033 | ret = user_regset_copyin_ignore( | |
1034 | &pos, &count, &kbuf, &ubuf, | |
1035 | (PT_TRAP + 1) * sizeof(reg), -1); | |
1036 | ||
1037 | return ret; | |
1038 | } | |
19cbcbf7 AK |
1039 | |
1040 | /** | |
1041 | * tm_cfpr_active - get active number of registers in CFPR | |
1042 | * @target: The target task. | |
1043 | * @regset: The user regset structure. | |
1044 | * | |
1045 | * This function checks for the active number of available | |
1046 | * regisers in transaction checkpointed FPR category. | |
1047 | */ | |
1048 | static int tm_cfpr_active(struct task_struct *target, | |
1049 | const struct user_regset *regset) | |
1050 | { | |
1051 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1052 | return -ENODEV; | |
1053 | ||
1054 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1055 | return 0; | |
1056 | ||
1057 | return regset->n; | |
1058 | } | |
1059 | ||
1060 | /** | |
1061 | * tm_cfpr_get - get CFPR registers | |
1062 | * @target: The target task. | |
1063 | * @regset: The user regset structure. | |
1064 | * @pos: The buffer position. | |
1065 | * @count: Number of bytes to copy. | |
1066 | * @kbuf: Kernel buffer to copy from. | |
1067 | * @ubuf: User buffer to copy into. | |
1068 | * | |
1069 | * This function gets in transaction checkpointed FPR registers. | |
1070 | * | |
1071 | * When the transaction is active 'fp_state' holds the checkpointed | |
1072 | * values for the current transaction to fall back on if it aborts | |
1073 | * in between. This function gets those checkpointed FPR registers. | |
1074 | * The userspace interface buffer layout is as follows. | |
1075 | * | |
1076 | * struct data { | |
1077 | * u64 fpr[32]; | |
1078 | * u64 fpscr; | |
1079 | *}; | |
1080 | */ | |
1081 | static int tm_cfpr_get(struct task_struct *target, | |
1082 | const struct user_regset *regset, | |
1083 | unsigned int pos, unsigned int count, | |
1084 | void *kbuf, void __user *ubuf) | |
1085 | { | |
1086 | u64 buf[33]; | |
1087 | int i; | |
1088 | ||
1089 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1090 | return -ENODEV; | |
1091 | ||
1092 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1093 | return -ENODATA; | |
1094 | ||
1095 | flush_fp_to_thread(target); | |
1096 | flush_altivec_to_thread(target); | |
1097 | flush_tmregs_to_thread(target); | |
1098 | ||
1099 | /* copy to local buffer then write that out */ | |
1100 | for (i = 0; i < 32 ; i++) | |
1101 | buf[i] = target->thread.TS_FPR(i); | |
1102 | buf[32] = target->thread.fp_state.fpscr; | |
1103 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
1104 | } | |
1105 | ||
1106 | /** | |
1107 | * tm_cfpr_set - set CFPR registers | |
1108 | * @target: The target task. | |
1109 | * @regset: The user regset structure. | |
1110 | * @pos: The buffer position. | |
1111 | * @count: Number of bytes to copy. | |
1112 | * @kbuf: Kernel buffer to copy into. | |
1113 | * @ubuf: User buffer to copy from. | |
1114 | * | |
1115 | * This function sets in transaction checkpointed FPR registers. | |
1116 | * | |
1117 | * When the transaction is active 'fp_state' holds the checkpointed | |
1118 | * FPR register values for the current transaction to fall back on | |
1119 | * if it aborts in between. This function sets these checkpointed | |
1120 | * FPR registers. The userspace interface buffer layout is as follows. | |
1121 | * | |
1122 | * struct data { | |
1123 | * u64 fpr[32]; | |
1124 | * u64 fpscr; | |
1125 | *}; | |
1126 | */ | |
1127 | static int tm_cfpr_set(struct task_struct *target, | |
1128 | const struct user_regset *regset, | |
1129 | unsigned int pos, unsigned int count, | |
1130 | const void *kbuf, const void __user *ubuf) | |
1131 | { | |
1132 | u64 buf[33]; | |
1133 | int i; | |
1134 | ||
1135 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1136 | return -ENODEV; | |
1137 | ||
1138 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1139 | return -ENODATA; | |
1140 | ||
1141 | flush_fp_to_thread(target); | |
1142 | flush_altivec_to_thread(target); | |
1143 | flush_tmregs_to_thread(target); | |
1144 | ||
1145 | /* copy to local buffer then write that out */ | |
1146 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
1147 | if (i) | |
1148 | return i; | |
1149 | for (i = 0; i < 32 ; i++) | |
1150 | target->thread.TS_FPR(i) = buf[i]; | |
1151 | target->thread.fp_state.fpscr = buf[32]; | |
1152 | return 0; | |
1153 | } | |
8c13f599 AK |
1154 | |
1155 | /** | |
1156 | * tm_cvmx_active - get active number of registers in CVMX | |
1157 | * @target: The target task. | |
1158 | * @regset: The user regset structure. | |
1159 | * | |
1160 | * This function checks for the active number of available | |
1161 | * regisers in checkpointed VMX category. | |
1162 | */ | |
1163 | static int tm_cvmx_active(struct task_struct *target, | |
1164 | const struct user_regset *regset) | |
1165 | { | |
1166 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1167 | return -ENODEV; | |
1168 | ||
1169 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1170 | return 0; | |
1171 | ||
1172 | return regset->n; | |
1173 | } | |
1174 | ||
1175 | /** | |
1176 | * tm_cvmx_get - get CMVX registers | |
1177 | * @target: The target task. | |
1178 | * @regset: The user regset structure. | |
1179 | * @pos: The buffer position. | |
1180 | * @count: Number of bytes to copy. | |
1181 | * @kbuf: Kernel buffer to copy from. | |
1182 | * @ubuf: User buffer to copy into. | |
1183 | * | |
1184 | * This function gets in transaction checkpointed VMX registers. | |
1185 | * | |
1186 | * When the transaction is active 'vr_state' and 'vr_save' hold | |
1187 | * the checkpointed values for the current transaction to fall | |
1188 | * back on if it aborts in between. The userspace interface buffer | |
1189 | * layout is as follows. | |
1190 | * | |
1191 | * struct data { | |
1192 | * vector128 vr[32]; | |
1193 | * vector128 vscr; | |
1194 | * vector128 vrsave; | |
1195 | *}; | |
1196 | */ | |
1197 | static int tm_cvmx_get(struct task_struct *target, | |
1198 | const struct user_regset *regset, | |
1199 | unsigned int pos, unsigned int count, | |
1200 | void *kbuf, void __user *ubuf) | |
1201 | { | |
1202 | int ret; | |
1203 | ||
1204 | BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32])); | |
1205 | ||
1206 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1207 | return -ENODEV; | |
1208 | ||
1209 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1210 | return -ENODATA; | |
1211 | ||
1212 | /* Flush the state */ | |
1213 | flush_fp_to_thread(target); | |
1214 | flush_altivec_to_thread(target); | |
1215 | flush_tmregs_to_thread(target); | |
1216 | ||
1217 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1218 | &target->thread.vr_state, 0, | |
1219 | 33 * sizeof(vector128)); | |
1220 | if (!ret) { | |
1221 | /* | |
1222 | * Copy out only the low-order word of vrsave. | |
1223 | */ | |
1224 | union { | |
1225 | elf_vrreg_t reg; | |
1226 | u32 word; | |
1227 | } vrsave; | |
1228 | memset(&vrsave, 0, sizeof(vrsave)); | |
1229 | vrsave.word = target->thread.vrsave; | |
1230 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, | |
1231 | 33 * sizeof(vector128), -1); | |
1232 | } | |
1233 | ||
1234 | return ret; | |
1235 | } | |
1236 | ||
1237 | /** | |
1238 | * tm_cvmx_set - set CMVX registers | |
1239 | * @target: The target task. | |
1240 | * @regset: The user regset structure. | |
1241 | * @pos: The buffer position. | |
1242 | * @count: Number of bytes to copy. | |
1243 | * @kbuf: Kernel buffer to copy into. | |
1244 | * @ubuf: User buffer to copy from. | |
1245 | * | |
1246 | * This function sets in transaction checkpointed VMX registers. | |
1247 | * | |
1248 | * When the transaction is active 'vr_state' and 'vr_save' hold | |
1249 | * the checkpointed values for the current transaction to fall | |
1250 | * back on if it aborts in between. The userspace interface buffer | |
1251 | * layout is as follows. | |
1252 | * | |
1253 | * struct data { | |
1254 | * vector128 vr[32]; | |
1255 | * vector128 vscr; | |
1256 | * vector128 vrsave; | |
1257 | *}; | |
1258 | */ | |
1259 | static int tm_cvmx_set(struct task_struct *target, | |
1260 | const struct user_regset *regset, | |
1261 | unsigned int pos, unsigned int count, | |
1262 | const void *kbuf, const void __user *ubuf) | |
1263 | { | |
1264 | int ret; | |
1265 | ||
1266 | BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32])); | |
1267 | ||
1268 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1269 | return -ENODEV; | |
1270 | ||
1271 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1272 | return -ENODATA; | |
1273 | ||
1274 | flush_fp_to_thread(target); | |
1275 | flush_altivec_to_thread(target); | |
1276 | flush_tmregs_to_thread(target); | |
1277 | ||
1278 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1279 | &target->thread.vr_state, 0, | |
1280 | 33 * sizeof(vector128)); | |
1281 | if (!ret && count > 0) { | |
1282 | /* | |
1283 | * We use only the low-order word of vrsave. | |
1284 | */ | |
1285 | union { | |
1286 | elf_vrreg_t reg; | |
1287 | u32 word; | |
1288 | } vrsave; | |
1289 | memset(&vrsave, 0, sizeof(vrsave)); | |
1290 | vrsave.word = target->thread.vrsave; | |
1291 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, | |
1292 | 33 * sizeof(vector128), -1); | |
1293 | if (!ret) | |
1294 | target->thread.vrsave = vrsave.word; | |
1295 | } | |
1296 | ||
1297 | return ret; | |
1298 | } | |
9d3918f7 AK |
1299 | |
1300 | /** | |
1301 | * tm_cvsx_active - get active number of registers in CVSX | |
1302 | * @target: The target task. | |
1303 | * @regset: The user regset structure. | |
1304 | * | |
1305 | * This function checks for the active number of available | |
1306 | * regisers in transaction checkpointed VSX category. | |
1307 | */ | |
1308 | static int tm_cvsx_active(struct task_struct *target, | |
1309 | const struct user_regset *regset) | |
1310 | { | |
1311 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1312 | return -ENODEV; | |
1313 | ||
1314 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1315 | return 0; | |
1316 | ||
1317 | flush_vsx_to_thread(target); | |
1318 | return target->thread.used_vsr ? regset->n : 0; | |
1319 | } | |
1320 | ||
1321 | /** | |
1322 | * tm_cvsx_get - get CVSX registers | |
1323 | * @target: The target task. | |
1324 | * @regset: The user regset structure. | |
1325 | * @pos: The buffer position. | |
1326 | * @count: Number of bytes to copy. | |
1327 | * @kbuf: Kernel buffer to copy from. | |
1328 | * @ubuf: User buffer to copy into. | |
1329 | * | |
1330 | * This function gets in transaction checkpointed VSX registers. | |
1331 | * | |
1332 | * When the transaction is active 'fp_state' holds the checkpointed | |
1333 | * values for the current transaction to fall back on if it aborts | |
1334 | * in between. This function gets those checkpointed VSX registers. | |
1335 | * The userspace interface buffer layout is as follows. | |
1336 | * | |
1337 | * struct data { | |
1338 | * u64 vsx[32]; | |
1339 | *}; | |
1340 | */ | |
1341 | static int tm_cvsx_get(struct task_struct *target, | |
1342 | const struct user_regset *regset, | |
1343 | unsigned int pos, unsigned int count, | |
1344 | void *kbuf, void __user *ubuf) | |
1345 | { | |
1346 | u64 buf[32]; | |
1347 | int ret, i; | |
1348 | ||
1349 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1350 | return -ENODEV; | |
1351 | ||
1352 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1353 | return -ENODATA; | |
1354 | ||
1355 | /* Flush the state */ | |
1356 | flush_fp_to_thread(target); | |
1357 | flush_altivec_to_thread(target); | |
1358 | flush_tmregs_to_thread(target); | |
1359 | flush_vsx_to_thread(target); | |
1360 | ||
1361 | for (i = 0; i < 32 ; i++) | |
1362 | buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET]; | |
1363 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1364 | buf, 0, 32 * sizeof(double)); | |
1365 | ||
1366 | return ret; | |
1367 | } | |
1368 | ||
1369 | /** | |
1370 | * tm_cvsx_set - set CFPR registers | |
1371 | * @target: The target task. | |
1372 | * @regset: The user regset structure. | |
1373 | * @pos: The buffer position. | |
1374 | * @count: Number of bytes to copy. | |
1375 | * @kbuf: Kernel buffer to copy into. | |
1376 | * @ubuf: User buffer to copy from. | |
1377 | * | |
1378 | * This function sets in transaction checkpointed VSX registers. | |
1379 | * | |
1380 | * When the transaction is active 'fp_state' holds the checkpointed | |
1381 | * VSX register values for the current transaction to fall back on | |
1382 | * if it aborts in between. This function sets these checkpointed | |
1383 | * FPR registers. The userspace interface buffer layout is as follows. | |
1384 | * | |
1385 | * struct data { | |
1386 | * u64 vsx[32]; | |
1387 | *}; | |
1388 | */ | |
1389 | static int tm_cvsx_set(struct task_struct *target, | |
1390 | const struct user_regset *regset, | |
1391 | unsigned int pos, unsigned int count, | |
1392 | const void *kbuf, const void __user *ubuf) | |
1393 | { | |
1394 | u64 buf[32]; | |
1395 | int ret, i; | |
1396 | ||
1397 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1398 | return -ENODEV; | |
1399 | ||
1400 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1401 | return -ENODATA; | |
1402 | ||
1403 | /* Flush the state */ | |
1404 | flush_fp_to_thread(target); | |
1405 | flush_altivec_to_thread(target); | |
1406 | flush_tmregs_to_thread(target); | |
1407 | flush_vsx_to_thread(target); | |
1408 | ||
1409 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1410 | buf, 0, 32 * sizeof(double)); | |
1411 | for (i = 0; i < 32 ; i++) | |
1412 | target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
1413 | ||
1414 | return ret; | |
1415 | } | |
08e1c01d AK |
1416 | |
1417 | /** | |
1418 | * tm_spr_active - get active number of registers in TM SPR | |
1419 | * @target: The target task. | |
1420 | * @regset: The user regset structure. | |
1421 | * | |
1422 | * This function checks the active number of available | |
1423 | * regisers in the transactional memory SPR category. | |
1424 | */ | |
1425 | static int tm_spr_active(struct task_struct *target, | |
1426 | const struct user_regset *regset) | |
1427 | { | |
1428 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1429 | return -ENODEV; | |
1430 | ||
1431 | return regset->n; | |
1432 | } | |
1433 | ||
1434 | /** | |
1435 | * tm_spr_get - get the TM related SPR registers | |
1436 | * @target: The target task. | |
1437 | * @regset: The user regset structure. | |
1438 | * @pos: The buffer position. | |
1439 | * @count: Number of bytes to copy. | |
1440 | * @kbuf: Kernel buffer to copy from. | |
1441 | * @ubuf: User buffer to copy into. | |
1442 | * | |
1443 | * This function gets transactional memory related SPR registers. | |
1444 | * The userspace interface buffer layout is as follows. | |
1445 | * | |
1446 | * struct { | |
1447 | * u64 tm_tfhar; | |
1448 | * u64 tm_texasr; | |
1449 | * u64 tm_tfiar; | |
1450 | * }; | |
1451 | */ | |
1452 | static int tm_spr_get(struct task_struct *target, | |
1453 | const struct user_regset *regset, | |
1454 | unsigned int pos, unsigned int count, | |
1455 | void *kbuf, void __user *ubuf) | |
1456 | { | |
1457 | int ret; | |
1458 | ||
1459 | /* Build tests */ | |
1460 | BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr)); | |
1461 | BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar)); | |
1462 | BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs)); | |
1463 | ||
1464 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1465 | return -ENODEV; | |
1466 | ||
1467 | /* Flush the states */ | |
1468 | flush_fp_to_thread(target); | |
1469 | flush_altivec_to_thread(target); | |
1470 | flush_tmregs_to_thread(target); | |
1471 | ||
1472 | /* TFHAR register */ | |
1473 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1474 | &target->thread.tm_tfhar, 0, sizeof(u64)); | |
1475 | ||
1476 | /* TEXASR register */ | |
1477 | if (!ret) | |
1478 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1479 | &target->thread.tm_texasr, sizeof(u64), | |
1480 | 2 * sizeof(u64)); | |
1481 | ||
1482 | /* TFIAR register */ | |
1483 | if (!ret) | |
1484 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1485 | &target->thread.tm_tfiar, | |
1486 | 2 * sizeof(u64), 3 * sizeof(u64)); | |
1487 | return ret; | |
1488 | } | |
1489 | ||
1490 | /** | |
1491 | * tm_spr_set - set the TM related SPR registers | |
1492 | * @target: The target task. | |
1493 | * @regset: The user regset structure. | |
1494 | * @pos: The buffer position. | |
1495 | * @count: Number of bytes to copy. | |
1496 | * @kbuf: Kernel buffer to copy into. | |
1497 | * @ubuf: User buffer to copy from. | |
1498 | * | |
1499 | * This function sets transactional memory related SPR registers. | |
1500 | * The userspace interface buffer layout is as follows. | |
1501 | * | |
1502 | * struct { | |
1503 | * u64 tm_tfhar; | |
1504 | * u64 tm_texasr; | |
1505 | * u64 tm_tfiar; | |
1506 | * }; | |
1507 | */ | |
1508 | static int tm_spr_set(struct task_struct *target, | |
1509 | const struct user_regset *regset, | |
1510 | unsigned int pos, unsigned int count, | |
1511 | const void *kbuf, const void __user *ubuf) | |
1512 | { | |
1513 | int ret; | |
1514 | ||
1515 | /* Build tests */ | |
1516 | BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr)); | |
1517 | BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar)); | |
1518 | BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs)); | |
1519 | ||
1520 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1521 | return -ENODEV; | |
1522 | ||
1523 | /* Flush the states */ | |
1524 | flush_fp_to_thread(target); | |
1525 | flush_altivec_to_thread(target); | |
1526 | flush_tmregs_to_thread(target); | |
1527 | ||
1528 | /* TFHAR register */ | |
1529 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1530 | &target->thread.tm_tfhar, 0, sizeof(u64)); | |
1531 | ||
1532 | /* TEXASR register */ | |
1533 | if (!ret) | |
1534 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1535 | &target->thread.tm_texasr, sizeof(u64), | |
1536 | 2 * sizeof(u64)); | |
1537 | ||
1538 | /* TFIAR register */ | |
1539 | if (!ret) | |
1540 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1541 | &target->thread.tm_tfiar, | |
1542 | 2 * sizeof(u64), 3 * sizeof(u64)); | |
1543 | return ret; | |
1544 | } | |
c45dc900 AK |
1545 | |
1546 | static int tm_tar_active(struct task_struct *target, | |
1547 | const struct user_regset *regset) | |
1548 | { | |
1549 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1550 | return -ENODEV; | |
1551 | ||
1552 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1553 | return regset->n; | |
1554 | ||
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | static int tm_tar_get(struct task_struct *target, | |
1559 | const struct user_regset *regset, | |
1560 | unsigned int pos, unsigned int count, | |
1561 | void *kbuf, void __user *ubuf) | |
1562 | { | |
1563 | int ret; | |
1564 | ||
1565 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1566 | return -ENODEV; | |
1567 | ||
1568 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1569 | return -ENODATA; | |
1570 | ||
1571 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1572 | &target->thread.tm_tar, 0, sizeof(u64)); | |
1573 | return ret; | |
1574 | } | |
1575 | ||
1576 | static int tm_tar_set(struct task_struct *target, | |
1577 | const struct user_regset *regset, | |
1578 | unsigned int pos, unsigned int count, | |
1579 | const void *kbuf, const void __user *ubuf) | |
1580 | { | |
1581 | int ret; | |
1582 | ||
1583 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1584 | return -ENODEV; | |
1585 | ||
1586 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1587 | return -ENODATA; | |
1588 | ||
1589 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1590 | &target->thread.tm_tar, 0, sizeof(u64)); | |
1591 | return ret; | |
1592 | } | |
1593 | ||
1594 | static int tm_ppr_active(struct task_struct *target, | |
1595 | const struct user_regset *regset) | |
1596 | { | |
1597 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1598 | return -ENODEV; | |
1599 | ||
1600 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1601 | return regset->n; | |
1602 | ||
1603 | return 0; | |
1604 | } | |
1605 | ||
1606 | ||
1607 | static int tm_ppr_get(struct task_struct *target, | |
1608 | const struct user_regset *regset, | |
1609 | unsigned int pos, unsigned int count, | |
1610 | void *kbuf, void __user *ubuf) | |
1611 | { | |
1612 | int ret; | |
1613 | ||
1614 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1615 | return -ENODEV; | |
1616 | ||
1617 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1618 | return -ENODATA; | |
1619 | ||
1620 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1621 | &target->thread.tm_ppr, 0, sizeof(u64)); | |
1622 | return ret; | |
1623 | } | |
1624 | ||
1625 | static int tm_ppr_set(struct task_struct *target, | |
1626 | const struct user_regset *regset, | |
1627 | unsigned int pos, unsigned int count, | |
1628 | const void *kbuf, const void __user *ubuf) | |
1629 | { | |
1630 | int ret; | |
1631 | ||
1632 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1633 | return -ENODEV; | |
1634 | ||
1635 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1636 | return -ENODATA; | |
1637 | ||
1638 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1639 | &target->thread.tm_ppr, 0, sizeof(u64)); | |
1640 | return ret; | |
1641 | } | |
1642 | ||
1643 | static int tm_dscr_active(struct task_struct *target, | |
1644 | const struct user_regset *regset) | |
1645 | { | |
1646 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1647 | return -ENODEV; | |
1648 | ||
1649 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1650 | return regset->n; | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
1655 | static int tm_dscr_get(struct task_struct *target, | |
1656 | const struct user_regset *regset, | |
1657 | unsigned int pos, unsigned int count, | |
1658 | void *kbuf, void __user *ubuf) | |
1659 | { | |
1660 | int ret; | |
1661 | ||
1662 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1663 | return -ENODEV; | |
1664 | ||
1665 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1666 | return -ENODATA; | |
1667 | ||
1668 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1669 | &target->thread.tm_dscr, 0, sizeof(u64)); | |
1670 | return ret; | |
1671 | } | |
1672 | ||
1673 | static int tm_dscr_set(struct task_struct *target, | |
1674 | const struct user_regset *regset, | |
1675 | unsigned int pos, unsigned int count, | |
1676 | const void *kbuf, const void __user *ubuf) | |
1677 | { | |
1678 | int ret; | |
1679 | ||
1680 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1681 | return -ENODEV; | |
1682 | ||
1683 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1684 | return -ENODATA; | |
1685 | ||
1686 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1687 | &target->thread.tm_dscr, 0, sizeof(u64)); | |
1688 | return ret; | |
1689 | } | |
08e1c01d | 1690 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
865418d8 | 1691 | |
fa439810 AK |
1692 | #ifdef CONFIG_PPC64 |
1693 | static int ppr_get(struct task_struct *target, | |
1694 | const struct user_regset *regset, | |
1695 | unsigned int pos, unsigned int count, | |
1696 | void *kbuf, void __user *ubuf) | |
1697 | { | |
1698 | int ret; | |
1699 | ||
1700 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1701 | &target->thread.ppr, 0, sizeof(u64)); | |
1702 | return ret; | |
1703 | } | |
1704 | ||
1705 | static int ppr_set(struct task_struct *target, | |
1706 | const struct user_regset *regset, | |
1707 | unsigned int pos, unsigned int count, | |
1708 | const void *kbuf, const void __user *ubuf) | |
1709 | { | |
1710 | int ret; | |
1711 | ||
1712 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1713 | &target->thread.ppr, 0, sizeof(u64)); | |
1714 | return ret; | |
1715 | } | |
1716 | ||
1717 | static int dscr_get(struct task_struct *target, | |
1718 | const struct user_regset *regset, | |
1719 | unsigned int pos, unsigned int count, | |
1720 | void *kbuf, void __user *ubuf) | |
1721 | { | |
1722 | int ret; | |
1723 | ||
1724 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1725 | &target->thread.dscr, 0, sizeof(u64)); | |
1726 | return ret; | |
1727 | } | |
1728 | static int dscr_set(struct task_struct *target, | |
1729 | const struct user_regset *regset, | |
1730 | unsigned int pos, unsigned int count, | |
1731 | const void *kbuf, const void __user *ubuf) | |
1732 | { | |
1733 | int ret; | |
1734 | ||
1735 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1736 | &target->thread.dscr, 0, sizeof(u64)); | |
1737 | return ret; | |
1738 | } | |
1739 | #endif | |
1740 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1741 | static int tar_get(struct task_struct *target, | |
1742 | const struct user_regset *regset, | |
1743 | unsigned int pos, unsigned int count, | |
1744 | void *kbuf, void __user *ubuf) | |
1745 | { | |
1746 | int ret; | |
1747 | ||
1748 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1749 | &target->thread.tar, 0, sizeof(u64)); | |
1750 | return ret; | |
1751 | } | |
1752 | static int tar_set(struct task_struct *target, | |
1753 | const struct user_regset *regset, | |
1754 | unsigned int pos, unsigned int count, | |
1755 | const void *kbuf, const void __user *ubuf) | |
1756 | { | |
1757 | int ret; | |
1758 | ||
1759 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1760 | &target->thread.tar, 0, sizeof(u64)); | |
1761 | return ret; | |
1762 | } | |
cf89d4e1 AK |
1763 | |
1764 | static int ebb_active(struct task_struct *target, | |
1765 | const struct user_regset *regset) | |
1766 | { | |
1767 | if (!cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1768 | return -ENODEV; | |
1769 | ||
1770 | if (target->thread.used_ebb) | |
1771 | return regset->n; | |
1772 | ||
1773 | return 0; | |
1774 | } | |
1775 | ||
1776 | static int ebb_get(struct task_struct *target, | |
1777 | const struct user_regset *regset, | |
1778 | unsigned int pos, unsigned int count, | |
1779 | void *kbuf, void __user *ubuf) | |
1780 | { | |
1781 | /* Build tests */ | |
1782 | BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr)); | |
1783 | BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr)); | |
1784 | ||
1785 | if (!cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1786 | return -ENODEV; | |
1787 | ||
1788 | if (!target->thread.used_ebb) | |
1789 | return -ENODATA; | |
1790 | ||
1791 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1792 | &target->thread.ebbrr, 0, 3 * sizeof(unsigned long)); | |
1793 | } | |
1794 | ||
1795 | static int ebb_set(struct task_struct *target, | |
1796 | const struct user_regset *regset, | |
1797 | unsigned int pos, unsigned int count, | |
1798 | const void *kbuf, const void __user *ubuf) | |
1799 | { | |
1800 | int ret = 0; | |
1801 | ||
1802 | /* Build tests */ | |
1803 | BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr)); | |
1804 | BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr)); | |
1805 | ||
1806 | if (!cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1807 | return -ENODEV; | |
1808 | ||
1809 | if (target->thread.used_ebb) | |
1810 | return -ENODATA; | |
1811 | ||
1812 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1813 | &target->thread.ebbrr, 0, sizeof(unsigned long)); | |
1814 | ||
1815 | if (!ret) | |
1816 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1817 | &target->thread.ebbhr, sizeof(unsigned long), | |
1818 | 2 * sizeof(unsigned long)); | |
1819 | ||
1820 | if (!ret) | |
1821 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1822 | &target->thread.bescr, | |
1823 | 2 * sizeof(unsigned long), 3 * sizeof(unsigned long)); | |
1824 | ||
1825 | return ret; | |
1826 | } | |
fa439810 | 1827 | #endif |
80fdf470 RM |
1828 | /* |
1829 | * These are our native regset flavors. | |
1830 | */ | |
1831 | enum powerpc_regset { | |
1832 | REGSET_GPR, | |
1833 | REGSET_FPR, | |
1834 | #ifdef CONFIG_ALTIVEC | |
1835 | REGSET_VMX, | |
1836 | #endif | |
ce48b210 MN |
1837 | #ifdef CONFIG_VSX |
1838 | REGSET_VSX, | |
1839 | #endif | |
80fdf470 RM |
1840 | #ifdef CONFIG_SPE |
1841 | REGSET_SPE, | |
1842 | #endif | |
25847fb1 AK |
1843 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1844 | REGSET_TM_CGPR, /* TM checkpointed GPR registers */ | |
19cbcbf7 | 1845 | REGSET_TM_CFPR, /* TM checkpointed FPR registers */ |
8c13f599 | 1846 | REGSET_TM_CVMX, /* TM checkpointed VMX registers */ |
9d3918f7 | 1847 | REGSET_TM_CVSX, /* TM checkpointed VSX registers */ |
08e1c01d | 1848 | REGSET_TM_SPR, /* TM specific SPR registers */ |
c45dc900 AK |
1849 | REGSET_TM_CTAR, /* TM checkpointed TAR register */ |
1850 | REGSET_TM_CPPR, /* TM checkpointed PPR register */ | |
1851 | REGSET_TM_CDSCR, /* TM checkpointed DSCR register */ | |
25847fb1 | 1852 | #endif |
fa439810 AK |
1853 | #ifdef CONFIG_PPC64 |
1854 | REGSET_PPR, /* PPR register */ | |
1855 | REGSET_DSCR, /* DSCR register */ | |
1856 | #endif | |
1857 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1858 | REGSET_TAR, /* TAR register */ | |
cf89d4e1 | 1859 | REGSET_EBB, /* EBB registers */ |
fa439810 | 1860 | #endif |
80fdf470 RM |
1861 | }; |
1862 | ||
1863 | static const struct user_regset native_regsets[] = { | |
1864 | [REGSET_GPR] = { | |
1865 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
1866 | .size = sizeof(long), .align = sizeof(long), | |
1867 | .get = gpr_get, .set = gpr_set | |
1868 | }, | |
1869 | [REGSET_FPR] = { | |
1870 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
1871 | .size = sizeof(double), .align = sizeof(double), | |
1872 | .get = fpr_get, .set = fpr_set | |
1873 | }, | |
1874 | #ifdef CONFIG_ALTIVEC | |
1875 | [REGSET_VMX] = { | |
1876 | .core_note_type = NT_PPC_VMX, .n = 34, | |
1877 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1878 | .active = vr_active, .get = vr_get, .set = vr_set | |
1879 | }, | |
1880 | #endif | |
ce48b210 MN |
1881 | #ifdef CONFIG_VSX |
1882 | [REGSET_VSX] = { | |
f3e909c2 MN |
1883 | .core_note_type = NT_PPC_VSX, .n = 32, |
1884 | .size = sizeof(double), .align = sizeof(double), | |
ce48b210 MN |
1885 | .active = vsr_active, .get = vsr_get, .set = vsr_set |
1886 | }, | |
1887 | #endif | |
80fdf470 RM |
1888 | #ifdef CONFIG_SPE |
1889 | [REGSET_SPE] = { | |
a0b38b4e | 1890 | .core_note_type = NT_PPC_SPE, .n = 35, |
80fdf470 RM |
1891 | .size = sizeof(u32), .align = sizeof(u32), |
1892 | .active = evr_active, .get = evr_get, .set = evr_set | |
1893 | }, | |
1894 | #endif | |
25847fb1 AK |
1895 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1896 | [REGSET_TM_CGPR] = { | |
1897 | .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG, | |
1898 | .size = sizeof(long), .align = sizeof(long), | |
1899 | .active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set | |
1900 | }, | |
19cbcbf7 AK |
1901 | [REGSET_TM_CFPR] = { |
1902 | .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG, | |
1903 | .size = sizeof(double), .align = sizeof(double), | |
1904 | .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set | |
1905 | }, | |
8c13f599 AK |
1906 | [REGSET_TM_CVMX] = { |
1907 | .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX, | |
1908 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1909 | .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set | |
1910 | }, | |
9d3918f7 AK |
1911 | [REGSET_TM_CVSX] = { |
1912 | .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX, | |
1913 | .size = sizeof(double), .align = sizeof(double), | |
1914 | .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set | |
1915 | }, | |
08e1c01d AK |
1916 | [REGSET_TM_SPR] = { |
1917 | .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG, | |
1918 | .size = sizeof(u64), .align = sizeof(u64), | |
1919 | .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set | |
1920 | }, | |
c45dc900 AK |
1921 | [REGSET_TM_CTAR] = { |
1922 | .core_note_type = NT_PPC_TM_CTAR, .n = 1, | |
1923 | .size = sizeof(u64), .align = sizeof(u64), | |
1924 | .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set | |
1925 | }, | |
1926 | [REGSET_TM_CPPR] = { | |
1927 | .core_note_type = NT_PPC_TM_CPPR, .n = 1, | |
1928 | .size = sizeof(u64), .align = sizeof(u64), | |
1929 | .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set | |
1930 | }, | |
1931 | [REGSET_TM_CDSCR] = { | |
1932 | .core_note_type = NT_PPC_TM_CDSCR, .n = 1, | |
1933 | .size = sizeof(u64), .align = sizeof(u64), | |
1934 | .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set | |
1935 | }, | |
25847fb1 | 1936 | #endif |
fa439810 AK |
1937 | #ifdef CONFIG_PPC64 |
1938 | [REGSET_PPR] = { | |
1939 | .core_note_type = NT_PPC_PPR, .n = 1, | |
1940 | .size = sizeof(u64), .align = sizeof(u64), | |
1941 | .get = ppr_get, .set = ppr_set | |
1942 | }, | |
1943 | [REGSET_DSCR] = { | |
1944 | .core_note_type = NT_PPC_DSCR, .n = 1, | |
1945 | .size = sizeof(u64), .align = sizeof(u64), | |
1946 | .get = dscr_get, .set = dscr_set | |
1947 | }, | |
1948 | #endif | |
1949 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1950 | [REGSET_TAR] = { | |
1951 | .core_note_type = NT_PPC_TAR, .n = 1, | |
1952 | .size = sizeof(u64), .align = sizeof(u64), | |
1953 | .get = tar_get, .set = tar_set | |
1954 | }, | |
cf89d4e1 AK |
1955 | [REGSET_EBB] = { |
1956 | .core_note_type = NT_PPC_EBB, .n = ELF_NEBB, | |
1957 | .size = sizeof(u64), .align = sizeof(u64), | |
1958 | .active = ebb_active, .get = ebb_get, .set = ebb_set | |
1959 | }, | |
fa439810 | 1960 | #endif |
80fdf470 RM |
1961 | }; |
1962 | ||
1963 | static const struct user_regset_view user_ppc_native_view = { | |
1964 | .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, | |
1965 | .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets) | |
1966 | }; | |
1967 | ||
fa8f5cb0 RM |
1968 | #ifdef CONFIG_PPC64 |
1969 | #include <linux/compat.h> | |
1970 | ||
04fcadce | 1971 | static int gpr32_get_common(struct task_struct *target, |
fa8f5cb0 RM |
1972 | const struct user_regset *regset, |
1973 | unsigned int pos, unsigned int count, | |
04fcadce | 1974 | void *kbuf, void __user *ubuf, bool tm_active) |
fa8f5cb0 RM |
1975 | { |
1976 | const unsigned long *regs = &target->thread.regs->gpr[0]; | |
04fcadce | 1977 | const unsigned long *ckpt_regs; |
fa8f5cb0 RM |
1978 | compat_ulong_t *k = kbuf; |
1979 | compat_ulong_t __user *u = ubuf; | |
1980 | compat_ulong_t reg; | |
a71f5d5d | 1981 | int i; |
fa8f5cb0 | 1982 | |
04fcadce AK |
1983 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1984 | ckpt_regs = &target->thread.ckpt_regs.gpr[0]; | |
1985 | #endif | |
1986 | if (tm_active) { | |
1987 | regs = ckpt_regs; | |
1988 | } else { | |
1989 | if (target->thread.regs == NULL) | |
1990 | return -EIO; | |
1991 | ||
1992 | if (!FULL_REGS(target->thread.regs)) { | |
1993 | /* | |
1994 | * We have a partial register set. | |
1995 | * Fill 14-31 with bogus values. | |
1996 | */ | |
1997 | for (i = 14; i < 32; i++) | |
1998 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
1999 | } | |
a71f5d5d | 2000 | } |
fa8f5cb0 RM |
2001 | |
2002 | pos /= sizeof(reg); | |
2003 | count /= sizeof(reg); | |
2004 | ||
2005 | if (kbuf) | |
2006 | for (; count > 0 && pos < PT_MSR; --count) | |
2007 | *k++ = regs[pos++]; | |
2008 | else | |
2009 | for (; count > 0 && pos < PT_MSR; --count) | |
2010 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
2011 | return -EFAULT; | |
2012 | ||
2013 | if (count > 0 && pos == PT_MSR) { | |
2014 | reg = get_user_msr(target); | |
2015 | if (kbuf) | |
2016 | *k++ = reg; | |
2017 | else if (__put_user(reg, u++)) | |
2018 | return -EFAULT; | |
2019 | ++pos; | |
2020 | --count; | |
2021 | } | |
2022 | ||
2023 | if (kbuf) | |
2024 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
2025 | *k++ = regs[pos++]; | |
2026 | else | |
2027 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
2028 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
2029 | return -EFAULT; | |
2030 | ||
2031 | kbuf = k; | |
2032 | ubuf = u; | |
2033 | pos *= sizeof(reg); | |
2034 | count *= sizeof(reg); | |
2035 | return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
2036 | PT_REGS_COUNT * sizeof(reg), -1); | |
2037 | } | |
2038 | ||
04fcadce | 2039 | static int gpr32_set_common(struct task_struct *target, |
fa8f5cb0 RM |
2040 | const struct user_regset *regset, |
2041 | unsigned int pos, unsigned int count, | |
04fcadce | 2042 | const void *kbuf, const void __user *ubuf, bool tm_active) |
fa8f5cb0 RM |
2043 | { |
2044 | unsigned long *regs = &target->thread.regs->gpr[0]; | |
04fcadce | 2045 | unsigned long *ckpt_regs; |
fa8f5cb0 RM |
2046 | const compat_ulong_t *k = kbuf; |
2047 | const compat_ulong_t __user *u = ubuf; | |
2048 | compat_ulong_t reg; | |
2049 | ||
04fcadce AK |
2050 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
2051 | ckpt_regs = &target->thread.ckpt_regs.gpr[0]; | |
2052 | #endif | |
fa8f5cb0 | 2053 | |
04fcadce AK |
2054 | if (tm_active) { |
2055 | regs = ckpt_regs; | |
2056 | } else { | |
2057 | regs = &target->thread.regs->gpr[0]; | |
2058 | ||
2059 | if (target->thread.regs == NULL) | |
2060 | return -EIO; | |
2061 | ||
2062 | CHECK_FULL_REGS(target->thread.regs); | |
2063 | } | |
fa8f5cb0 RM |
2064 | |
2065 | pos /= sizeof(reg); | |
2066 | count /= sizeof(reg); | |
2067 | ||
2068 | if (kbuf) | |
2069 | for (; count > 0 && pos < PT_MSR; --count) | |
2070 | regs[pos++] = *k++; | |
2071 | else | |
2072 | for (; count > 0 && pos < PT_MSR; --count) { | |
2073 | if (__get_user(reg, u++)) | |
2074 | return -EFAULT; | |
2075 | regs[pos++] = reg; | |
2076 | } | |
2077 | ||
2078 | ||
2079 | if (count > 0 && pos == PT_MSR) { | |
2080 | if (kbuf) | |
2081 | reg = *k++; | |
2082 | else if (__get_user(reg, u++)) | |
2083 | return -EFAULT; | |
2084 | set_user_msr(target, reg); | |
2085 | ++pos; | |
2086 | --count; | |
2087 | } | |
2088 | ||
c2372eb9 | 2089 | if (kbuf) { |
fa8f5cb0 RM |
2090 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) |
2091 | regs[pos++] = *k++; | |
c2372eb9 RM |
2092 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
2093 | ++k; | |
2094 | } else { | |
fa8f5cb0 RM |
2095 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) { |
2096 | if (__get_user(reg, u++)) | |
2097 | return -EFAULT; | |
2098 | regs[pos++] = reg; | |
2099 | } | |
c2372eb9 RM |
2100 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
2101 | if (__get_user(reg, u++)) | |
2102 | return -EFAULT; | |
2103 | } | |
fa8f5cb0 RM |
2104 | |
2105 | if (count > 0 && pos == PT_TRAP) { | |
2106 | if (kbuf) | |
2107 | reg = *k++; | |
2108 | else if (__get_user(reg, u++)) | |
2109 | return -EFAULT; | |
2110 | set_user_trap(target, reg); | |
2111 | ++pos; | |
2112 | --count; | |
2113 | } | |
2114 | ||
2115 | kbuf = k; | |
2116 | ubuf = u; | |
2117 | pos *= sizeof(reg); | |
2118 | count *= sizeof(reg); | |
2119 | return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, | |
2120 | (PT_TRAP + 1) * sizeof(reg), -1); | |
2121 | } | |
2122 | ||
25847fb1 AK |
2123 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
2124 | static int tm_cgpr32_get(struct task_struct *target, | |
2125 | const struct user_regset *regset, | |
2126 | unsigned int pos, unsigned int count, | |
2127 | void *kbuf, void __user *ubuf) | |
2128 | { | |
2129 | return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 1); | |
2130 | } | |
2131 | ||
2132 | static int tm_cgpr32_set(struct task_struct *target, | |
2133 | const struct user_regset *regset, | |
2134 | unsigned int pos, unsigned int count, | |
2135 | const void *kbuf, const void __user *ubuf) | |
2136 | { | |
2137 | return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 1); | |
2138 | } | |
2139 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
2140 | ||
04fcadce AK |
2141 | static int gpr32_get(struct task_struct *target, |
2142 | const struct user_regset *regset, | |
2143 | unsigned int pos, unsigned int count, | |
2144 | void *kbuf, void __user *ubuf) | |
2145 | { | |
2146 | return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 0); | |
2147 | } | |
2148 | ||
2149 | static int gpr32_set(struct task_struct *target, | |
2150 | const struct user_regset *regset, | |
2151 | unsigned int pos, unsigned int count, | |
2152 | const void *kbuf, const void __user *ubuf) | |
2153 | { | |
2154 | return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 0); | |
2155 | } | |
2156 | ||
fa8f5cb0 RM |
2157 | /* |
2158 | * These are the regset flavors matching the CONFIG_PPC32 native set. | |
2159 | */ | |
2160 | static const struct user_regset compat_regsets[] = { | |
2161 | [REGSET_GPR] = { | |
2162 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
2163 | .size = sizeof(compat_long_t), .align = sizeof(compat_long_t), | |
2164 | .get = gpr32_get, .set = gpr32_set | |
2165 | }, | |
2166 | [REGSET_FPR] = { | |
2167 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
2168 | .size = sizeof(double), .align = sizeof(double), | |
2169 | .get = fpr_get, .set = fpr_set | |
2170 | }, | |
2171 | #ifdef CONFIG_ALTIVEC | |
2172 | [REGSET_VMX] = { | |
2173 | .core_note_type = NT_PPC_VMX, .n = 34, | |
2174 | .size = sizeof(vector128), .align = sizeof(vector128), | |
2175 | .active = vr_active, .get = vr_get, .set = vr_set | |
2176 | }, | |
2177 | #endif | |
2178 | #ifdef CONFIG_SPE | |
2179 | [REGSET_SPE] = { | |
24f1a849 | 2180 | .core_note_type = NT_PPC_SPE, .n = 35, |
fa8f5cb0 RM |
2181 | .size = sizeof(u32), .align = sizeof(u32), |
2182 | .active = evr_active, .get = evr_get, .set = evr_set | |
2183 | }, | |
2184 | #endif | |
25847fb1 AK |
2185 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
2186 | [REGSET_TM_CGPR] = { | |
2187 | .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG, | |
2188 | .size = sizeof(long), .align = sizeof(long), | |
2189 | .active = tm_cgpr_active, | |
2190 | .get = tm_cgpr32_get, .set = tm_cgpr32_set | |
2191 | }, | |
19cbcbf7 AK |
2192 | [REGSET_TM_CFPR] = { |
2193 | .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG, | |
2194 | .size = sizeof(double), .align = sizeof(double), | |
2195 | .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set | |
2196 | }, | |
8c13f599 AK |
2197 | [REGSET_TM_CVMX] = { |
2198 | .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX, | |
2199 | .size = sizeof(vector128), .align = sizeof(vector128), | |
2200 | .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set | |
2201 | }, | |
9d3918f7 AK |
2202 | [REGSET_TM_CVSX] = { |
2203 | .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX, | |
2204 | .size = sizeof(double), .align = sizeof(double), | |
2205 | .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set | |
2206 | }, | |
08e1c01d AK |
2207 | [REGSET_TM_SPR] = { |
2208 | .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG, | |
2209 | .size = sizeof(u64), .align = sizeof(u64), | |
2210 | .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set | |
2211 | }, | |
c45dc900 AK |
2212 | [REGSET_TM_CTAR] = { |
2213 | .core_note_type = NT_PPC_TM_CTAR, .n = 1, | |
2214 | .size = sizeof(u64), .align = sizeof(u64), | |
2215 | .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set | |
2216 | }, | |
2217 | [REGSET_TM_CPPR] = { | |
2218 | .core_note_type = NT_PPC_TM_CPPR, .n = 1, | |
2219 | .size = sizeof(u64), .align = sizeof(u64), | |
2220 | .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set | |
2221 | }, | |
2222 | [REGSET_TM_CDSCR] = { | |
2223 | .core_note_type = NT_PPC_TM_CDSCR, .n = 1, | |
2224 | .size = sizeof(u64), .align = sizeof(u64), | |
2225 | .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set | |
2226 | }, | |
25847fb1 | 2227 | #endif |
fa439810 AK |
2228 | #ifdef CONFIG_PPC64 |
2229 | [REGSET_PPR] = { | |
2230 | .core_note_type = NT_PPC_PPR, .n = 1, | |
2231 | .size = sizeof(u64), .align = sizeof(u64), | |
2232 | .get = ppr_get, .set = ppr_set | |
2233 | }, | |
2234 | [REGSET_DSCR] = { | |
2235 | .core_note_type = NT_PPC_DSCR, .n = 1, | |
2236 | .size = sizeof(u64), .align = sizeof(u64), | |
2237 | .get = dscr_get, .set = dscr_set | |
2238 | }, | |
2239 | #endif | |
2240 | #ifdef CONFIG_PPC_BOOK3S_64 | |
2241 | [REGSET_TAR] = { | |
2242 | .core_note_type = NT_PPC_TAR, .n = 1, | |
2243 | .size = sizeof(u64), .align = sizeof(u64), | |
2244 | .get = tar_get, .set = tar_set | |
2245 | }, | |
cf89d4e1 AK |
2246 | [REGSET_EBB] = { |
2247 | .core_note_type = NT_PPC_EBB, .n = ELF_NEBB, | |
2248 | .size = sizeof(u64), .align = sizeof(u64), | |
2249 | .active = ebb_active, .get = ebb_get, .set = ebb_set | |
2250 | }, | |
fa439810 | 2251 | #endif |
fa8f5cb0 RM |
2252 | }; |
2253 | ||
2254 | static const struct user_regset_view user_ppc_compat_view = { | |
2255 | .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI, | |
2256 | .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets) | |
2257 | }; | |
2258 | #endif /* CONFIG_PPC64 */ | |
2259 | ||
80fdf470 RM |
2260 | const struct user_regset_view *task_user_regset_view(struct task_struct *task) |
2261 | { | |
fa8f5cb0 RM |
2262 | #ifdef CONFIG_PPC64 |
2263 | if (test_tsk_thread_flag(task, TIF_32BIT)) | |
2264 | return &user_ppc_compat_view; | |
2265 | #endif | |
80fdf470 RM |
2266 | return &user_ppc_native_view; |
2267 | } | |
2268 | ||
2269 | ||
2a84b0d7 | 2270 | void user_enable_single_step(struct task_struct *task) |
865418d8 BH |
2271 | { |
2272 | struct pt_regs *regs = task->thread.regs; | |
2273 | ||
2274 | if (regs != NULL) { | |
172ae2e7 | 2275 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
2276 | task->thread.debug.dbcr0 &= ~DBCR0_BT; |
2277 | task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
865418d8 BH |
2278 | regs->msr |= MSR_DE; |
2279 | #else | |
ec097c84 | 2280 | regs->msr &= ~MSR_BE; |
865418d8 BH |
2281 | regs->msr |= MSR_SE; |
2282 | #endif | |
2283 | } | |
2284 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
2285 | } | |
2286 | ||
ec097c84 RM |
2287 | void user_enable_block_step(struct task_struct *task) |
2288 | { | |
2289 | struct pt_regs *regs = task->thread.regs; | |
2290 | ||
2291 | if (regs != NULL) { | |
172ae2e7 | 2292 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
2293 | task->thread.debug.dbcr0 &= ~DBCR0_IC; |
2294 | task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT; | |
ec097c84 RM |
2295 | regs->msr |= MSR_DE; |
2296 | #else | |
2297 | regs->msr &= ~MSR_SE; | |
2298 | regs->msr |= MSR_BE; | |
2299 | #endif | |
2300 | } | |
2301 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
2302 | } | |
2303 | ||
2a84b0d7 | 2304 | void user_disable_single_step(struct task_struct *task) |
865418d8 BH |
2305 | { |
2306 | struct pt_regs *regs = task->thread.regs; | |
2307 | ||
2308 | if (regs != NULL) { | |
172ae2e7 | 2309 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
2310 | /* |
2311 | * The logic to disable single stepping should be as | |
2312 | * simple as turning off the Instruction Complete flag. | |
2313 | * And, after doing so, if all debug flags are off, turn | |
2314 | * off DBCR0(IDM) and MSR(DE) .... Torez | |
2315 | */ | |
682775b8 | 2316 | task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT); |
3bffb652 DK |
2317 | /* |
2318 | * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. | |
2319 | */ | |
51ae8d4a BB |
2320 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
2321 | task->thread.debug.dbcr1)) { | |
3bffb652 DK |
2322 | /* |
2323 | * All debug events were off..... | |
2324 | */ | |
51ae8d4a | 2325 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
28477fb1 DK |
2326 | regs->msr &= ~MSR_DE; |
2327 | } | |
865418d8 | 2328 | #else |
ec097c84 | 2329 | regs->msr &= ~(MSR_SE | MSR_BE); |
865418d8 BH |
2330 | #endif |
2331 | } | |
2332 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); | |
2333 | } | |
2334 | ||
5aae8a53 | 2335 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
a8b0ca17 | 2336 | void ptrace_triggered(struct perf_event *bp, |
5aae8a53 P |
2337 | struct perf_sample_data *data, struct pt_regs *regs) |
2338 | { | |
2339 | struct perf_event_attr attr; | |
2340 | ||
2341 | /* | |
2342 | * Disable the breakpoint request here since ptrace has defined a | |
2343 | * one-shot behaviour for breakpoint exceptions in PPC64. | |
2344 | * The SIGTRAP signal is generated automatically for us in do_dabr(). | |
2345 | * We don't have to do anything about that here | |
2346 | */ | |
2347 | attr = bp->attr; | |
2348 | attr.disabled = true; | |
2349 | modify_user_hw_breakpoint(bp, &attr); | |
2350 | } | |
2351 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
2352 | ||
e51df2c1 | 2353 | static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, |
abd06505 BH |
2354 | unsigned long data) |
2355 | { | |
5aae8a53 P |
2356 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2357 | int ret; | |
2358 | struct thread_struct *thread = &(task->thread); | |
2359 | struct perf_event *bp; | |
2360 | struct perf_event_attr attr; | |
2361 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e MN |
2362 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
2363 | struct arch_hw_breakpoint hw_brk; | |
2364 | #endif | |
5aae8a53 | 2365 | |
d6a61bfc LM |
2366 | /* For ppc64 we support one DABR and no IABR's at the moment (ppc64). |
2367 | * For embedded processors we support one DAC and no IAC's at the | |
2368 | * moment. | |
2369 | */ | |
abd06505 BH |
2370 | if (addr > 0) |
2371 | return -EINVAL; | |
2372 | ||
2325f0a0 | 2373 | /* The bottom 3 bits in dabr are flags */ |
abd06505 BH |
2374 | if ((data & ~0x7UL) >= TASK_SIZE) |
2375 | return -EIO; | |
2376 | ||
172ae2e7 | 2377 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
d6a61bfc LM |
2378 | /* For processors using DABR (i.e. 970), the bottom 3 bits are flags. |
2379 | * It was assumed, on previous implementations, that 3 bits were | |
2380 | * passed together with the data address, fitting the design of the | |
2381 | * DABR register, as follows: | |
2382 | * | |
2383 | * bit 0: Read flag | |
2384 | * bit 1: Write flag | |
2385 | * bit 2: Breakpoint translation | |
2386 | * | |
2387 | * Thus, we use them here as so. | |
2388 | */ | |
2389 | ||
2390 | /* Ensure breakpoint translation bit is set */ | |
9422de3e | 2391 | if (data && !(data & HW_BRK_TYPE_TRANSLATE)) |
abd06505 | 2392 | return -EIO; |
9422de3e MN |
2393 | hw_brk.address = data & (~HW_BRK_TYPE_DABR); |
2394 | hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL; | |
2395 | hw_brk.len = 8; | |
5aae8a53 P |
2396 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2397 | bp = thread->ptrace_bps[0]; | |
9422de3e | 2398 | if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) { |
5aae8a53 P |
2399 | if (bp) { |
2400 | unregister_hw_breakpoint(bp); | |
2401 | thread->ptrace_bps[0] = NULL; | |
2402 | } | |
2403 | return 0; | |
2404 | } | |
2405 | if (bp) { | |
2406 | attr = bp->attr; | |
9422de3e MN |
2407 | attr.bp_addr = hw_brk.address; |
2408 | arch_bp_generic_fields(hw_brk.type, &attr.bp_type); | |
a53fd61a AP |
2409 | |
2410 | /* Enable breakpoint */ | |
2411 | attr.disabled = false; | |
2412 | ||
5aae8a53 | 2413 | ret = modify_user_hw_breakpoint(bp, &attr); |
925f83c0 | 2414 | if (ret) { |
5aae8a53 | 2415 | return ret; |
925f83c0 | 2416 | } |
5aae8a53 | 2417 | thread->ptrace_bps[0] = bp; |
9422de3e | 2418 | thread->hw_brk = hw_brk; |
5aae8a53 P |
2419 | return 0; |
2420 | } | |
2421 | ||
2422 | /* Create a new breakpoint request if one doesn't exist already */ | |
2423 | hw_breakpoint_init(&attr); | |
9422de3e MN |
2424 | attr.bp_addr = hw_brk.address; |
2425 | arch_bp_generic_fields(hw_brk.type, | |
2426 | &attr.bp_type); | |
5aae8a53 P |
2427 | |
2428 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
4dc0da86 | 2429 | ptrace_triggered, NULL, task); |
5aae8a53 P |
2430 | if (IS_ERR(bp)) { |
2431 | thread->ptrace_bps[0] = NULL; | |
2432 | return PTR_ERR(bp); | |
2433 | } | |
2434 | ||
2435 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 2436 | task->thread.hw_brk = hw_brk; |
172ae2e7 | 2437 | #else /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc LM |
2438 | /* As described above, it was assumed 3 bits were passed with the data |
2439 | * address, but we will assume only the mode bits will be passed | |
2440 | * as to not cause alignment restrictions for DAC-based processors. | |
2441 | */ | |
2442 | ||
2443 | /* DAC's hold the whole address without any mode flags */ | |
51ae8d4a | 2444 | task->thread.debug.dac1 = data & ~0x3UL; |
3bffb652 | 2445 | |
51ae8d4a | 2446 | if (task->thread.debug.dac1 == 0) { |
3bffb652 | 2447 | dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
51ae8d4a BB |
2448 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
2449 | task->thread.debug.dbcr1)) { | |
3bffb652 | 2450 | task->thread.regs->msr &= ~MSR_DE; |
51ae8d4a | 2451 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 | 2452 | } |
d6a61bfc LM |
2453 | return 0; |
2454 | } | |
2455 | ||
2456 | /* Read or Write bits must be set */ | |
2457 | ||
2458 | if (!(data & 0x3UL)) | |
2459 | return -EINVAL; | |
2460 | ||
2461 | /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 | |
2462 | register */ | |
51ae8d4a | 2463 | task->thread.debug.dbcr0 |= DBCR0_IDM; |
d6a61bfc LM |
2464 | |
2465 | /* Check for write and read flags and set DBCR0 | |
2466 | accordingly */ | |
3bffb652 | 2467 | dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W); |
d6a61bfc | 2468 | if (data & 0x1UL) |
3bffb652 | 2469 | dbcr_dac(task) |= DBCR_DAC1R; |
d6a61bfc | 2470 | if (data & 0x2UL) |
3bffb652 | 2471 | dbcr_dac(task) |= DBCR_DAC1W; |
d6a61bfc | 2472 | task->thread.regs->msr |= MSR_DE; |
172ae2e7 | 2473 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
abd06505 BH |
2474 | return 0; |
2475 | } | |
abd06505 | 2476 | |
1da177e4 LT |
2477 | /* |
2478 | * Called by kernel/ptrace.c when detaching.. | |
2479 | * | |
2480 | * Make sure single step bits etc are not set. | |
2481 | */ | |
2482 | void ptrace_disable(struct task_struct *child) | |
2483 | { | |
2484 | /* make sure the single step bit is not set. */ | |
2a84b0d7 | 2485 | user_disable_single_step(child); |
1da177e4 LT |
2486 | } |
2487 | ||
3bffb652 | 2488 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
84295dfc | 2489 | static long set_instruction_bp(struct task_struct *child, |
3bffb652 DK |
2490 | struct ppc_hw_breakpoint *bp_info) |
2491 | { | |
2492 | int slot; | |
51ae8d4a BB |
2493 | int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0); |
2494 | int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0); | |
2495 | int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0); | |
2496 | int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0); | |
3bffb652 DK |
2497 | |
2498 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
2499 | slot2_in_use = 1; | |
2500 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
2501 | slot4_in_use = 1; | |
2502 | ||
2503 | if (bp_info->addr >= TASK_SIZE) | |
2504 | return -EIO; | |
2505 | ||
2506 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { | |
2507 | ||
2508 | /* Make sure range is valid. */ | |
2509 | if (bp_info->addr2 >= TASK_SIZE) | |
2510 | return -EIO; | |
2511 | ||
2512 | /* We need a pair of IAC regsisters */ | |
2513 | if ((!slot1_in_use) && (!slot2_in_use)) { | |
2514 | slot = 1; | |
51ae8d4a BB |
2515 | child->thread.debug.iac1 = bp_info->addr; |
2516 | child->thread.debug.iac2 = bp_info->addr2; | |
2517 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
2518 | if (bp_info->addr_mode == |
2519 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
2520 | dbcr_iac_range(child) |= DBCR_IAC12X; | |
2521 | else | |
2522 | dbcr_iac_range(child) |= DBCR_IAC12I; | |
2523 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
2524 | } else if ((!slot3_in_use) && (!slot4_in_use)) { | |
2525 | slot = 3; | |
51ae8d4a BB |
2526 | child->thread.debug.iac3 = bp_info->addr; |
2527 | child->thread.debug.iac4 = bp_info->addr2; | |
2528 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
2529 | if (bp_info->addr_mode == |
2530 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
2531 | dbcr_iac_range(child) |= DBCR_IAC34X; | |
2532 | else | |
2533 | dbcr_iac_range(child) |= DBCR_IAC34I; | |
2534 | #endif | |
2535 | } else | |
2536 | return -ENOSPC; | |
2537 | } else { | |
2538 | /* We only need one. If possible leave a pair free in | |
2539 | * case a range is needed later | |
2540 | */ | |
2541 | if (!slot1_in_use) { | |
2542 | /* | |
2543 | * Don't use iac1 if iac1-iac2 are free and either | |
2544 | * iac3 or iac4 (but not both) are free | |
2545 | */ | |
2546 | if (slot2_in_use || (slot3_in_use == slot4_in_use)) { | |
2547 | slot = 1; | |
51ae8d4a BB |
2548 | child->thread.debug.iac1 = bp_info->addr; |
2549 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
2550 | goto out; |
2551 | } | |
2552 | } | |
2553 | if (!slot2_in_use) { | |
2554 | slot = 2; | |
51ae8d4a BB |
2555 | child->thread.debug.iac2 = bp_info->addr; |
2556 | child->thread.debug.dbcr0 |= DBCR0_IAC2; | |
3bffb652 DK |
2557 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
2558 | } else if (!slot3_in_use) { | |
2559 | slot = 3; | |
51ae8d4a BB |
2560 | child->thread.debug.iac3 = bp_info->addr; |
2561 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
2562 | } else if (!slot4_in_use) { |
2563 | slot = 4; | |
51ae8d4a BB |
2564 | child->thread.debug.iac4 = bp_info->addr; |
2565 | child->thread.debug.dbcr0 |= DBCR0_IAC4; | |
3bffb652 DK |
2566 | #endif |
2567 | } else | |
2568 | return -ENOSPC; | |
2569 | } | |
2570 | out: | |
51ae8d4a | 2571 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
2572 | child->thread.regs->msr |= MSR_DE; |
2573 | ||
2574 | return slot; | |
2575 | } | |
2576 | ||
2577 | static int del_instruction_bp(struct task_struct *child, int slot) | |
2578 | { | |
2579 | switch (slot) { | |
2580 | case 1: | |
51ae8d4a | 2581 | if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0) |
3bffb652 DK |
2582 | return -ENOENT; |
2583 | ||
2584 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) { | |
2585 | /* address range - clear slots 1 & 2 */ | |
51ae8d4a | 2586 | child->thread.debug.iac2 = 0; |
3bffb652 DK |
2587 | dbcr_iac_range(child) &= ~DBCR_IAC12MODE; |
2588 | } | |
51ae8d4a BB |
2589 | child->thread.debug.iac1 = 0; |
2590 | child->thread.debug.dbcr0 &= ~DBCR0_IAC1; | |
3bffb652 DK |
2591 | break; |
2592 | case 2: | |
51ae8d4a | 2593 | if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0) |
3bffb652 DK |
2594 | return -ENOENT; |
2595 | ||
2596 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
2597 | /* used in a range */ | |
2598 | return -EINVAL; | |
51ae8d4a BB |
2599 | child->thread.debug.iac2 = 0; |
2600 | child->thread.debug.dbcr0 &= ~DBCR0_IAC2; | |
3bffb652 DK |
2601 | break; |
2602 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
2603 | case 3: | |
51ae8d4a | 2604 | if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0) |
3bffb652 DK |
2605 | return -ENOENT; |
2606 | ||
2607 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) { | |
2608 | /* address range - clear slots 3 & 4 */ | |
51ae8d4a | 2609 | child->thread.debug.iac4 = 0; |
3bffb652 DK |
2610 | dbcr_iac_range(child) &= ~DBCR_IAC34MODE; |
2611 | } | |
51ae8d4a BB |
2612 | child->thread.debug.iac3 = 0; |
2613 | child->thread.debug.dbcr0 &= ~DBCR0_IAC3; | |
3bffb652 DK |
2614 | break; |
2615 | case 4: | |
51ae8d4a | 2616 | if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0) |
3bffb652 DK |
2617 | return -ENOENT; |
2618 | ||
2619 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
2620 | /* Used in a range */ | |
2621 | return -EINVAL; | |
51ae8d4a BB |
2622 | child->thread.debug.iac4 = 0; |
2623 | child->thread.debug.dbcr0 &= ~DBCR0_IAC4; | |
3bffb652 DK |
2624 | break; |
2625 | #endif | |
2626 | default: | |
2627 | return -EINVAL; | |
2628 | } | |
2629 | return 0; | |
2630 | } | |
2631 | ||
2632 | static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) | |
2633 | { | |
2634 | int byte_enable = | |
2635 | (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT) | |
2636 | & 0xf; | |
2637 | int condition_mode = | |
2638 | bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE; | |
2639 | int slot; | |
2640 | ||
2641 | if (byte_enable && (condition_mode == 0)) | |
2642 | return -EINVAL; | |
2643 | ||
2644 | if (bp_info->addr >= TASK_SIZE) | |
2645 | return -EIO; | |
2646 | ||
2647 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) { | |
2648 | slot = 1; | |
2649 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
2650 | dbcr_dac(child) |= DBCR_DAC1R; | |
2651 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
2652 | dbcr_dac(child) |= DBCR_DAC1W; | |
51ae8d4a | 2653 | child->thread.debug.dac1 = (unsigned long)bp_info->addr; |
3bffb652 DK |
2654 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
2655 | if (byte_enable) { | |
51ae8d4a | 2656 | child->thread.debug.dvc1 = |
3bffb652 | 2657 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 2658 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
2659 | ((byte_enable << DBCR2_DVC1BE_SHIFT) | |
2660 | (condition_mode << DBCR2_DVC1M_SHIFT)); | |
2661 | } | |
2662 | #endif | |
2663 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 2664 | } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
3bffb652 DK |
2665 | /* Both dac1 and dac2 are part of a range */ |
2666 | return -ENOSPC; | |
2667 | #endif | |
2668 | } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) { | |
2669 | slot = 2; | |
2670 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
2671 | dbcr_dac(child) |= DBCR_DAC2R; | |
2672 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
2673 | dbcr_dac(child) |= DBCR_DAC2W; | |
51ae8d4a | 2674 | child->thread.debug.dac2 = (unsigned long)bp_info->addr; |
3bffb652 DK |
2675 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
2676 | if (byte_enable) { | |
51ae8d4a | 2677 | child->thread.debug.dvc2 = |
3bffb652 | 2678 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 2679 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
2680 | ((byte_enable << DBCR2_DVC2BE_SHIFT) | |
2681 | (condition_mode << DBCR2_DVC2M_SHIFT)); | |
2682 | } | |
2683 | #endif | |
2684 | } else | |
2685 | return -ENOSPC; | |
51ae8d4a | 2686 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
2687 | child->thread.regs->msr |= MSR_DE; |
2688 | ||
2689 | return slot + 4; | |
2690 | } | |
2691 | ||
2692 | static int del_dac(struct task_struct *child, int slot) | |
2693 | { | |
2694 | if (slot == 1) { | |
30124d11 | 2695 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) |
3bffb652 DK |
2696 | return -ENOENT; |
2697 | ||
51ae8d4a | 2698 | child->thread.debug.dac1 = 0; |
3bffb652 DK |
2699 | dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
2700 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a BB |
2701 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
2702 | child->thread.debug.dac2 = 0; | |
2703 | child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; | |
3bffb652 | 2704 | } |
51ae8d4a | 2705 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); |
3bffb652 DK |
2706 | #endif |
2707 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 2708 | child->thread.debug.dvc1 = 0; |
3bffb652 DK |
2709 | #endif |
2710 | } else if (slot == 2) { | |
30124d11 | 2711 | if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) |
3bffb652 DK |
2712 | return -ENOENT; |
2713 | ||
2714 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 2715 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) |
3bffb652 DK |
2716 | /* Part of a range */ |
2717 | return -EINVAL; | |
51ae8d4a | 2718 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); |
3bffb652 DK |
2719 | #endif |
2720 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 2721 | child->thread.debug.dvc2 = 0; |
3bffb652 | 2722 | #endif |
51ae8d4a | 2723 | child->thread.debug.dac2 = 0; |
3bffb652 DK |
2724 | dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
2725 | } else | |
2726 | return -EINVAL; | |
2727 | ||
2728 | return 0; | |
2729 | } | |
2730 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ | |
2731 | ||
2732 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2733 | static int set_dac_range(struct task_struct *child, | |
2734 | struct ppc_hw_breakpoint *bp_info) | |
2735 | { | |
2736 | int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK; | |
2737 | ||
2738 | /* We don't allow range watchpoints to be used with DVC */ | |
2739 | if (bp_info->condition_mode) | |
2740 | return -EINVAL; | |
2741 | ||
2742 | /* | |
2743 | * Best effort to verify the address range. The user/supervisor bits | |
2744 | * prevent trapping in kernel space, but let's fail on an obvious bad | |
2745 | * range. The simple test on the mask is not fool-proof, and any | |
2746 | * exclusive range will spill over into kernel space. | |
2747 | */ | |
2748 | if (bp_info->addr >= TASK_SIZE) | |
2749 | return -EIO; | |
2750 | if (mode == PPC_BREAKPOINT_MODE_MASK) { | |
2751 | /* | |
2752 | * dac2 is a bitmask. Don't allow a mask that makes a | |
2753 | * kernel space address from a valid dac1 value | |
2754 | */ | |
2755 | if (~((unsigned long)bp_info->addr2) >= TASK_SIZE) | |
2756 | return -EIO; | |
2757 | } else { | |
2758 | /* | |
2759 | * For range breakpoints, addr2 must also be a valid address | |
2760 | */ | |
2761 | if (bp_info->addr2 >= TASK_SIZE) | |
2762 | return -EIO; | |
2763 | } | |
2764 | ||
51ae8d4a | 2765 | if (child->thread.debug.dbcr0 & |
3bffb652 DK |
2766 | (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) |
2767 | return -ENOSPC; | |
2768 | ||
2769 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
51ae8d4a | 2770 | child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); |
3bffb652 | 2771 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
51ae8d4a BB |
2772 | child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); |
2773 | child->thread.debug.dac1 = bp_info->addr; | |
2774 | child->thread.debug.dac2 = bp_info->addr2; | |
3bffb652 | 2775 | if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
51ae8d4a | 2776 | child->thread.debug.dbcr2 |= DBCR2_DAC12M; |
3bffb652 | 2777 | else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
51ae8d4a | 2778 | child->thread.debug.dbcr2 |= DBCR2_DAC12MX; |
3bffb652 | 2779 | else /* PPC_BREAKPOINT_MODE_MASK */ |
51ae8d4a | 2780 | child->thread.debug.dbcr2 |= DBCR2_DAC12MM; |
3bffb652 DK |
2781 | child->thread.regs->msr |= MSR_DE; |
2782 | ||
2783 | return 5; | |
2784 | } | |
2785 | #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */ | |
2786 | ||
3162d92d DK |
2787 | static long ppc_set_hwdebug(struct task_struct *child, |
2788 | struct ppc_hw_breakpoint *bp_info) | |
2789 | { | |
6c7a2856 P |
2790 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2791 | int len = 0; | |
2792 | struct thread_struct *thread = &(child->thread); | |
2793 | struct perf_event *bp; | |
2794 | struct perf_event_attr attr; | |
2795 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
4dfbf290 | 2796 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e | 2797 | struct arch_hw_breakpoint brk; |
4dfbf290 AS |
2798 | #endif |
2799 | ||
3bffb652 DK |
2800 | if (bp_info->version != 1) |
2801 | return -ENOTSUPP; | |
2802 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | |
2803 | /* | |
2804 | * Check for invalid flags and combinations | |
2805 | */ | |
2806 | if ((bp_info->trigger_type == 0) || | |
2807 | (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE | | |
2808 | PPC_BREAKPOINT_TRIGGER_RW)) || | |
2809 | (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) || | |
2810 | (bp_info->condition_mode & | |
2811 | ~(PPC_BREAKPOINT_CONDITION_MODE | | |
2812 | PPC_BREAKPOINT_CONDITION_BE_ALL))) | |
2813 | return -EINVAL; | |
2814 | #if CONFIG_PPC_ADV_DEBUG_DVCS == 0 | |
2815 | if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) | |
2816 | return -EINVAL; | |
2817 | #endif | |
2818 | ||
2819 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) { | |
2820 | if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) || | |
2821 | (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) | |
2822 | return -EINVAL; | |
84295dfc | 2823 | return set_instruction_bp(child, bp_info); |
3bffb652 DK |
2824 | } |
2825 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) | |
2826 | return set_dac(child, bp_info); | |
2827 | ||
2828 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2829 | return set_dac_range(child, bp_info); | |
2830 | #else | |
2831 | return -EINVAL; | |
2832 | #endif | |
2833 | #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */ | |
3162d92d | 2834 | /* |
3bffb652 | 2835 | * We only support one data breakpoint |
3162d92d | 2836 | */ |
4dfbf290 AS |
2837 | if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 || |
2838 | (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 || | |
4dfbf290 | 2839 | bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) |
3162d92d DK |
2840 | return -EINVAL; |
2841 | ||
3162d92d DK |
2842 | if ((unsigned long)bp_info->addr >= TASK_SIZE) |
2843 | return -EIO; | |
2844 | ||
9422de3e MN |
2845 | brk.address = bp_info->addr & ~7UL; |
2846 | brk.type = HW_BRK_TYPE_TRANSLATE; | |
2bb78efa | 2847 | brk.len = 8; |
4dfbf290 | 2848 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
9422de3e | 2849 | brk.type |= HW_BRK_TYPE_READ; |
4dfbf290 | 2850 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
9422de3e | 2851 | brk.type |= HW_BRK_TYPE_WRITE; |
6c7a2856 | 2852 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
6c7a2856 P |
2853 | /* |
2854 | * Check if the request is for 'range' breakpoints. We can | |
2855 | * support it if range < 8 bytes. | |
2856 | */ | |
6961ed96 | 2857 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
6c7a2856 | 2858 | len = bp_info->addr2 - bp_info->addr; |
6961ed96 | 2859 | else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) |
b0b0aa9c | 2860 | len = 1; |
6961ed96 | 2861 | else |
6c7a2856 | 2862 | return -EINVAL; |
6c7a2856 | 2863 | bp = thread->ptrace_bps[0]; |
6961ed96 | 2864 | if (bp) |
6c7a2856 | 2865 | return -ENOSPC; |
6c7a2856 P |
2866 | |
2867 | /* Create a new breakpoint request if one doesn't exist already */ | |
2868 | hw_breakpoint_init(&attr); | |
2869 | attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN; | |
2870 | attr.bp_len = len; | |
9422de3e | 2871 | arch_bp_generic_fields(brk.type, &attr.bp_type); |
6c7a2856 P |
2872 | |
2873 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
2874 | ptrace_triggered, NULL, child); | |
2875 | if (IS_ERR(bp)) { | |
2876 | thread->ptrace_bps[0] = NULL; | |
6c7a2856 P |
2877 | return PTR_ERR(bp); |
2878 | } | |
2879 | ||
6c7a2856 P |
2880 | return 1; |
2881 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
2882 | ||
2883 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) | |
2884 | return -EINVAL; | |
2885 | ||
9422de3e | 2886 | if (child->thread.hw_brk.address) |
6c7a2856 | 2887 | return -ENOSPC; |
4dfbf290 | 2888 | |
9422de3e | 2889 | child->thread.hw_brk = brk; |
3bffb652 | 2890 | |
3162d92d | 2891 | return 1; |
3bffb652 | 2892 | #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ |
3162d92d DK |
2893 | } |
2894 | ||
ec1b33dc | 2895 | static long ppc_del_hwdebug(struct task_struct *child, long data) |
3162d92d | 2896 | { |
6c7a2856 P |
2897 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2898 | int ret = 0; | |
2899 | struct thread_struct *thread = &(child->thread); | |
2900 | struct perf_event *bp; | |
2901 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
3bffb652 DK |
2902 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
2903 | int rc; | |
2904 | ||
2905 | if (data <= 4) | |
2906 | rc = del_instruction_bp(child, (int)data); | |
2907 | else | |
2908 | rc = del_dac(child, (int)data - 4); | |
2909 | ||
2910 | if (!rc) { | |
51ae8d4a BB |
2911 | if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0, |
2912 | child->thread.debug.dbcr1)) { | |
2913 | child->thread.debug.dbcr0 &= ~DBCR0_IDM; | |
3bffb652 DK |
2914 | child->thread.regs->msr &= ~MSR_DE; |
2915 | } | |
2916 | } | |
2917 | return rc; | |
2918 | #else | |
3162d92d DK |
2919 | if (data != 1) |
2920 | return -EINVAL; | |
6c7a2856 P |
2921 | |
2922 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
6c7a2856 P |
2923 | bp = thread->ptrace_bps[0]; |
2924 | if (bp) { | |
2925 | unregister_hw_breakpoint(bp); | |
2926 | thread->ptrace_bps[0] = NULL; | |
2927 | } else | |
2928 | ret = -ENOENT; | |
6c7a2856 P |
2929 | return ret; |
2930 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 2931 | if (child->thread.hw_brk.address == 0) |
3162d92d DK |
2932 | return -ENOENT; |
2933 | ||
9422de3e MN |
2934 | child->thread.hw_brk.address = 0; |
2935 | child->thread.hw_brk.type = 0; | |
6c7a2856 | 2936 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 2937 | |
3162d92d | 2938 | return 0; |
3bffb652 | 2939 | #endif |
3162d92d DK |
2940 | } |
2941 | ||
9b05a69e NK |
2942 | long arch_ptrace(struct task_struct *child, long request, |
2943 | unsigned long addr, unsigned long data) | |
1da177e4 | 2944 | { |
1da177e4 | 2945 | int ret = -EPERM; |
f68d2048 NK |
2946 | void __user *datavp = (void __user *) data; |
2947 | unsigned long __user *datalp = datavp; | |
1da177e4 | 2948 | |
1da177e4 | 2949 | switch (request) { |
1da177e4 | 2950 | /* read the word at location addr in the USER area. */ |
1da177e4 LT |
2951 | case PTRACE_PEEKUSR: { |
2952 | unsigned long index, tmp; | |
2953 | ||
2954 | ret = -EIO; | |
2955 | /* convert to index and check */ | |
e8a30302 | 2956 | #ifdef CONFIG_PPC32 |
9b05a69e | 2957 | index = addr >> 2; |
e8a30302 SR |
2958 | if ((addr & 3) || (index > PT_FPSCR) |
2959 | || (child->thread.regs == NULL)) | |
2960 | #else | |
9b05a69e | 2961 | index = addr >> 3; |
e8a30302 SR |
2962 | if ((addr & 7) || (index > PT_FPSCR)) |
2963 | #endif | |
1da177e4 LT |
2964 | break; |
2965 | ||
2966 | CHECK_FULL_REGS(child->thread.regs); | |
2967 | if (index < PT_FPR0) { | |
ee4a3916 AK |
2968 | ret = ptrace_get_reg(child, (int) index, &tmp); |
2969 | if (ret) | |
2970 | break; | |
1da177e4 | 2971 | } else { |
e69b742a BH |
2972 | unsigned int fpidx = index - PT_FPR0; |
2973 | ||
e8a30302 | 2974 | flush_fp_to_thread(child); |
e69b742a | 2975 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 2976 | memcpy(&tmp, &child->thread.TS_FPR(fpidx), |
87fec051 | 2977 | sizeof(long)); |
e69b742a | 2978 | else |
de79f7b9 | 2979 | tmp = child->thread.fp_state.fpscr; |
1da177e4 | 2980 | } |
f68d2048 | 2981 | ret = put_user(tmp, datalp); |
1da177e4 LT |
2982 | break; |
2983 | } | |
2984 | ||
1da177e4 LT |
2985 | /* write the word at location addr in the USER area */ |
2986 | case PTRACE_POKEUSR: { | |
2987 | unsigned long index; | |
2988 | ||
2989 | ret = -EIO; | |
2990 | /* convert to index and check */ | |
e8a30302 | 2991 | #ifdef CONFIG_PPC32 |
9b05a69e | 2992 | index = addr >> 2; |
e8a30302 SR |
2993 | if ((addr & 3) || (index > PT_FPSCR) |
2994 | || (child->thread.regs == NULL)) | |
2995 | #else | |
9b05a69e | 2996 | index = addr >> 3; |
e8a30302 SR |
2997 | if ((addr & 7) || (index > PT_FPSCR)) |
2998 | #endif | |
1da177e4 LT |
2999 | break; |
3000 | ||
3001 | CHECK_FULL_REGS(child->thread.regs); | |
1da177e4 | 3002 | if (index < PT_FPR0) { |
865418d8 | 3003 | ret = ptrace_put_reg(child, index, data); |
1da177e4 | 3004 | } else { |
e69b742a BH |
3005 | unsigned int fpidx = index - PT_FPR0; |
3006 | ||
e8a30302 | 3007 | flush_fp_to_thread(child); |
e69b742a | 3008 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 3009 | memcpy(&child->thread.TS_FPR(fpidx), &data, |
87fec051 | 3010 | sizeof(long)); |
e69b742a | 3011 | else |
de79f7b9 | 3012 | child->thread.fp_state.fpscr = data; |
1da177e4 LT |
3013 | ret = 0; |
3014 | } | |
3015 | break; | |
3016 | } | |
3017 | ||
3162d92d DK |
3018 | case PPC_PTRACE_GETHWDBGINFO: { |
3019 | struct ppc_debug_info dbginfo; | |
3020 | ||
3021 | dbginfo.version = 1; | |
3bffb652 DK |
3022 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3023 | dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS; | |
3024 | dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS; | |
3025 | dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS; | |
3026 | dbginfo.data_bp_alignment = 4; | |
3027 | dbginfo.sizeof_condition = 4; | |
3028 | dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE | | |
3029 | PPC_DEBUG_FEATURE_INSN_BP_MASK; | |
3030 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
3031 | dbginfo.features |= | |
3032 | PPC_DEBUG_FEATURE_DATA_BP_RANGE | | |
3033 | PPC_DEBUG_FEATURE_DATA_BP_MASK; | |
3034 | #endif | |
3035 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
3162d92d DK |
3036 | dbginfo.num_instruction_bps = 0; |
3037 | dbginfo.num_data_bps = 1; | |
3038 | dbginfo.num_condition_regs = 0; | |
3039 | #ifdef CONFIG_PPC64 | |
3040 | dbginfo.data_bp_alignment = 8; | |
3041 | #else | |
3042 | dbginfo.data_bp_alignment = 4; | |
3043 | #endif | |
3044 | dbginfo.sizeof_condition = 0; | |
6c7a2856 P |
3045 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
3046 | dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE; | |
517b7314 MN |
3047 | if (cpu_has_feature(CPU_FTR_DAWR)) |
3048 | dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR; | |
6c7a2856 | 3049 | #else |
3162d92d | 3050 | dbginfo.features = 0; |
6c7a2856 | 3051 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 3052 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
3162d92d | 3053 | |
f68d2048 | 3054 | if (!access_ok(VERIFY_WRITE, datavp, |
3162d92d DK |
3055 | sizeof(struct ppc_debug_info))) |
3056 | return -EFAULT; | |
f68d2048 NK |
3057 | ret = __copy_to_user(datavp, &dbginfo, |
3058 | sizeof(struct ppc_debug_info)) ? | |
3162d92d DK |
3059 | -EFAULT : 0; |
3060 | break; | |
3061 | } | |
3062 | ||
3063 | case PPC_PTRACE_SETHWDEBUG: { | |
3064 | struct ppc_hw_breakpoint bp_info; | |
3065 | ||
f68d2048 | 3066 | if (!access_ok(VERIFY_READ, datavp, |
3162d92d DK |
3067 | sizeof(struct ppc_hw_breakpoint))) |
3068 | return -EFAULT; | |
f68d2048 | 3069 | ret = __copy_from_user(&bp_info, datavp, |
3162d92d DK |
3070 | sizeof(struct ppc_hw_breakpoint)) ? |
3071 | -EFAULT : 0; | |
3072 | if (!ret) | |
3073 | ret = ppc_set_hwdebug(child, &bp_info); | |
3074 | break; | |
3075 | } | |
3076 | ||
3077 | case PPC_PTRACE_DELHWDEBUG: { | |
ec1b33dc | 3078 | ret = ppc_del_hwdebug(child, data); |
3162d92d DK |
3079 | break; |
3080 | } | |
3081 | ||
e8a30302 | 3082 | case PTRACE_GET_DEBUGREG: { |
9422de3e MN |
3083 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
3084 | unsigned long dabr_fake; | |
3085 | #endif | |
e8a30302 SR |
3086 | ret = -EINVAL; |
3087 | /* We only support one DABR and no IABRS at the moment */ | |
3088 | if (addr > 0) | |
3089 | break; | |
3bffb652 | 3090 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a | 3091 | ret = put_user(child->thread.debug.dac1, datalp); |
3bffb652 | 3092 | #else |
9422de3e MN |
3093 | dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | |
3094 | (child->thread.hw_brk.type & HW_BRK_TYPE_DABR)); | |
3095 | ret = put_user(dabr_fake, datalp); | |
3bffb652 | 3096 | #endif |
e8a30302 SR |
3097 | break; |
3098 | } | |
3099 | ||
3100 | case PTRACE_SET_DEBUGREG: | |
3101 | ret = ptrace_set_debugreg(child, addr, data); | |
3102 | break; | |
e8a30302 | 3103 | |
e17666ba BH |
3104 | #ifdef CONFIG_PPC64 |
3105 | case PTRACE_GETREGS64: | |
3106 | #endif | |
c391cd00 RM |
3107 | case PTRACE_GETREGS: /* Get all pt_regs from the child. */ |
3108 | return copy_regset_to_user(child, &user_ppc_native_view, | |
3109 | REGSET_GPR, | |
3110 | 0, sizeof(struct pt_regs), | |
f68d2048 | 3111 | datavp); |
e8a30302 | 3112 | |
e17666ba BH |
3113 | #ifdef CONFIG_PPC64 |
3114 | case PTRACE_SETREGS64: | |
3115 | #endif | |
c391cd00 RM |
3116 | case PTRACE_SETREGS: /* Set all gp regs in the child. */ |
3117 | return copy_regset_from_user(child, &user_ppc_native_view, | |
3118 | REGSET_GPR, | |
3119 | 0, sizeof(struct pt_regs), | |
f68d2048 | 3120 | datavp); |
c391cd00 RM |
3121 | |
3122 | case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */ | |
3123 | return copy_regset_to_user(child, &user_ppc_native_view, | |
3124 | REGSET_FPR, | |
3125 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 3126 | datavp); |
c391cd00 RM |
3127 | |
3128 | case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */ | |
3129 | return copy_regset_from_user(child, &user_ppc_native_view, | |
3130 | REGSET_FPR, | |
3131 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 3132 | datavp); |
e8a30302 | 3133 | |
1da177e4 LT |
3134 | #ifdef CONFIG_ALTIVEC |
3135 | case PTRACE_GETVRREGS: | |
c391cd00 RM |
3136 | return copy_regset_to_user(child, &user_ppc_native_view, |
3137 | REGSET_VMX, | |
3138 | 0, (33 * sizeof(vector128) + | |
3139 | sizeof(u32)), | |
f68d2048 | 3140 | datavp); |
1da177e4 LT |
3141 | |
3142 | case PTRACE_SETVRREGS: | |
c391cd00 RM |
3143 | return copy_regset_from_user(child, &user_ppc_native_view, |
3144 | REGSET_VMX, | |
3145 | 0, (33 * sizeof(vector128) + | |
3146 | sizeof(u32)), | |
f68d2048 | 3147 | datavp); |
1da177e4 | 3148 | #endif |
ce48b210 MN |
3149 | #ifdef CONFIG_VSX |
3150 | case PTRACE_GETVSRREGS: | |
3151 | return copy_regset_to_user(child, &user_ppc_native_view, | |
3152 | REGSET_VSX, | |
1ac42ef8 | 3153 | 0, 32 * sizeof(double), |
f68d2048 | 3154 | datavp); |
ce48b210 MN |
3155 | |
3156 | case PTRACE_SETVSRREGS: | |
3157 | return copy_regset_from_user(child, &user_ppc_native_view, | |
3158 | REGSET_VSX, | |
1ac42ef8 | 3159 | 0, 32 * sizeof(double), |
f68d2048 | 3160 | datavp); |
ce48b210 | 3161 | #endif |
1da177e4 LT |
3162 | #ifdef CONFIG_SPE |
3163 | case PTRACE_GETEVRREGS: | |
3164 | /* Get the child spe register state. */ | |
c391cd00 RM |
3165 | return copy_regset_to_user(child, &user_ppc_native_view, |
3166 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 3167 | datavp); |
1da177e4 LT |
3168 | |
3169 | case PTRACE_SETEVRREGS: | |
3170 | /* Set the child spe register state. */ | |
c391cd00 RM |
3171 | return copy_regset_from_user(child, &user_ppc_native_view, |
3172 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 3173 | datavp); |
1da177e4 LT |
3174 | #endif |
3175 | ||
3176 | default: | |
3177 | ret = ptrace_request(child, request, addr, data); | |
3178 | break; | |
3179 | } | |
1da177e4 LT |
3180 | return ret; |
3181 | } | |
3182 | ||
2449acc5 ME |
3183 | #ifdef CONFIG_SECCOMP |
3184 | static int do_seccomp(struct pt_regs *regs) | |
3185 | { | |
3186 | if (!test_thread_flag(TIF_SECCOMP)) | |
3187 | return 0; | |
3188 | ||
3189 | /* | |
3190 | * The ABI we present to seccomp tracers is that r3 contains | |
3191 | * the syscall return value and orig_gpr3 contains the first | |
3192 | * syscall parameter. This is different to the ptrace ABI where | |
3193 | * both r3 and orig_gpr3 contain the first syscall parameter. | |
3194 | */ | |
3195 | regs->gpr[3] = -ENOSYS; | |
3196 | ||
3197 | /* | |
3198 | * We use the __ version here because we have already checked | |
3199 | * TIF_SECCOMP. If this fails, there is nothing left to do, we | |
3200 | * have already loaded -ENOSYS into r3, or seccomp has put | |
3201 | * something else in r3 (via SECCOMP_RET_ERRNO/TRACE). | |
3202 | */ | |
2f275de5 | 3203 | if (__secure_computing(NULL)) |
2449acc5 ME |
3204 | return -1; |
3205 | ||
3206 | /* | |
3207 | * The syscall was allowed by seccomp, restore the register | |
1addc57e | 3208 | * state to what audit expects. |
2449acc5 ME |
3209 | * Note that we use orig_gpr3, which means a seccomp tracer can |
3210 | * modify the first syscall parameter (in orig_gpr3) and also | |
3211 | * allow the syscall to proceed. | |
3212 | */ | |
3213 | regs->gpr[3] = regs->orig_gpr3; | |
3214 | ||
3215 | return 0; | |
3216 | } | |
3217 | #else | |
3218 | static inline int do_seccomp(struct pt_regs *regs) { return 0; } | |
3219 | #endif /* CONFIG_SECCOMP */ | |
3220 | ||
d3837414 ME |
3221 | /** |
3222 | * do_syscall_trace_enter() - Do syscall tracing on kernel entry. | |
3223 | * @regs: the pt_regs of the task to trace (current) | |
3224 | * | |
3225 | * Performs various types of tracing on syscall entry. This includes seccomp, | |
3226 | * ptrace, syscall tracepoints and audit. | |
3227 | * | |
3228 | * The pt_regs are potentially visible to userspace via ptrace, so their | |
3229 | * contents is ABI. | |
3230 | * | |
3231 | * One or more of the tracers may modify the contents of pt_regs, in particular | |
3232 | * to modify arguments or even the syscall number itself. | |
3233 | * | |
3234 | * It's also possible that a tracer can choose to reject the system call. In | |
3235 | * that case this function will return an illegal syscall number, and will put | |
3236 | * an appropriate return value in regs->r3. | |
3237 | * | |
3238 | * Return: the (possibly changed) syscall number. | |
4f72c427 RM |
3239 | */ |
3240 | long do_syscall_trace_enter(struct pt_regs *regs) | |
1da177e4 | 3241 | { |
22ecbe8d LZ |
3242 | user_exit(); |
3243 | ||
1addc57e KC |
3244 | /* |
3245 | * The tracer may decide to abort the syscall, if so tracehook | |
3246 | * will return !0. Note that the tracer may also just change | |
3247 | * regs->gpr[0] to an invalid syscall number, that is handled | |
3248 | * below on the exit path. | |
3249 | */ | |
3250 | if (test_thread_flag(TIF_SYSCALL_TRACE) && | |
3251 | tracehook_report_syscall_entry(regs)) | |
3252 | goto skip; | |
3253 | ||
3254 | /* Run seccomp after ptrace; allow it to set gpr[3]. */ | |
2449acc5 ME |
3255 | if (do_seccomp(regs)) |
3256 | return -1; | |
e8a30302 | 3257 | |
1addc57e KC |
3258 | /* Avoid trace and audit when syscall is invalid. */ |
3259 | if (regs->gpr[0] >= NR_syscalls) | |
3260 | goto skip; | |
ea9c102c | 3261 | |
02424d89 IM |
3262 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
3263 | trace_sys_enter(regs, regs->gpr[0]); | |
3264 | ||
cfcd1705 | 3265 | #ifdef CONFIG_PPC64 |
b05d8447 | 3266 | if (!is_32bit_task()) |
91397401 | 3267 | audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4], |
b05d8447 EP |
3268 | regs->gpr[5], regs->gpr[6]); |
3269 | else | |
e8a30302 | 3270 | #endif |
91397401 | 3271 | audit_syscall_entry(regs->gpr[0], |
b05d8447 EP |
3272 | regs->gpr[3] & 0xffffffff, |
3273 | regs->gpr[4] & 0xffffffff, | |
3274 | regs->gpr[5] & 0xffffffff, | |
3275 | regs->gpr[6] & 0xffffffff); | |
4f72c427 | 3276 | |
d3837414 ME |
3277 | /* Return the possibly modified but valid syscall number */ |
3278 | return regs->gpr[0]; | |
1addc57e KC |
3279 | |
3280 | skip: | |
3281 | /* | |
3282 | * If we are aborting explicitly, or if the syscall number is | |
3283 | * now invalid, set the return value to -ENOSYS. | |
3284 | */ | |
3285 | regs->gpr[3] = -ENOSYS; | |
3286 | return -1; | |
ea9c102c DW |
3287 | } |
3288 | ||
3289 | void do_syscall_trace_leave(struct pt_regs *regs) | |
3290 | { | |
4f72c427 RM |
3291 | int step; |
3292 | ||
d7e7528b | 3293 | audit_syscall_exit(regs); |
ea9c102c | 3294 | |
02424d89 IM |
3295 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
3296 | trace_sys_exit(regs, regs->result); | |
3297 | ||
4f72c427 RM |
3298 | step = test_thread_flag(TIF_SINGLESTEP); |
3299 | if (step || test_thread_flag(TIF_SYSCALL_TRACE)) | |
3300 | tracehook_report_syscall_exit(regs, step); | |
22ecbe8d LZ |
3301 | |
3302 | user_enter(); | |
ea9c102c | 3303 | } |