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14cf11af | 1 | /* |
14cf11af | 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
fe04b112 | 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
14cf11af PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
11 | * and Paul Mackerras (paulus@samba.org) | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This file handles the architecture-dependent parts of hardware exceptions | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/stddef.h> | |
23 | #include <linux/unistd.h> | |
8dad3f92 | 24 | #include <linux/ptrace.h> |
14cf11af | 25 | #include <linux/user.h> |
14cf11af | 26 | #include <linux/interrupt.h> |
14cf11af PM |
27 | #include <linux/init.h> |
28 | #include <linux/module.h> | |
8dad3f92 | 29 | #include <linux/prctl.h> |
14cf11af PM |
30 | #include <linux/delay.h> |
31 | #include <linux/kprobes.h> | |
cc532915 | 32 | #include <linux/kexec.h> |
5474c120 | 33 | #include <linux/backlight.h> |
73c9ceab | 34 | #include <linux/bug.h> |
1eeb66a1 | 35 | #include <linux/kdebug.h> |
80947e7c | 36 | #include <linux/debugfs.h> |
76462232 | 37 | #include <linux/ratelimit.h> |
14cf11af | 38 | |
80947e7c | 39 | #include <asm/emulated_ops.h> |
14cf11af PM |
40 | #include <asm/pgtable.h> |
41 | #include <asm/uaccess.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/io.h> | |
86417780 PM |
44 | #include <asm/machdep.h> |
45 | #include <asm/rtas.h> | |
f7f6f4fe | 46 | #include <asm/pmc.h> |
dc1c1ca3 | 47 | #ifdef CONFIG_PPC32 |
14cf11af | 48 | #include <asm/reg.h> |
86417780 | 49 | #endif |
14cf11af PM |
50 | #ifdef CONFIG_PMAC_BACKLIGHT |
51 | #include <asm/backlight.h> | |
52 | #endif | |
dc1c1ca3 | 53 | #ifdef CONFIG_PPC64 |
86417780 | 54 | #include <asm/firmware.h> |
dc1c1ca3 | 55 | #include <asm/processor.h> |
dc1c1ca3 | 56 | #endif |
c0ce7d08 | 57 | #include <asm/kexec.h> |
16c57b36 | 58 | #include <asm/ppc-opcode.h> |
cce1f106 | 59 | #include <asm/rio.h> |
dc1c1ca3 | 60 | |
7dbb922c | 61 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
5be3492f AB |
62 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
63 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
64 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
65 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
66 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
67 | int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly; | |
68 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; | |
14cf11af PM |
69 | |
70 | EXPORT_SYMBOL(__debugger); | |
71 | EXPORT_SYMBOL(__debugger_ipi); | |
72 | EXPORT_SYMBOL(__debugger_bpt); | |
73 | EXPORT_SYMBOL(__debugger_sstep); | |
74 | EXPORT_SYMBOL(__debugger_iabr_match); | |
75 | EXPORT_SYMBOL(__debugger_dabr_match); | |
76 | EXPORT_SYMBOL(__debugger_fault_handler); | |
77 | #endif | |
78 | ||
14cf11af PM |
79 | /* |
80 | * Trap & Exception support | |
81 | */ | |
82 | ||
6031d9d9 | 83 | #ifdef CONFIG_PMAC_BACKLIGHT |
84 | static void pmac_backlight_unblank(void) | |
85 | { | |
86 | mutex_lock(&pmac_backlight_mutex); | |
87 | if (pmac_backlight) { | |
88 | struct backlight_properties *props; | |
89 | ||
90 | props = &pmac_backlight->props; | |
91 | props->brightness = props->max_brightness; | |
92 | props->power = FB_BLANK_UNBLANK; | |
93 | backlight_update_status(pmac_backlight); | |
94 | } | |
95 | mutex_unlock(&pmac_backlight_mutex); | |
96 | } | |
97 | #else | |
98 | static inline void pmac_backlight_unblank(void) { } | |
99 | #endif | |
100 | ||
760ca4dc AB |
101 | static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
102 | static int die_owner = -1; | |
103 | static unsigned int die_nest_count; | |
104 | static int die_counter; | |
105 | ||
106 | static unsigned __kprobes long oops_begin(struct pt_regs *regs) | |
14cf11af | 107 | { |
760ca4dc | 108 | int cpu; |
34c2a14f | 109 | unsigned long flags; |
14cf11af PM |
110 | |
111 | if (debugger(regs)) | |
112 | return 1; | |
113 | ||
293e4688 | 114 | oops_enter(); |
115 | ||
760ca4dc AB |
116 | /* racy, but better than risking deadlock. */ |
117 | raw_local_irq_save(flags); | |
118 | cpu = smp_processor_id(); | |
119 | if (!arch_spin_trylock(&die_lock)) { | |
120 | if (cpu == die_owner) | |
121 | /* nested oops. should stop eventually */; | |
122 | else | |
123 | arch_spin_lock(&die_lock); | |
34c2a14f | 124 | } |
760ca4dc AB |
125 | die_nest_count++; |
126 | die_owner = cpu; | |
127 | console_verbose(); | |
128 | bust_spinlocks(1); | |
129 | if (machine_is(powermac)) | |
130 | pmac_backlight_unblank(); | |
131 | return flags; | |
132 | } | |
e8222502 | 133 | |
760ca4dc AB |
134 | static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, |
135 | int signr) | |
136 | { | |
14cf11af | 137 | bust_spinlocks(0); |
760ca4dc | 138 | die_owner = -1; |
bcdcd8e7 | 139 | add_taint(TAINT_DIE); |
760ca4dc | 140 | die_nest_count--; |
58154c8c AB |
141 | oops_exit(); |
142 | printk("\n"); | |
760ca4dc AB |
143 | if (!die_nest_count) |
144 | /* Nest count reaches zero, release the lock. */ | |
145 | arch_spin_unlock(&die_lock); | |
146 | raw_local_irq_restore(flags); | |
cc532915 | 147 | |
9b00ac06 AB |
148 | /* |
149 | * A system reset (0x100) is a request to dump, so we always send | |
150 | * it through the crashdump code. | |
151 | */ | |
152 | if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { | |
cc532915 | 153 | crash_kexec(regs); |
9b00ac06 AB |
154 | |
155 | /* | |
156 | * We aren't the primary crash CPU. We need to send it | |
157 | * to a holding pattern to avoid it ending up in the panic | |
158 | * code. | |
159 | */ | |
160 | crash_kexec_secondary(regs); | |
161 | } | |
14cf11af | 162 | |
760ca4dc AB |
163 | if (!signr) |
164 | return; | |
165 | ||
58154c8c AB |
166 | /* |
167 | * While our oops output is serialised by a spinlock, output | |
168 | * from panic() called below can race and corrupt it. If we | |
169 | * know we are going to panic, delay for 1 second so we have a | |
170 | * chance to get clean backtraces from all CPUs that are oopsing. | |
171 | */ | |
172 | if (in_interrupt() || panic_on_oops || !current->pid || | |
173 | is_global_init(current)) { | |
174 | mdelay(MSEC_PER_SEC); | |
175 | } | |
176 | ||
14cf11af PM |
177 | if (in_interrupt()) |
178 | panic("Fatal exception in interrupt"); | |
cea6a4ba | 179 | if (panic_on_oops) |
012c437d | 180 | panic("Fatal exception"); |
760ca4dc AB |
181 | do_exit(signr); |
182 | } | |
cea6a4ba | 183 | |
760ca4dc AB |
184 | static int __kprobes __die(const char *str, struct pt_regs *regs, long err) |
185 | { | |
186 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
187 | #ifdef CONFIG_PREEMPT | |
188 | printk("PREEMPT "); | |
189 | #endif | |
190 | #ifdef CONFIG_SMP | |
191 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
192 | #endif | |
193 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
194 | printk("DEBUG_PAGEALLOC "); | |
195 | #endif | |
196 | #ifdef CONFIG_NUMA | |
197 | printk("NUMA "); | |
198 | #endif | |
199 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); | |
200 | ||
201 | if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) | |
202 | return 1; | |
203 | ||
204 | print_modules(); | |
205 | show_regs(regs); | |
14cf11af PM |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
760ca4dc AB |
210 | void die(const char *str, struct pt_regs *regs, long err) |
211 | { | |
212 | unsigned long flags = oops_begin(regs); | |
213 | ||
214 | if (__die(str, regs, err)) | |
215 | err = 0; | |
216 | oops_end(flags, regs, err); | |
217 | } | |
218 | ||
25baa35b ON |
219 | void user_single_step_siginfo(struct task_struct *tsk, |
220 | struct pt_regs *regs, siginfo_t *info) | |
221 | { | |
222 | memset(info, 0, sizeof(*info)); | |
223 | info->si_signo = SIGTRAP; | |
224 | info->si_code = TRAP_TRACE; | |
225 | info->si_addr = (void __user *)regs->nip; | |
226 | } | |
227 | ||
14cf11af PM |
228 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
229 | { | |
230 | siginfo_t info; | |
d0c3d534 OJ |
231 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
232 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
233 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
234 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
235 | |
236 | if (!user_mode(regs)) { | |
760ca4dc AB |
237 | die("Exception in kernel mode", regs, signr); |
238 | return; | |
239 | } | |
240 | ||
241 | if (show_unhandled_signals && unhandled_signal(current, signr)) { | |
76462232 CD |
242 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
243 | current->comm, current->pid, signr, | |
244 | addr, regs->nip, regs->link, code); | |
245 | } | |
14cf11af PM |
246 | |
247 | memset(&info, 0, sizeof(info)); | |
248 | info.si_signo = signr; | |
249 | info.si_code = code; | |
250 | info.si_addr = (void __user *) addr; | |
251 | force_sig_info(signr, &info, current); | |
14cf11af PM |
252 | } |
253 | ||
254 | #ifdef CONFIG_PPC64 | |
255 | void system_reset_exception(struct pt_regs *regs) | |
256 | { | |
257 | /* See if any machine dependent calls */ | |
c902be71 AB |
258 | if (ppc_md.system_reset_exception) { |
259 | if (ppc_md.system_reset_exception(regs)) | |
260 | return; | |
261 | } | |
14cf11af | 262 | |
8dad3f92 | 263 | die("System Reset", regs, SIGABRT); |
14cf11af PM |
264 | |
265 | /* Must die if the interrupt is not recoverable */ | |
266 | if (!(regs->msr & MSR_RI)) | |
267 | panic("Unrecoverable System Reset"); | |
268 | ||
269 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
270 | } | |
271 | #endif | |
272 | ||
273 | /* | |
274 | * I/O accesses can cause machine checks on powermacs. | |
275 | * Check if the NIP corresponds to the address of a sync | |
276 | * instruction for which there is an entry in the exception | |
277 | * table. | |
278 | * Note that the 601 only takes a machine check on TEA | |
279 | * (transfer error ack) signal assertion, and does not | |
280 | * set any of the top 16 bits of SRR1. | |
281 | * -- paulus. | |
282 | */ | |
283 | static inline int check_io_access(struct pt_regs *regs) | |
284 | { | |
68a64357 | 285 | #ifdef CONFIG_PPC32 |
14cf11af PM |
286 | unsigned long msr = regs->msr; |
287 | const struct exception_table_entry *entry; | |
288 | unsigned int *nip = (unsigned int *)regs->nip; | |
289 | ||
290 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
291 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
292 | /* | |
293 | * Check that it's a sync instruction, or somewhere | |
294 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
295 | * As the address is in the exception table | |
296 | * we should be able to read the instr there. | |
297 | * For the debug message, we look at the preceding | |
298 | * load or store. | |
299 | */ | |
300 | if (*nip == 0x60000000) /* nop */ | |
301 | nip -= 2; | |
302 | else if (*nip == 0x4c00012c) /* isync */ | |
303 | --nip; | |
304 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
305 | /* sync or twi */ | |
306 | unsigned int rb; | |
307 | ||
308 | --nip; | |
309 | rb = (*nip >> 11) & 0x1f; | |
310 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
311 | (*nip & 0x100)? "OUT to": "IN from", | |
312 | regs->gpr[rb] - _IO_BASE, nip); | |
313 | regs->msr |= MSR_RI; | |
314 | regs->nip = entry->fixup; | |
315 | return 1; | |
316 | } | |
317 | } | |
68a64357 | 318 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
319 | return 0; |
320 | } | |
321 | ||
172ae2e7 | 322 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
323 | /* On 4xx, the reason for the machine check or program exception |
324 | is in the ESR. */ | |
325 | #define get_reason(regs) ((regs)->dsisr) | |
326 | #ifndef CONFIG_FSL_BOOKE | |
327 | #define get_mc_reason(regs) ((regs)->dsisr) | |
328 | #else | |
fe04b112 | 329 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) |
14cf11af PM |
330 | #endif |
331 | #define REASON_FP ESR_FP | |
332 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
333 | #define REASON_PRIVILEGED ESR_PPR | |
334 | #define REASON_TRAP ESR_PTR | |
335 | ||
336 | /* single-step stuff */ | |
337 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
338 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
339 | ||
340 | #else | |
341 | /* On non-4xx, the reason for the machine check or program | |
342 | exception is in the MSR. */ | |
343 | #define get_reason(regs) ((regs)->msr) | |
344 | #define get_mc_reason(regs) ((regs)->msr) | |
345 | #define REASON_FP 0x100000 | |
346 | #define REASON_ILLEGAL 0x80000 | |
347 | #define REASON_PRIVILEGED 0x40000 | |
348 | #define REASON_TRAP 0x20000 | |
349 | ||
350 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
351 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
352 | #endif | |
353 | ||
47c0bd1a BH |
354 | #if defined(CONFIG_4xx) |
355 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 356 | { |
1a6a4ffe | 357 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 358 | |
14cf11af PM |
359 | if (reason & ESR_IMCP) { |
360 | printk("Instruction"); | |
361 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
362 | } else | |
363 | printk("Data"); | |
364 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
365 | |
366 | return 0; | |
367 | } | |
368 | ||
369 | int machine_check_440A(struct pt_regs *regs) | |
370 | { | |
371 | unsigned long reason = get_mc_reason(regs); | |
372 | ||
14cf11af PM |
373 | printk("Machine check in kernel mode.\n"); |
374 | if (reason & ESR_IMCP){ | |
375 | printk("Instruction Synchronous Machine Check exception\n"); | |
376 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
377 | } | |
378 | else { | |
379 | u32 mcsr = mfspr(SPRN_MCSR); | |
380 | if (mcsr & MCSR_IB) | |
381 | printk("Instruction Read PLB Error\n"); | |
382 | if (mcsr & MCSR_DRB) | |
383 | printk("Data Read PLB Error\n"); | |
384 | if (mcsr & MCSR_DWB) | |
385 | printk("Data Write PLB Error\n"); | |
386 | if (mcsr & MCSR_TLBP) | |
387 | printk("TLB Parity Error\n"); | |
388 | if (mcsr & MCSR_ICP){ | |
389 | flush_instruction_cache(); | |
390 | printk("I-Cache Parity Error\n"); | |
391 | } | |
392 | if (mcsr & MCSR_DCSP) | |
393 | printk("D-Cache Search Parity Error\n"); | |
394 | if (mcsr & MCSR_DCFP) | |
395 | printk("D-Cache Flush Parity Error\n"); | |
396 | if (mcsr & MCSR_IMPE) | |
397 | printk("Machine Check exception is imprecise\n"); | |
398 | ||
399 | /* Clear MCSR */ | |
400 | mtspr(SPRN_MCSR, mcsr); | |
401 | } | |
47c0bd1a BH |
402 | return 0; |
403 | } | |
fc5e7097 DK |
404 | |
405 | int machine_check_47x(struct pt_regs *regs) | |
406 | { | |
407 | unsigned long reason = get_mc_reason(regs); | |
408 | u32 mcsr; | |
409 | ||
410 | printk(KERN_ERR "Machine check in kernel mode.\n"); | |
411 | if (reason & ESR_IMCP) { | |
412 | printk(KERN_ERR | |
413 | "Instruction Synchronous Machine Check exception\n"); | |
414 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
415 | return 0; | |
416 | } | |
417 | mcsr = mfspr(SPRN_MCSR); | |
418 | if (mcsr & MCSR_IB) | |
419 | printk(KERN_ERR "Instruction Read PLB Error\n"); | |
420 | if (mcsr & MCSR_DRB) | |
421 | printk(KERN_ERR "Data Read PLB Error\n"); | |
422 | if (mcsr & MCSR_DWB) | |
423 | printk(KERN_ERR "Data Write PLB Error\n"); | |
424 | if (mcsr & MCSR_TLBP) | |
425 | printk(KERN_ERR "TLB Parity Error\n"); | |
426 | if (mcsr & MCSR_ICP) { | |
427 | flush_instruction_cache(); | |
428 | printk(KERN_ERR "I-Cache Parity Error\n"); | |
429 | } | |
430 | if (mcsr & MCSR_DCSP) | |
431 | printk(KERN_ERR "D-Cache Search Parity Error\n"); | |
432 | if (mcsr & PPC47x_MCSR_GPR) | |
433 | printk(KERN_ERR "GPR Parity Error\n"); | |
434 | if (mcsr & PPC47x_MCSR_FPR) | |
435 | printk(KERN_ERR "FPR Parity Error\n"); | |
436 | if (mcsr & PPC47x_MCSR_IPR) | |
437 | printk(KERN_ERR "Machine Check exception is imprecise\n"); | |
438 | ||
439 | /* Clear MCSR */ | |
440 | mtspr(SPRN_MCSR, mcsr); | |
441 | ||
442 | return 0; | |
443 | } | |
47c0bd1a | 444 | #elif defined(CONFIG_E500) |
fe04b112 SW |
445 | int machine_check_e500mc(struct pt_regs *regs) |
446 | { | |
447 | unsigned long mcsr = mfspr(SPRN_MCSR); | |
448 | unsigned long reason = mcsr; | |
449 | int recoverable = 1; | |
450 | ||
82a9a480 | 451 | if (reason & MCSR_LD) { |
cce1f106 SX |
452 | recoverable = fsl_rio_mcheck_exception(regs); |
453 | if (recoverable == 1) | |
454 | goto silent_out; | |
455 | } | |
456 | ||
fe04b112 SW |
457 | printk("Machine check in kernel mode.\n"); |
458 | printk("Caused by (from MCSR=%lx): ", reason); | |
459 | ||
460 | if (reason & MCSR_MCP) | |
461 | printk("Machine Check Signal\n"); | |
462 | ||
463 | if (reason & MCSR_ICPERR) { | |
464 | printk("Instruction Cache Parity Error\n"); | |
465 | ||
466 | /* | |
467 | * This is recoverable by invalidating the i-cache. | |
468 | */ | |
469 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); | |
470 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) | |
471 | ; | |
472 | ||
473 | /* | |
474 | * This will generally be accompanied by an instruction | |
475 | * fetch error report -- only treat MCSR_IF as fatal | |
476 | * if it wasn't due to an L1 parity error. | |
477 | */ | |
478 | reason &= ~MCSR_IF; | |
479 | } | |
480 | ||
481 | if (reason & MCSR_DCPERR_MC) { | |
482 | printk("Data Cache Parity Error\n"); | |
37caf9f2 KG |
483 | |
484 | /* | |
485 | * In write shadow mode we auto-recover from the error, but it | |
486 | * may still get logged and cause a machine check. We should | |
487 | * only treat the non-write shadow case as non-recoverable. | |
488 | */ | |
489 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) | |
490 | recoverable = 0; | |
fe04b112 SW |
491 | } |
492 | ||
493 | if (reason & MCSR_L2MMU_MHIT) { | |
494 | printk("Hit on multiple TLB entries\n"); | |
495 | recoverable = 0; | |
496 | } | |
497 | ||
498 | if (reason & MCSR_NMI) | |
499 | printk("Non-maskable interrupt\n"); | |
500 | ||
501 | if (reason & MCSR_IF) { | |
502 | printk("Instruction Fetch Error Report\n"); | |
503 | recoverable = 0; | |
504 | } | |
505 | ||
506 | if (reason & MCSR_LD) { | |
507 | printk("Load Error Report\n"); | |
508 | recoverable = 0; | |
509 | } | |
510 | ||
511 | if (reason & MCSR_ST) { | |
512 | printk("Store Error Report\n"); | |
513 | recoverable = 0; | |
514 | } | |
515 | ||
516 | if (reason & MCSR_LDG) { | |
517 | printk("Guarded Load Error Report\n"); | |
518 | recoverable = 0; | |
519 | } | |
520 | ||
521 | if (reason & MCSR_TLBSYNC) | |
522 | printk("Simultaneous tlbsync operations\n"); | |
523 | ||
524 | if (reason & MCSR_BSL2_ERR) { | |
525 | printk("Level 2 Cache Error\n"); | |
526 | recoverable = 0; | |
527 | } | |
528 | ||
529 | if (reason & MCSR_MAV) { | |
530 | u64 addr; | |
531 | ||
532 | addr = mfspr(SPRN_MCAR); | |
533 | addr |= (u64)mfspr(SPRN_MCARU) << 32; | |
534 | ||
535 | printk("Machine Check %s Address: %#llx\n", | |
536 | reason & MCSR_MEA ? "Effective" : "Physical", addr); | |
537 | } | |
538 | ||
cce1f106 | 539 | silent_out: |
fe04b112 SW |
540 | mtspr(SPRN_MCSR, mcsr); |
541 | return mfspr(SPRN_MCSR) == 0 && recoverable; | |
542 | } | |
543 | ||
47c0bd1a BH |
544 | int machine_check_e500(struct pt_regs *regs) |
545 | { | |
546 | unsigned long reason = get_mc_reason(regs); | |
547 | ||
cce1f106 SX |
548 | if (reason & MCSR_BUS_RBERR) { |
549 | if (fsl_rio_mcheck_exception(regs)) | |
550 | return 1; | |
551 | } | |
552 | ||
14cf11af PM |
553 | printk("Machine check in kernel mode.\n"); |
554 | printk("Caused by (from MCSR=%lx): ", reason); | |
555 | ||
556 | if (reason & MCSR_MCP) | |
557 | printk("Machine Check Signal\n"); | |
558 | if (reason & MCSR_ICPERR) | |
559 | printk("Instruction Cache Parity Error\n"); | |
560 | if (reason & MCSR_DCP_PERR) | |
561 | printk("Data Cache Push Parity Error\n"); | |
562 | if (reason & MCSR_DCPERR) | |
563 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
564 | if (reason & MCSR_BUS_IAERR) |
565 | printk("Bus - Instruction Address Error\n"); | |
566 | if (reason & MCSR_BUS_RAERR) | |
567 | printk("Bus - Read Address Error\n"); | |
568 | if (reason & MCSR_BUS_WAERR) | |
569 | printk("Bus - Write Address Error\n"); | |
570 | if (reason & MCSR_BUS_IBERR) | |
571 | printk("Bus - Instruction Data Error\n"); | |
572 | if (reason & MCSR_BUS_RBERR) | |
573 | printk("Bus - Read Data Bus Error\n"); | |
574 | if (reason & MCSR_BUS_WBERR) | |
575 | printk("Bus - Read Data Bus Error\n"); | |
576 | if (reason & MCSR_BUS_IPERR) | |
577 | printk("Bus - Instruction Parity Error\n"); | |
578 | if (reason & MCSR_BUS_RPERR) | |
579 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
580 | |
581 | return 0; | |
582 | } | |
4490c06b KG |
583 | |
584 | int machine_check_generic(struct pt_regs *regs) | |
585 | { | |
586 | return 0; | |
587 | } | |
47c0bd1a BH |
588 | #elif defined(CONFIG_E200) |
589 | int machine_check_e200(struct pt_regs *regs) | |
590 | { | |
591 | unsigned long reason = get_mc_reason(regs); | |
592 | ||
14cf11af PM |
593 | printk("Machine check in kernel mode.\n"); |
594 | printk("Caused by (from MCSR=%lx): ", reason); | |
595 | ||
596 | if (reason & MCSR_MCP) | |
597 | printk("Machine Check Signal\n"); | |
598 | if (reason & MCSR_CP_PERR) | |
599 | printk("Cache Push Parity Error\n"); | |
600 | if (reason & MCSR_CPERR) | |
601 | printk("Cache Parity Error\n"); | |
602 | if (reason & MCSR_EXCP_ERR) | |
603 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
604 | if (reason & MCSR_BUS_IRERR) | |
605 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
606 | if (reason & MCSR_BUS_DRERR) | |
607 | printk("Bus - Read Bus Error on data load\n"); | |
608 | if (reason & MCSR_BUS_WRERR) | |
609 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
610 | |
611 | return 0; | |
612 | } | |
613 | #else | |
614 | int machine_check_generic(struct pt_regs *regs) | |
615 | { | |
616 | unsigned long reason = get_mc_reason(regs); | |
617 | ||
14cf11af PM |
618 | printk("Machine check in kernel mode.\n"); |
619 | printk("Caused by (from SRR1=%lx): ", reason); | |
620 | switch (reason & 0x601F0000) { | |
621 | case 0x80000: | |
622 | printk("Machine check signal\n"); | |
623 | break; | |
624 | case 0: /* for 601 */ | |
625 | case 0x40000: | |
626 | case 0x140000: /* 7450 MSS error and TEA */ | |
627 | printk("Transfer error ack signal\n"); | |
628 | break; | |
629 | case 0x20000: | |
630 | printk("Data parity error signal\n"); | |
631 | break; | |
632 | case 0x10000: | |
633 | printk("Address parity error signal\n"); | |
634 | break; | |
635 | case 0x20000000: | |
636 | printk("L1 Data Cache error\n"); | |
637 | break; | |
638 | case 0x40000000: | |
639 | printk("L1 Instruction Cache error\n"); | |
640 | break; | |
641 | case 0x00100000: | |
642 | printk("L2 data cache parity error\n"); | |
643 | break; | |
644 | default: | |
645 | printk("Unknown values in msr\n"); | |
646 | } | |
75918a4b OJ |
647 | return 0; |
648 | } | |
47c0bd1a | 649 | #endif /* everything else */ |
75918a4b OJ |
650 | |
651 | void machine_check_exception(struct pt_regs *regs) | |
652 | { | |
653 | int recover = 0; | |
654 | ||
89713ed1 AB |
655 | __get_cpu_var(irq_stat).mce_exceptions++; |
656 | ||
47c0bd1a BH |
657 | /* See if any machine dependent calls. In theory, we would want |
658 | * to call the CPU first, and call the ppc_md. one if the CPU | |
659 | * one returns a positive number. However there is existing code | |
660 | * that assumes the board gets a first chance, so let's keep it | |
661 | * that way for now and fix things later. --BenH. | |
662 | */ | |
75918a4b OJ |
663 | if (ppc_md.machine_check_exception) |
664 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
665 | else if (cur_cpu_spec->machine_check) |
666 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 667 | |
47c0bd1a | 668 | if (recover > 0) |
75918a4b OJ |
669 | return; |
670 | ||
75918a4b | 671 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) |
47c0bd1a BH |
672 | /* the qspan pci read routines can cause machine checks -- Cort |
673 | * | |
674 | * yuck !!! that totally needs to go away ! There are better ways | |
675 | * to deal with that than having a wart in the mcheck handler. | |
676 | * -- BenH | |
677 | */ | |
75918a4b OJ |
678 | bad_page_fault(regs, regs->dar, SIGBUS); |
679 | return; | |
680 | #endif | |
681 | ||
a443506b | 682 | if (debugger_fault_handler(regs)) |
75918a4b | 683 | return; |
75918a4b OJ |
684 | |
685 | if (check_io_access(regs)) | |
686 | return; | |
687 | ||
8dad3f92 | 688 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
689 | |
690 | /* Must die if the interrupt is not recoverable */ | |
691 | if (!(regs->msr & MSR_RI)) | |
692 | panic("Unrecoverable Machine check"); | |
693 | } | |
694 | ||
695 | void SMIException(struct pt_regs *regs) | |
696 | { | |
697 | die("System Management Interrupt", regs, SIGABRT); | |
698 | } | |
699 | ||
dc1c1ca3 | 700 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
701 | { |
702 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
703 | regs->nip, regs->msr, regs->trap); | |
704 | ||
705 | _exception(SIGTRAP, regs, 0, 0); | |
706 | } | |
707 | ||
dc1c1ca3 | 708 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
709 | { |
710 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
711 | 5, SIGTRAP) == NOTIFY_STOP) | |
712 | return; | |
713 | if (debugger_iabr_match(regs)) | |
714 | return; | |
715 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
716 | } | |
717 | ||
718 | void RunModeException(struct pt_regs *regs) | |
719 | { | |
720 | _exception(SIGTRAP, regs, 0, 0); | |
721 | } | |
722 | ||
8dad3f92 | 723 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af | 724 | { |
2538c2d0 | 725 | clear_single_step(regs); |
14cf11af PM |
726 | |
727 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
728 | 5, SIGTRAP) == NOTIFY_STOP) | |
729 | return; | |
730 | if (debugger_sstep(regs)) | |
731 | return; | |
732 | ||
733 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
734 | } | |
735 | ||
736 | /* | |
737 | * After we have successfully emulated an instruction, we have to | |
738 | * check if the instruction was being single-stepped, and if so, | |
739 | * pretend we got a single-step exception. This was pointed out | |
740 | * by Kumar Gala. -- paulus | |
741 | */ | |
8dad3f92 | 742 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af | 743 | { |
2538c2d0 P |
744 | if (single_stepping(regs)) |
745 | single_step_exception(regs); | |
14cf11af PM |
746 | } |
747 | ||
5fad293b | 748 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 749 | { |
5fad293b | 750 | int ret = 0; |
dc1c1ca3 SR |
751 | |
752 | /* Invalid operation */ | |
753 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 754 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
755 | |
756 | /* Overflow */ | |
757 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 758 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
759 | |
760 | /* Underflow */ | |
761 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 762 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
763 | |
764 | /* Divide by zero */ | |
765 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 766 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
767 | |
768 | /* Inexact result */ | |
769 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
770 | ret = FPE_FLTRES; |
771 | ||
772 | return ret; | |
773 | } | |
774 | ||
775 | static void parse_fpe(struct pt_regs *regs) | |
776 | { | |
777 | int code = 0; | |
778 | ||
779 | flush_fp_to_thread(current); | |
780 | ||
781 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
782 | |
783 | _exception(SIGFPE, regs, code, regs->nip); | |
784 | } | |
785 | ||
786 | /* | |
787 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
788 | * provide the PVR to user applications using the mfspr rd, PVR. |
789 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
790 | * memory access caused an access fault. Return zero on success. | |
791 | * | |
792 | * There are a couple of ways to do this, either "decode" the instruction | |
793 | * or directly match lots of bits. In this case, matching lots of | |
794 | * bits is faster and easier. | |
86417780 | 795 | * |
14cf11af | 796 | */ |
14cf11af PM |
797 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
798 | { | |
799 | u8 rT = (instword >> 21) & 0x1f; | |
800 | u8 rA = (instword >> 16) & 0x1f; | |
801 | u8 NB_RB = (instword >> 11) & 0x1f; | |
802 | u32 num_bytes; | |
803 | unsigned long EA; | |
804 | int pos = 0; | |
805 | ||
806 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 807 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
808 | if ((rT == rA) || (rT == NB_RB)) |
809 | return -EINVAL; | |
810 | ||
811 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
812 | ||
16c57b36 KG |
813 | switch (instword & PPC_INST_STRING_MASK) { |
814 | case PPC_INST_LSWX: | |
815 | case PPC_INST_STSWX: | |
14cf11af PM |
816 | EA += NB_RB; |
817 | num_bytes = regs->xer & 0x7f; | |
818 | break; | |
16c57b36 KG |
819 | case PPC_INST_LSWI: |
820 | case PPC_INST_STSWI: | |
14cf11af PM |
821 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
822 | break; | |
823 | default: | |
824 | return -EINVAL; | |
825 | } | |
826 | ||
827 | while (num_bytes != 0) | |
828 | { | |
829 | u8 val; | |
830 | u32 shift = 8 * (3 - (pos & 0x3)); | |
831 | ||
16c57b36 KG |
832 | switch ((instword & PPC_INST_STRING_MASK)) { |
833 | case PPC_INST_LSWX: | |
834 | case PPC_INST_LSWI: | |
14cf11af PM |
835 | if (get_user(val, (u8 __user *)EA)) |
836 | return -EFAULT; | |
837 | /* first time updating this reg, | |
838 | * zero it out */ | |
839 | if (pos == 0) | |
840 | regs->gpr[rT] = 0; | |
841 | regs->gpr[rT] |= val << shift; | |
842 | break; | |
16c57b36 KG |
843 | case PPC_INST_STSWI: |
844 | case PPC_INST_STSWX: | |
14cf11af PM |
845 | val = regs->gpr[rT] >> shift; |
846 | if (put_user(val, (u8 __user *)EA)) | |
847 | return -EFAULT; | |
848 | break; | |
849 | } | |
850 | /* move EA to next address */ | |
851 | EA += 1; | |
852 | num_bytes--; | |
853 | ||
854 | /* manage our position within the register */ | |
855 | if (++pos == 4) { | |
856 | pos = 0; | |
857 | if (++rT == 32) | |
858 | rT = 0; | |
859 | } | |
860 | } | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
c3412dcb WS |
865 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
866 | { | |
867 | u32 ra,rs; | |
868 | unsigned long tmp; | |
869 | ||
870 | ra = (instword >> 16) & 0x1f; | |
871 | rs = (instword >> 21) & 0x1f; | |
872 | ||
873 | tmp = regs->gpr[rs]; | |
874 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
875 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
876 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
877 | regs->gpr[ra] = tmp; | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
c1469f13 KG |
882 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
883 | { | |
884 | u8 rT = (instword >> 21) & 0x1f; | |
885 | u8 rA = (instword >> 16) & 0x1f; | |
886 | u8 rB = (instword >> 11) & 0x1f; | |
887 | u8 BC = (instword >> 6) & 0x1f; | |
888 | u8 bit; | |
889 | unsigned long tmp; | |
890 | ||
891 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
892 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
893 | ||
894 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
14cf11af PM |
899 | static int emulate_instruction(struct pt_regs *regs) |
900 | { | |
901 | u32 instword; | |
902 | u32 rd; | |
903 | ||
fab5db97 | 904 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
905 | return -EINVAL; |
906 | CHECK_FULL_REGS(regs); | |
907 | ||
908 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
909 | return -EFAULT; | |
910 | ||
911 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 912 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 913 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
914 | rd = (instword >> 21) & 0x1f; |
915 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
916 | return 0; | |
917 | } | |
918 | ||
919 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 920 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 921 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 922 | return 0; |
80947e7c | 923 | } |
14cf11af PM |
924 | |
925 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 926 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 927 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
928 | unsigned long msk = 0xf0000000UL >> shift; |
929 | ||
eecff81d | 930 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
931 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
932 | regs->xer &= ~0xf0000000UL; | |
933 | return 0; | |
934 | } | |
935 | ||
936 | /* Emulate load/store string insn. */ | |
80947e7c | 937 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
eecff81d | 938 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 939 | return emulate_string_inst(regs, instword); |
80947e7c | 940 | } |
14cf11af | 941 | |
c3412dcb | 942 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 943 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 944 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
945 | return emulate_popcntb_inst(regs, instword); |
946 | } | |
947 | ||
c1469f13 | 948 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 949 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 950 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
951 | return emulate_isel(regs, instword); |
952 | } | |
953 | ||
efcac658 AK |
954 | #ifdef CONFIG_PPC64 |
955 | /* Emulate the mfspr rD, DSCR. */ | |
956 | if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) && | |
957 | cpu_has_feature(CPU_FTR_DSCR)) { | |
958 | PPC_WARN_EMULATED(mfdscr, regs); | |
959 | rd = (instword >> 21) & 0x1f; | |
960 | regs->gpr[rd] = mfspr(SPRN_DSCR); | |
961 | return 0; | |
962 | } | |
963 | /* Emulate the mtspr DSCR, rD. */ | |
964 | if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) && | |
965 | cpu_has_feature(CPU_FTR_DSCR)) { | |
966 | PPC_WARN_EMULATED(mtdscr, regs); | |
967 | rd = (instword >> 21) & 0x1f; | |
968 | mtspr(SPRN_DSCR, regs->gpr[rd]); | |
969 | current->thread.dscr_inherit = 1; | |
970 | return 0; | |
971 | } | |
972 | #endif | |
973 | ||
14cf11af PM |
974 | return -EINVAL; |
975 | } | |
976 | ||
73c9ceab | 977 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 978 | { |
73c9ceab | 979 | return is_kernel_addr(addr); |
14cf11af PM |
980 | } |
981 | ||
8dad3f92 | 982 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
983 | { |
984 | unsigned int reason = get_reason(regs); | |
985 | extern int do_mathemu(struct pt_regs *regs); | |
986 | ||
aa42c69c | 987 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 988 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 989 | |
dc1c1ca3 SR |
990 | if (reason & REASON_FP) { |
991 | /* IEEE FP exception */ | |
992 | parse_fpe(regs); | |
8dad3f92 PM |
993 | return; |
994 | } | |
995 | if (reason & REASON_TRAP) { | |
ba797b28 JW |
996 | /* Debugger is first in line to stop recursive faults in |
997 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ | |
998 | if (debugger_bpt(regs)) | |
999 | return; | |
1000 | ||
14cf11af | 1001 | /* trap exception */ |
dc1c1ca3 SR |
1002 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
1003 | == NOTIFY_STOP) | |
1004 | return; | |
73c9ceab JF |
1005 | |
1006 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
608e2619 | 1007 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af PM |
1008 | regs->nip += 4; |
1009 | return; | |
1010 | } | |
8dad3f92 PM |
1011 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
1012 | return; | |
1013 | } | |
1014 | ||
cd8a5673 PM |
1015 | local_irq_enable(); |
1016 | ||
04903a30 KG |
1017 | #ifdef CONFIG_MATH_EMULATION |
1018 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
1019 | * but there seems to be a hardware bug on the 405GP (RevD) | |
1020 | * that means ESR is sometimes set incorrectly - either to | |
1021 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
1022 | * hardware people - not sure if it can happen on any illegal | |
1023 | * instruction or only on FP instructions, whether there is a | |
25985edc | 1024 | * pattern to occurrences etc. -dgibson 31/Mar/2003 */ |
5fad293b KG |
1025 | switch (do_mathemu(regs)) { |
1026 | case 0: | |
04903a30 KG |
1027 | emulate_single_step(regs); |
1028 | return; | |
5fad293b KG |
1029 | case 1: { |
1030 | int code = 0; | |
1031 | code = __parse_fpscr(current->thread.fpscr.val); | |
1032 | _exception(SIGFPE, regs, code, regs->nip); | |
1033 | return; | |
1034 | } | |
1035 | case -EFAULT: | |
1036 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1037 | return; | |
04903a30 | 1038 | } |
5fad293b | 1039 | /* fall through on any other errors */ |
04903a30 KG |
1040 | #endif /* CONFIG_MATH_EMULATION */ |
1041 | ||
8dad3f92 PM |
1042 | /* Try to emulate it if we should. */ |
1043 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
1044 | switch (emulate_instruction(regs)) { |
1045 | case 0: | |
1046 | regs->nip += 4; | |
1047 | emulate_single_step(regs); | |
8dad3f92 | 1048 | return; |
14cf11af PM |
1049 | case -EFAULT: |
1050 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 1051 | return; |
14cf11af PM |
1052 | } |
1053 | } | |
8dad3f92 PM |
1054 | |
1055 | if (reason & REASON_PRIVILEGED) | |
1056 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1057 | else | |
1058 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
1059 | } |
1060 | ||
dc1c1ca3 | 1061 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 1062 | { |
4393c4f6 | 1063 | int sig, code, fixed = 0; |
14cf11af | 1064 | |
e9370ae1 PM |
1065 | /* we don't implement logging of alignment exceptions */ |
1066 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
1067 | fixed = fix_alignment(regs); | |
14cf11af PM |
1068 | |
1069 | if (fixed == 1) { | |
1070 | regs->nip += 4; /* skip over emulated instruction */ | |
1071 | emulate_single_step(regs); | |
1072 | return; | |
1073 | } | |
1074 | ||
dc1c1ca3 | 1075 | /* Operand address was bad */ |
14cf11af | 1076 | if (fixed == -EFAULT) { |
4393c4f6 BH |
1077 | sig = SIGSEGV; |
1078 | code = SEGV_ACCERR; | |
1079 | } else { | |
1080 | sig = SIGBUS; | |
1081 | code = BUS_ADRALN; | |
14cf11af | 1082 | } |
4393c4f6 BH |
1083 | if (user_mode(regs)) |
1084 | _exception(sig, regs, code, regs->dar); | |
1085 | else | |
1086 | bad_page_fault(regs, regs->dar, sig); | |
14cf11af PM |
1087 | } |
1088 | ||
1089 | void StackOverflow(struct pt_regs *regs) | |
1090 | { | |
1091 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
1092 | current, regs->gpr[1]); | |
1093 | debugger(regs); | |
1094 | show_regs(regs); | |
1095 | panic("kernel stack overflow"); | |
1096 | } | |
1097 | ||
1098 | void nonrecoverable_exception(struct pt_regs *regs) | |
1099 | { | |
1100 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
1101 | regs->nip, regs->msr); | |
1102 | debugger(regs); | |
1103 | die("nonrecoverable exception", regs, SIGKILL); | |
1104 | } | |
1105 | ||
1106 | void trace_syscall(struct pt_regs *regs) | |
1107 | { | |
1108 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
19c5870c | 1109 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
14cf11af PM |
1110 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
1111 | } | |
dc1c1ca3 | 1112 | |
dc1c1ca3 SR |
1113 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
1114 | { | |
1115 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
1116 | "%lx at %lx\n", regs->trap, regs->nip); | |
1117 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
1118 | } | |
dc1c1ca3 SR |
1119 | |
1120 | void altivec_unavailable_exception(struct pt_regs *regs) | |
1121 | { | |
dc1c1ca3 SR |
1122 | if (user_mode(regs)) { |
1123 | /* A user program has executed an altivec instruction, | |
1124 | but this kernel doesn't support altivec. */ | |
1125 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1126 | return; | |
1127 | } | |
6c4841c2 | 1128 | |
dc1c1ca3 SR |
1129 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
1130 | "%lx at %lx\n", regs->trap, regs->nip); | |
1131 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
1132 | } |
1133 | ||
ce48b210 MN |
1134 | void vsx_unavailable_exception(struct pt_regs *regs) |
1135 | { | |
1136 | if (user_mode(regs)) { | |
1137 | /* A user program has executed an vsx instruction, | |
1138 | but this kernel doesn't support vsx. */ | |
1139 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1140 | return; | |
1141 | } | |
1142 | ||
1143 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
1144 | "%lx at %lx\n", regs->trap, regs->nip); | |
1145 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
1146 | } | |
1147 | ||
dc1c1ca3 SR |
1148 | void performance_monitor_exception(struct pt_regs *regs) |
1149 | { | |
89713ed1 AB |
1150 | __get_cpu_var(irq_stat).pmu_irqs++; |
1151 | ||
dc1c1ca3 SR |
1152 | perf_irq(regs); |
1153 | } | |
dc1c1ca3 | 1154 | |
8dad3f92 | 1155 | #ifdef CONFIG_8xx |
14cf11af PM |
1156 | void SoftwareEmulation(struct pt_regs *regs) |
1157 | { | |
1158 | extern int do_mathemu(struct pt_regs *); | |
1159 | extern int Soft_emulate_8xx(struct pt_regs *); | |
5dd57a13 | 1160 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1161 | int errcode; |
5dd57a13 | 1162 | #endif |
14cf11af PM |
1163 | |
1164 | CHECK_FULL_REGS(regs); | |
1165 | ||
1166 | if (!user_mode(regs)) { | |
1167 | debugger(regs); | |
1168 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
1169 | } | |
1170 | ||
1171 | #ifdef CONFIG_MATH_EMULATION | |
1172 | errcode = do_mathemu(regs); | |
80947e7c | 1173 | if (errcode >= 0) |
eecff81d | 1174 | PPC_WARN_EMULATED(math, regs); |
5fad293b KG |
1175 | |
1176 | switch (errcode) { | |
1177 | case 0: | |
1178 | emulate_single_step(regs); | |
1179 | return; | |
1180 | case 1: { | |
1181 | int code = 0; | |
1182 | code = __parse_fpscr(current->thread.fpscr.val); | |
1183 | _exception(SIGFPE, regs, code, regs->nip); | |
1184 | return; | |
1185 | } | |
1186 | case -EFAULT: | |
1187 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1188 | return; | |
1189 | default: | |
1190 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1191 | return; | |
1192 | } | |
1193 | ||
5dd57a13 | 1194 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1195 | errcode = Soft_emulate_8xx(regs); |
80947e7c | 1196 | if (errcode >= 0) |
eecff81d | 1197 | PPC_WARN_EMULATED(8xx, regs); |
80947e7c | 1198 | |
5fad293b KG |
1199 | switch (errcode) { |
1200 | case 0: | |
14cf11af | 1201 | emulate_single_step(regs); |
5fad293b KG |
1202 | return; |
1203 | case 1: | |
1204 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1205 | return; | |
1206 | case -EFAULT: | |
1207 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1208 | return; | |
1209 | } | |
5dd57a13 SW |
1210 | #else |
1211 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
5fad293b | 1212 | #endif |
14cf11af | 1213 | } |
8dad3f92 | 1214 | #endif /* CONFIG_8xx */ |
14cf11af | 1215 | |
172ae2e7 | 1216 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1217 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1218 | { | |
1219 | int changed = 0; | |
1220 | /* | |
1221 | * Determine the cause of the debug event, clear the | |
1222 | * event flags and send a trap to the handler. Torez | |
1223 | */ | |
1224 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1225 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1226 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1227 | current->thread.dbcr2 &= ~DBCR2_DAC12MODE; | |
1228 | #endif | |
1229 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, | |
1230 | 5); | |
1231 | changed |= 0x01; | |
1232 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1233 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
1234 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, | |
1235 | 6); | |
1236 | changed |= 0x01; | |
1237 | } else if (debug_status & DBSR_IAC1) { | |
1238 | current->thread.dbcr0 &= ~DBCR0_IAC1; | |
1239 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; | |
1240 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, | |
1241 | 1); | |
1242 | changed |= 0x01; | |
1243 | } else if (debug_status & DBSR_IAC2) { | |
1244 | current->thread.dbcr0 &= ~DBCR0_IAC2; | |
1245 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, | |
1246 | 2); | |
1247 | changed |= 0x01; | |
1248 | } else if (debug_status & DBSR_IAC3) { | |
1249 | current->thread.dbcr0 &= ~DBCR0_IAC3; | |
1250 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; | |
1251 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, | |
1252 | 3); | |
1253 | changed |= 0x01; | |
1254 | } else if (debug_status & DBSR_IAC4) { | |
1255 | current->thread.dbcr0 &= ~DBCR0_IAC4; | |
1256 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, | |
1257 | 4); | |
1258 | changed |= 0x01; | |
1259 | } | |
1260 | /* | |
1261 | * At the point this routine was called, the MSR(DE) was turned off. | |
1262 | * Check all other debug flags and see if that bit needs to be turned | |
1263 | * back on or not. | |
1264 | */ | |
1265 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) | |
1266 | regs->msr |= MSR_DE; | |
1267 | else | |
1268 | /* Make sure the IDM flag is off */ | |
1269 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
1270 | ||
1271 | if (changed & 0x01) | |
1272 | mtspr(SPRN_DBCR0, current->thread.dbcr0); | |
1273 | } | |
14cf11af | 1274 | |
f8279621 | 1275 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1276 | { |
3bffb652 DK |
1277 | current->thread.dbsr = debug_status; |
1278 | ||
ec097c84 RM |
1279 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1280 | * on server, it stops on the target of the branch. In order to simulate | |
1281 | * the server behaviour, we thus restart right away with a single step | |
1282 | * instead of stopping here when hitting a BT | |
1283 | */ | |
1284 | if (debug_status & DBSR_BT) { | |
1285 | regs->msr &= ~MSR_DE; | |
1286 | ||
1287 | /* Disable BT */ | |
1288 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1289 | /* Clear the BT event */ | |
1290 | mtspr(SPRN_DBSR, DBSR_BT); | |
1291 | ||
1292 | /* Do the single step trick only when coming from userspace */ | |
1293 | if (user_mode(regs)) { | |
1294 | current->thread.dbcr0 &= ~DBCR0_BT; | |
1295 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
1296 | regs->msr |= MSR_DE; | |
1297 | return; | |
1298 | } | |
1299 | ||
1300 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, | |
1301 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1302 | return; | |
1303 | } | |
1304 | if (debugger_sstep(regs)) | |
1305 | return; | |
1306 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1307 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1308 | |
1309 | /* Disable instruction completion */ | |
1310 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1311 | /* Clear the instruction completion event */ | |
1312 | mtspr(SPRN_DBSR, DBSR_IC); | |
1313 | ||
1314 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
1315 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1316 | return; | |
1317 | } | |
1318 | ||
1319 | if (debugger_sstep(regs)) | |
1320 | return; | |
1321 | ||
d6a61bfc | 1322 | if (user_mode(regs)) { |
3bffb652 | 1323 | current->thread.dbcr0 &= ~DBCR0_IC; |
3bffb652 DK |
1324 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, |
1325 | current->thread.dbcr1)) | |
1326 | regs->msr |= MSR_DE; | |
1327 | else | |
1328 | /* Make sure the IDM bit is off */ | |
1329 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
d6a61bfc | 1330 | } |
3bffb652 DK |
1331 | |
1332 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1333 | } else | |
1334 | handle_debug(regs, debug_status); | |
14cf11af | 1335 | } |
172ae2e7 | 1336 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1337 | |
1338 | #if !defined(CONFIG_TAU_INT) | |
1339 | void TAUException(struct pt_regs *regs) | |
1340 | { | |
1341 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1342 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1343 | } | |
1344 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1345 | |
1346 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1347 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1348 | { |
1349 | int err; | |
1350 | ||
14cf11af PM |
1351 | if (!user_mode(regs)) { |
1352 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1353 | " at %lx\n", regs->nip); | |
8dad3f92 | 1354 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1355 | } |
1356 | ||
dc1c1ca3 | 1357 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1358 | |
eecff81d | 1359 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1360 | err = emulate_altivec(regs); |
1361 | if (err == 0) { | |
1362 | regs->nip += 4; /* skip emulated instruction */ | |
1363 | emulate_single_step(regs); | |
1364 | return; | |
1365 | } | |
1366 | ||
1367 | if (err == -EFAULT) { | |
1368 | /* got an error reading the instruction */ | |
1369 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1370 | } else { | |
1371 | /* didn't recognize the instruction */ | |
1372 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
76462232 CD |
1373 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
1374 | "in %s at %lx\n", current->comm, regs->nip); | |
14cf11af PM |
1375 | current->thread.vscr.u[3] |= 0x10000; |
1376 | } | |
1377 | } | |
1378 | #endif /* CONFIG_ALTIVEC */ | |
1379 | ||
ce48b210 MN |
1380 | #ifdef CONFIG_VSX |
1381 | void vsx_assist_exception(struct pt_regs *regs) | |
1382 | { | |
1383 | if (!user_mode(regs)) { | |
1384 | printk(KERN_EMERG "VSX assist exception in kernel mode" | |
1385 | " at %lx\n", regs->nip); | |
1386 | die("Kernel VSX assist exception", regs, SIGILL); | |
1387 | } | |
1388 | ||
1389 | flush_vsx_to_thread(current); | |
1390 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); | |
1391 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1392 | } | |
1393 | #endif /* CONFIG_VSX */ | |
1394 | ||
14cf11af PM |
1395 | #ifdef CONFIG_FSL_BOOKE |
1396 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1397 | unsigned long error_code) | |
1398 | { | |
1399 | /* We treat cache locking instructions from the user | |
1400 | * as priv ops, in the future we could try to do | |
1401 | * something smarter | |
1402 | */ | |
1403 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1404 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1405 | return; | |
1406 | } | |
1407 | #endif /* CONFIG_FSL_BOOKE */ | |
1408 | ||
1409 | #ifdef CONFIG_SPE | |
1410 | void SPEFloatingPointException(struct pt_regs *regs) | |
1411 | { | |
6a800f36 | 1412 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1413 | unsigned long spefscr; |
1414 | int fpexc_mode; | |
1415 | int code = 0; | |
6a800f36 LY |
1416 | int err; |
1417 | ||
685659ee | 1418 | flush_spe_to_thread(current); |
14cf11af PM |
1419 | |
1420 | spefscr = current->thread.spefscr; | |
1421 | fpexc_mode = current->thread.fpexc_mode; | |
1422 | ||
14cf11af PM |
1423 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1424 | code = FPE_FLTOVF; | |
14cf11af PM |
1425 | } |
1426 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1427 | code = FPE_FLTUND; | |
14cf11af PM |
1428 | } |
1429 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1430 | code = FPE_FLTDIV; | |
1431 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1432 | code = FPE_FLTINV; | |
14cf11af PM |
1433 | } |
1434 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1435 | code = FPE_FLTRES; | |
1436 | ||
6a800f36 LY |
1437 | err = do_spe_mathemu(regs); |
1438 | if (err == 0) { | |
1439 | regs->nip += 4; /* skip emulated instruction */ | |
1440 | emulate_single_step(regs); | |
1441 | return; | |
1442 | } | |
1443 | ||
1444 | if (err == -EFAULT) { | |
1445 | /* got an error reading the instruction */ | |
1446 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1447 | } else if (err == -EINVAL) { | |
1448 | /* didn't recognize the instruction */ | |
1449 | printk(KERN_ERR "unrecognized spe instruction " | |
1450 | "in %s at %lx\n", current->comm, regs->nip); | |
1451 | } else { | |
1452 | _exception(SIGFPE, regs, code, regs->nip); | |
1453 | } | |
14cf11af | 1454 | |
14cf11af PM |
1455 | return; |
1456 | } | |
6a800f36 LY |
1457 | |
1458 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1459 | { | |
1460 | extern int speround_handler(struct pt_regs *regs); | |
1461 | int err; | |
1462 | ||
1463 | preempt_disable(); | |
1464 | if (regs->msr & MSR_SPE) | |
1465 | giveup_spe(current); | |
1466 | preempt_enable(); | |
1467 | ||
1468 | regs->nip -= 4; | |
1469 | err = speround_handler(regs); | |
1470 | if (err == 0) { | |
1471 | regs->nip += 4; /* skip emulated instruction */ | |
1472 | emulate_single_step(regs); | |
1473 | return; | |
1474 | } | |
1475 | ||
1476 | if (err == -EFAULT) { | |
1477 | /* got an error reading the instruction */ | |
1478 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1479 | } else if (err == -EINVAL) { | |
1480 | /* didn't recognize the instruction */ | |
1481 | printk(KERN_ERR "unrecognized spe instruction " | |
1482 | "in %s at %lx\n", current->comm, regs->nip); | |
1483 | } else { | |
1484 | _exception(SIGFPE, regs, 0, regs->nip); | |
1485 | return; | |
1486 | } | |
1487 | } | |
14cf11af PM |
1488 | #endif |
1489 | ||
dc1c1ca3 SR |
1490 | /* |
1491 | * We enter here if we get an unrecoverable exception, that is, one | |
1492 | * that happened at a point where the RI (recoverable interrupt) bit | |
1493 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1494 | * we therefore lost state by taking this exception. | |
1495 | */ | |
1496 | void unrecoverable_exception(struct pt_regs *regs) | |
1497 | { | |
1498 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1499 | regs->trap, regs->nip); | |
1500 | die("Unrecoverable exception", regs, SIGABRT); | |
1501 | } | |
dc1c1ca3 | 1502 | |
14cf11af PM |
1503 | #ifdef CONFIG_BOOKE_WDT |
1504 | /* | |
1505 | * Default handler for a Watchdog exception, | |
1506 | * spins until a reboot occurs | |
1507 | */ | |
1508 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1509 | { | |
1510 | /* Generic WatchdogHandler, implement your own */ | |
1511 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1512 | return; | |
1513 | } | |
1514 | ||
1515 | void WatchdogException(struct pt_regs *regs) | |
1516 | { | |
1517 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1518 | WatchdogHandler(regs); | |
1519 | } | |
1520 | #endif | |
dc1c1ca3 | 1521 | |
dc1c1ca3 SR |
1522 | /* |
1523 | * We enter here if we discover during exception entry that we are | |
1524 | * running in supervisor mode with a userspace value in the stack pointer. | |
1525 | */ | |
1526 | void kernel_bad_stack(struct pt_regs *regs) | |
1527 | { | |
1528 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1529 | regs->gpr[1], regs->nip); | |
1530 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1531 | } | |
14cf11af PM |
1532 | |
1533 | void __init trap_init(void) | |
1534 | { | |
1535 | } | |
80947e7c GU |
1536 | |
1537 | ||
1538 | #ifdef CONFIG_PPC_EMULATED_STATS | |
1539 | ||
1540 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
1541 | ||
1542 | struct ppc_emulated ppc_emulated = { | |
1543 | #ifdef CONFIG_ALTIVEC | |
1544 | WARN_EMULATED_SETUP(altivec), | |
1545 | #endif | |
1546 | WARN_EMULATED_SETUP(dcba), | |
1547 | WARN_EMULATED_SETUP(dcbz), | |
1548 | WARN_EMULATED_SETUP(fp_pair), | |
1549 | WARN_EMULATED_SETUP(isel), | |
1550 | WARN_EMULATED_SETUP(mcrxr), | |
1551 | WARN_EMULATED_SETUP(mfpvr), | |
1552 | WARN_EMULATED_SETUP(multiple), | |
1553 | WARN_EMULATED_SETUP(popcntb), | |
1554 | WARN_EMULATED_SETUP(spe), | |
1555 | WARN_EMULATED_SETUP(string), | |
1556 | WARN_EMULATED_SETUP(unaligned), | |
1557 | #ifdef CONFIG_MATH_EMULATION | |
1558 | WARN_EMULATED_SETUP(math), | |
1559 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | |
1560 | WARN_EMULATED_SETUP(8xx), | |
1561 | #endif | |
1562 | #ifdef CONFIG_VSX | |
1563 | WARN_EMULATED_SETUP(vsx), | |
1564 | #endif | |
efcac658 AK |
1565 | #ifdef CONFIG_PPC64 |
1566 | WARN_EMULATED_SETUP(mfdscr), | |
1567 | WARN_EMULATED_SETUP(mtdscr), | |
1568 | #endif | |
80947e7c GU |
1569 | }; |
1570 | ||
1571 | u32 ppc_warn_emulated; | |
1572 | ||
1573 | void ppc_warn_emulated_print(const char *type) | |
1574 | { | |
76462232 CD |
1575 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
1576 | type); | |
80947e7c GU |
1577 | } |
1578 | ||
1579 | static int __init ppc_warn_emulated_init(void) | |
1580 | { | |
1581 | struct dentry *dir, *d; | |
1582 | unsigned int i; | |
1583 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
1584 | ||
1585 | if (!powerpc_debugfs_root) | |
1586 | return -ENODEV; | |
1587 | ||
1588 | dir = debugfs_create_dir("emulated_instructions", | |
1589 | powerpc_debugfs_root); | |
1590 | if (!dir) | |
1591 | return -ENOMEM; | |
1592 | ||
1593 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
1594 | &ppc_warn_emulated); | |
1595 | if (!d) | |
1596 | goto fail; | |
1597 | ||
1598 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
1599 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
1600 | (u32 *)&entries[i].val.counter); | |
1601 | if (!d) | |
1602 | goto fail; | |
1603 | } | |
1604 | ||
1605 | return 0; | |
1606 | ||
1607 | fail: | |
1608 | debugfs_remove_recursive(dir); | |
1609 | return -ENOMEM; | |
1610 | } | |
1611 | ||
1612 | device_initcall(ppc_warn_emulated_init); | |
1613 | ||
1614 | #endif /* CONFIG_PPC_EMULATED_STATS */ |