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1a472c9d AK |
1 | /* |
2 | * TLB flush routines for radix kernels. | |
3 | * | |
4 | * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/mm.h> | |
13 | #include <linux/hugetlb.h> | |
14 | #include <linux/memblock.h> | |
15 | ||
16 | #include <asm/tlb.h> | |
17 | #include <asm/tlbflush.h> | |
18 | ||
19 | static DEFINE_RAW_SPINLOCK(native_tlbie_lock); | |
20 | ||
36194812 AK |
21 | #define RIC_FLUSH_TLB 0 |
22 | #define RIC_FLUSH_PWC 1 | |
23 | #define RIC_FLUSH_ALL 2 | |
24 | ||
25 | static inline void __tlbiel_pid(unsigned long pid, int set, | |
26 | unsigned long ric) | |
1a472c9d | 27 | { |
36194812 | 28 | unsigned long rb,rs,prs,r; |
1a472c9d AK |
29 | |
30 | rb = PPC_BIT(53); /* IS = 1 */ | |
31 | rb |= set << PPC_BITLSHIFT(51); | |
32 | rs = ((unsigned long)pid) << PPC_BITLSHIFT(31); | |
33 | prs = 1; /* process scoped */ | |
34 | r = 1; /* raidx format */ | |
1a472c9d AK |
35 | |
36 | asm volatile("ptesync": : :"memory"); | |
37 | asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |" | |
38 | "(%2 << 17) | (%3 << 18) | (%4 << 21)" | |
39 | : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); | |
40 | asm volatile("ptesync": : :"memory"); | |
41 | } | |
42 | ||
43 | /* | |
44 | * We use 128 set in radix mode and 256 set in hpt mode. | |
45 | */ | |
36194812 | 46 | static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) |
1a472c9d AK |
47 | { |
48 | int set; | |
49 | ||
50 | for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) { | |
36194812 | 51 | __tlbiel_pid(pid, set, ric); |
1a472c9d AK |
52 | } |
53 | return; | |
54 | } | |
55 | ||
36194812 | 56 | static inline void _tlbie_pid(unsigned long pid, unsigned long ric) |
1a472c9d | 57 | { |
36194812 | 58 | unsigned long rb,rs,prs,r; |
1a472c9d AK |
59 | |
60 | rb = PPC_BIT(53); /* IS = 1 */ | |
61 | rs = pid << PPC_BITLSHIFT(31); | |
62 | prs = 1; /* process scoped */ | |
63 | r = 1; /* raidx format */ | |
1a472c9d AK |
64 | |
65 | asm volatile("ptesync": : :"memory"); | |
66 | asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |" | |
67 | "(%2 << 17) | (%3 << 18) | (%4 << 21)" | |
68 | : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); | |
69 | asm volatile("eieio; tlbsync; ptesync": : :"memory"); | |
70 | } | |
71 | ||
72 | static inline void _tlbiel_va(unsigned long va, unsigned long pid, | |
36194812 | 73 | unsigned long ap, unsigned long ric) |
1a472c9d | 74 | { |
36194812 | 75 | unsigned long rb,rs,prs,r; |
1a472c9d AK |
76 | |
77 | rb = va & ~(PPC_BITMASK(52, 63)); | |
78 | rb |= ap << PPC_BITLSHIFT(58); | |
79 | rs = pid << PPC_BITLSHIFT(31); | |
80 | prs = 1; /* process scoped */ | |
81 | r = 1; /* raidx format */ | |
1a472c9d AK |
82 | |
83 | asm volatile("ptesync": : :"memory"); | |
84 | asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |" | |
85 | "(%2 << 17) | (%3 << 18) | (%4 << 21)" | |
86 | : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); | |
87 | asm volatile("ptesync": : :"memory"); | |
88 | } | |
89 | ||
90 | static inline void _tlbie_va(unsigned long va, unsigned long pid, | |
36194812 | 91 | unsigned long ap, unsigned long ric) |
1a472c9d | 92 | { |
36194812 | 93 | unsigned long rb,rs,prs,r; |
1a472c9d AK |
94 | |
95 | rb = va & ~(PPC_BITMASK(52, 63)); | |
96 | rb |= ap << PPC_BITLSHIFT(58); | |
97 | rs = pid << PPC_BITLSHIFT(31); | |
98 | prs = 1; /* process scoped */ | |
99 | r = 1; /* raidx format */ | |
1a472c9d AK |
100 | |
101 | asm volatile("ptesync": : :"memory"); | |
102 | asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |" | |
103 | "(%2 << 17) | (%3 << 18) | (%4 << 21)" | |
104 | : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); | |
105 | asm volatile("eieio; tlbsync; ptesync": : :"memory"); | |
106 | } | |
107 | ||
108 | /* | |
109 | * Base TLB flushing operations: | |
110 | * | |
111 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | |
112 | * - flush_tlb_page(vma, vmaddr) flushes one page | |
113 | * - flush_tlb_range(vma, start, end) flushes a range of pages | |
114 | * - flush_tlb_kernel_range(start, end) flushes kernel pages | |
115 | * | |
116 | * - local_* variants of page and mm only apply to the current | |
117 | * processor | |
118 | */ | |
119 | void radix__local_flush_tlb_mm(struct mm_struct *mm) | |
120 | { | |
9690c157 | 121 | unsigned long pid; |
1a472c9d AK |
122 | |
123 | preempt_disable(); | |
124 | pid = mm->context.id; | |
125 | if (pid != MMU_NO_CONTEXT) | |
36194812 | 126 | _tlbiel_pid(pid, RIC_FLUSH_ALL); |
1a472c9d AK |
127 | preempt_enable(); |
128 | } | |
129 | EXPORT_SYMBOL(radix__local_flush_tlb_mm); | |
130 | ||
131 | void radix___local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, | |
132 | unsigned long ap, int nid) | |
133 | { | |
9690c157 | 134 | unsigned long pid; |
1a472c9d AK |
135 | |
136 | preempt_disable(); | |
137 | pid = mm ? mm->context.id : 0; | |
138 | if (pid != MMU_NO_CONTEXT) | |
36194812 | 139 | _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB); |
1a472c9d AK |
140 | preempt_enable(); |
141 | } | |
142 | ||
143 | void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) | |
144 | { | |
48483760 AK |
145 | #ifdef CONFIG_HUGETLB_PAGE |
146 | /* need the return fix for nohash.c */ | |
147 | if (vma && is_vm_hugetlb_page(vma)) | |
148 | return __local_flush_hugetlb_page(vma, vmaddr); | |
149 | #endif | |
1a472c9d AK |
150 | radix___local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr, |
151 | mmu_get_ap(mmu_virtual_psize), 0); | |
152 | } | |
153 | EXPORT_SYMBOL(radix__local_flush_tlb_page); | |
154 | ||
155 | #ifdef CONFIG_SMP | |
156 | static int mm_is_core_local(struct mm_struct *mm) | |
157 | { | |
158 | return cpumask_subset(mm_cpumask(mm), | |
159 | topology_sibling_cpumask(smp_processor_id())); | |
160 | } | |
161 | ||
162 | void radix__flush_tlb_mm(struct mm_struct *mm) | |
163 | { | |
9690c157 | 164 | unsigned long pid; |
1a472c9d AK |
165 | |
166 | preempt_disable(); | |
167 | pid = mm->context.id; | |
168 | if (unlikely(pid == MMU_NO_CONTEXT)) | |
169 | goto no_context; | |
170 | ||
171 | if (!mm_is_core_local(mm)) { | |
172 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); | |
173 | ||
174 | if (lock_tlbie) | |
175 | raw_spin_lock(&native_tlbie_lock); | |
36194812 | 176 | _tlbie_pid(pid, RIC_FLUSH_ALL); |
1a472c9d AK |
177 | if (lock_tlbie) |
178 | raw_spin_unlock(&native_tlbie_lock); | |
179 | } else | |
36194812 | 180 | _tlbiel_pid(pid, RIC_FLUSH_ALL); |
1a472c9d AK |
181 | no_context: |
182 | preempt_enable(); | |
183 | } | |
184 | EXPORT_SYMBOL(radix__flush_tlb_mm); | |
185 | ||
186 | void radix___flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, | |
187 | unsigned long ap, int nid) | |
188 | { | |
9690c157 | 189 | unsigned long pid; |
1a472c9d AK |
190 | |
191 | preempt_disable(); | |
192 | pid = mm ? mm->context.id : 0; | |
193 | if (unlikely(pid == MMU_NO_CONTEXT)) | |
194 | goto bail; | |
195 | if (!mm_is_core_local(mm)) { | |
196 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); | |
197 | ||
198 | if (lock_tlbie) | |
199 | raw_spin_lock(&native_tlbie_lock); | |
36194812 | 200 | _tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB); |
1a472c9d AK |
201 | if (lock_tlbie) |
202 | raw_spin_unlock(&native_tlbie_lock); | |
203 | } else | |
36194812 | 204 | _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB); |
1a472c9d AK |
205 | bail: |
206 | preempt_enable(); | |
207 | } | |
208 | ||
209 | void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) | |
210 | { | |
48483760 AK |
211 | #ifdef CONFIG_HUGETLB_PAGE |
212 | if (vma && is_vm_hugetlb_page(vma)) | |
213 | return flush_hugetlb_page(vma, vmaddr); | |
214 | #endif | |
1a472c9d AK |
215 | radix___flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr, |
216 | mmu_get_ap(mmu_virtual_psize), 0); | |
217 | } | |
218 | EXPORT_SYMBOL(radix__flush_tlb_page); | |
219 | ||
220 | #endif /* CONFIG_SMP */ | |
221 | ||
222 | void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
223 | { | |
224 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); | |
225 | ||
226 | if (lock_tlbie) | |
227 | raw_spin_lock(&native_tlbie_lock); | |
36194812 | 228 | _tlbie_pid(0, RIC_FLUSH_ALL); |
1a472c9d AK |
229 | if (lock_tlbie) |
230 | raw_spin_unlock(&native_tlbie_lock); | |
231 | } | |
232 | EXPORT_SYMBOL(radix__flush_tlb_kernel_range); | |
233 | ||
234 | /* | |
235 | * Currently, for range flushing, we just do a full mm flush. Because | |
236 | * we use this in code path where we don' track the page size. | |
237 | */ | |
238 | void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
239 | unsigned long end) | |
240 | ||
241 | { | |
242 | struct mm_struct *mm = vma->vm_mm; | |
243 | radix__flush_tlb_mm(mm); | |
244 | } | |
245 | EXPORT_SYMBOL(radix__flush_tlb_range); | |
246 | ||
247 | ||
248 | void radix__tlb_flush(struct mmu_gather *tlb) | |
249 | { | |
250 | struct mm_struct *mm = tlb->mm; | |
251 | radix__flush_tlb_mm(mm); | |
252 | } |