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Commit | Line | Data |
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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
b0d436c7 | 27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL |
3925f46b | 28 | |
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
9de5cb0f ME |
39 | /* |
40 | * The order of the MMCR array is: | |
41 | * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 | |
42 | * - 32-bit, MMCR0, MMCR1, MMCR2 | |
43 | */ | |
44 | unsigned long mmcr[4]; | |
a8f90e90 PM |
45 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
46 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
47 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
48 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
49 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 | 50 | |
fbbe0701 | 51 | unsigned int txn_flags; |
8e6d5573 | 52 | int n_txn_start; |
3925f46b AK |
53 | |
54 | /* BHRB bits */ | |
55 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
f0322f7f | 56 | unsigned int bhrb_users; |
3925f46b AK |
57 | void *bhrb_context; |
58 | struct perf_branch_stack bhrb_stack; | |
59 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
356d8ce3 | 60 | u64 ic_init; |
4574910e | 61 | }; |
3925f46b | 62 | |
e51df2c1 | 63 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e | 64 | |
e51df2c1 | 65 | static struct power_pmu *ppmu; |
4574910e | 66 | |
d095cd46 | 67 | /* |
57c0c15b | 68 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
69 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
70 | * hypervisor bit set in the MSR, or if we are running on a processor | |
71 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
72 | * then we need to use the FCHV bit to ignore kernel events. | |
73 | */ | |
cdd6c482 | 74 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 75 | |
98fb1807 PM |
76 | /* |
77 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
78 | * and a few other names are different. | |
79 | */ | |
80 | #ifdef CONFIG_PPC32 | |
81 | ||
82 | #define MMCR0_FCHV 0 | |
83 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
7a7a41f9 | 84 | #define MMCR0_FC56 0 |
378a6ee9 | 85 | #define MMCR0_PMAO 0 |
330a1eb7 | 86 | #define MMCR0_EBE 0 |
76cb8a78 | 87 | #define MMCR0_BHRBA 0 |
330a1eb7 ME |
88 | #define MMCR0_PMCC 0 |
89 | #define MMCR0_PMCC_U6 0 | |
98fb1807 PM |
90 | |
91 | #define SPRN_MMCRA SPRN_MMCR2 | |
92 | #define MMCRA_SAMPLE_ENABLE 0 | |
93 | ||
94 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
95 | { | |
96 | return 0; | |
97 | } | |
98fb1807 PM |
98 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
99 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
100 | { | |
101 | return 0; | |
102 | } | |
75382aa7 AB |
103 | static inline void perf_read_regs(struct pt_regs *regs) |
104 | { | |
105 | regs->result = 0; | |
106 | } | |
98fb1807 PM |
107 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
108 | { | |
109 | return 0; | |
110 | } | |
111 | ||
e6878835 | 112 | static inline int siar_valid(struct pt_regs *regs) |
113 | { | |
114 | return 1; | |
115 | } | |
116 | ||
330a1eb7 ME |
117 | static bool is_ebb_event(struct perf_event *event) { return false; } |
118 | static int ebb_event_check(struct perf_event *event) { return 0; } | |
119 | static void ebb_event_add(struct perf_event *event) { } | |
120 | static void ebb_switch_out(unsigned long mmcr0) { } | |
9de5cb0f | 121 | static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) |
330a1eb7 | 122 | { |
9de5cb0f | 123 | return cpuhw->mmcr[0]; |
330a1eb7 ME |
124 | } |
125 | ||
d52f2dc4 MN |
126 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
127 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
acba3c7e | 128 | static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} |
d52f2dc4 | 129 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} |
c2e37a26 | 130 | static void pmao_restore_workaround(bool ebb) { } |
356d8ce3 MS |
131 | static bool use_ic(u64 event) |
132 | { | |
133 | return false; | |
134 | } | |
98fb1807 PM |
135 | #endif /* CONFIG_PPC32 */ |
136 | ||
33904054 ME |
137 | static bool regs_use_siar(struct pt_regs *regs) |
138 | { | |
72e349f1 AB |
139 | /* |
140 | * When we take a performance monitor exception the regs are setup | |
141 | * using perf_read_regs() which overloads some fields, in particular | |
142 | * regs->result to tell us whether to use SIAR. | |
143 | * | |
144 | * However if the regs are from another exception, eg. a syscall, then | |
145 | * they have not been setup using perf_read_regs() and so regs->result | |
146 | * is something random. | |
147 | */ | |
148 | return ((TRAP(regs) == 0xf00) && regs->result); | |
33904054 ME |
149 | } |
150 | ||
98fb1807 PM |
151 | /* |
152 | * Things that are specific to 64-bit implementations. | |
153 | */ | |
154 | #ifdef CONFIG_PPC64 | |
155 | ||
156 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
157 | { | |
158 | unsigned long mmcra = regs->dsisr; | |
159 | ||
7a786832 | 160 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
161 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
162 | if (slot > 1) | |
163 | return 4 * (slot - 1); | |
164 | } | |
7a786832 | 165 | |
98fb1807 PM |
166 | return 0; |
167 | } | |
168 | ||
98fb1807 PM |
169 | /* |
170 | * The user wants a data address recorded. | |
171 | * If we're not doing instruction sampling, give them the SDAR | |
172 | * (sampled data address). If we are doing instruction sampling, then | |
173 | * only give them the SDAR if it corresponds to the instruction | |
58a032c3 ME |
174 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the |
175 | * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. | |
98fb1807 PM |
176 | */ |
177 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
178 | { | |
179 | unsigned long mmcra = regs->dsisr; | |
58a032c3 | 180 | bool sdar_valid; |
e6878835 | 181 | |
58a032c3 ME |
182 | if (ppmu->flags & PPMU_HAS_SIER) |
183 | sdar_valid = regs->dar & SIER_SDAR_VALID; | |
184 | else { | |
185 | unsigned long sdsync; | |
186 | ||
187 | if (ppmu->flags & PPMU_SIAR_VALID) | |
188 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
189 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
190 | sdsync = POWER6_MMCRA_SDSYNC; | |
f04d1080 MS |
191 | else if (ppmu->flags & PPMU_NO_SIAR) |
192 | sdsync = MMCRA_SAMPLE_ENABLE; | |
58a032c3 ME |
193 | else |
194 | sdsync = MMCRA_SDSYNC; | |
195 | ||
196 | sdar_valid = mmcra & sdsync; | |
197 | } | |
98fb1807 | 198 | |
58a032c3 | 199 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) |
98fb1807 PM |
200 | *addrp = mfspr(SPRN_SDAR); |
201 | } | |
202 | ||
5682c460 | 203 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
204 | { |
205 | unsigned long sihv = MMCRA_SIHV; | |
206 | ||
8f61aa32 ME |
207 | if (ppmu->flags & PPMU_HAS_SIER) |
208 | return !!(regs->dar & SIER_SIHV); | |
209 | ||
68b30bb9 AB |
210 | if (ppmu->flags & PPMU_ALT_SIPR) |
211 | sihv = POWER6_MMCRA_SIHV; | |
212 | ||
5682c460 | 213 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
214 | } |
215 | ||
5682c460 | 216 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
217 | { |
218 | unsigned long sipr = MMCRA_SIPR; | |
219 | ||
8f61aa32 ME |
220 | if (ppmu->flags & PPMU_HAS_SIER) |
221 | return !!(regs->dar & SIER_SIPR); | |
222 | ||
68b30bb9 AB |
223 | if (ppmu->flags & PPMU_ALT_SIPR) |
224 | sipr = POWER6_MMCRA_SIPR; | |
225 | ||
5682c460 | 226 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
227 | } |
228 | ||
1ce447b9 BH |
229 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
230 | { | |
231 | if (regs->msr & MSR_PR) | |
232 | return PERF_RECORD_MISC_USER; | |
233 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
234 | return PERF_RECORD_MISC_HYPERVISOR; | |
235 | return PERF_RECORD_MISC_KERNEL; | |
236 | } | |
237 | ||
98fb1807 PM |
238 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
239 | { | |
33904054 | 240 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 241 | |
75382aa7 | 242 | if (!use_siar) |
1ce447b9 BH |
243 | return perf_flags_from_msr(regs); |
244 | ||
245 | /* | |
246 | * If we don't have flags in MMCRA, rather than using | |
247 | * the MSR, we intuit the flags from the address in | |
248 | * SIAR which should give slightly more reliable | |
249 | * results | |
250 | */ | |
cbda6aa1 | 251 | if (ppmu->flags & PPMU_NO_SIPR) { |
1ce447b9 | 252 | unsigned long siar = mfspr(SPRN_SIAR); |
a2391b35 | 253 | if (is_kernel_addr(siar)) |
1ce447b9 BH |
254 | return PERF_RECORD_MISC_KERNEL; |
255 | return PERF_RECORD_MISC_USER; | |
256 | } | |
98fb1807 | 257 | |
7abb840b | 258 | /* PR has priority over HV, so order below is important */ |
5682c460 | 259 | if (regs_sipr(regs)) |
7abb840b | 260 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
261 | |
262 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 263 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 264 | |
7abb840b | 265 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
266 | } |
267 | ||
268 | /* | |
269 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
270 | * on each interrupt. | |
8f61aa32 | 271 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
272 | * Overload regs->result to specify whether we should use the MSR (result |
273 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
274 | */ |
275 | static inline void perf_read_regs(struct pt_regs *regs) | |
276 | { | |
75382aa7 AB |
277 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
278 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
279 | int use_siar; | |
280 | ||
5682c460 | 281 | regs->dsisr = mmcra; |
8f61aa32 | 282 | |
cbda6aa1 ME |
283 | if (ppmu->flags & PPMU_HAS_SIER) |
284 | regs->dar = mfspr(SPRN_SIER); | |
8f61aa32 | 285 | |
5c093efa AB |
286 | /* |
287 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
288 | * not valid. Use pt_regs. | |
289 | * | |
290 | * If it is a marked event use the SIAR. | |
291 | * | |
292 | * If the PMU doesn't update the SIAR for non marked events use | |
293 | * pt_regs. | |
294 | * | |
295 | * If the PMU has HV/PR flags then check to see if they | |
296 | * place the exception in userspace. If so, use pt_regs. In | |
297 | * continuous sampling mode the SIAR and the PMU exception are | |
298 | * not synchronised, so they may be many instructions apart. | |
299 | * This can result in confusing backtraces. We still want | |
300 | * hypervisor samples as well as samples in the kernel with | |
301 | * interrupts off hence the userspace check. | |
302 | */ | |
75382aa7 AB |
303 | if (TRAP(regs) != 0xf00) |
304 | use_siar = 0; | |
27593d72 MS |
305 | else if ((ppmu->flags & PPMU_NO_SIAR)) |
306 | use_siar = 0; | |
5c093efa AB |
307 | else if (marked) |
308 | use_siar = 1; | |
309 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
310 | use_siar = 0; | |
cbda6aa1 | 311 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
312 | use_siar = 0; |
313 | else | |
314 | use_siar = 1; | |
315 | ||
cbda6aa1 | 316 | regs->result = use_siar; |
98fb1807 PM |
317 | } |
318 | ||
319 | /* | |
320 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
321 | * it as an NMI. | |
322 | */ | |
323 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
324 | { | |
325 | return !regs->softe; | |
326 | } | |
327 | ||
e6878835 | 328 | /* |
329 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
330 | * must be sampled only if the SIAR-valid bit is set. | |
331 | * | |
332 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
333 | * bit, assume that SIAR is valid. | |
334 | */ | |
335 | static inline int siar_valid(struct pt_regs *regs) | |
336 | { | |
337 | unsigned long mmcra = regs->dsisr; | |
338 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
339 | ||
58a032c3 ME |
340 | if (marked) { |
341 | if (ppmu->flags & PPMU_HAS_SIER) | |
342 | return regs->dar & SIER_SIAR_VALID; | |
343 | ||
344 | if (ppmu->flags & PPMU_SIAR_VALID) | |
345 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
346 | } | |
e6878835 | 347 | |
348 | return 1; | |
349 | } | |
350 | ||
d52f2dc4 MN |
351 | |
352 | /* Reset all possible BHRB entries */ | |
353 | static void power_pmu_bhrb_reset(void) | |
354 | { | |
355 | asm volatile(PPC_CLRBHRB); | |
356 | } | |
357 | ||
358 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
359 | { | |
69111bac | 360 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
d52f2dc4 MN |
361 | |
362 | if (!ppmu->bhrb_nr) | |
363 | return; | |
364 | ||
365 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
366 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
367 | power_pmu_bhrb_reset(); | |
368 | cpuhw->bhrb_context = event->ctx; | |
369 | } | |
370 | cpuhw->bhrb_users++; | |
acba3c7e | 371 | perf_sched_cb_inc(event->ctx->pmu); |
d52f2dc4 MN |
372 | } |
373 | ||
374 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
375 | { | |
69111bac | 376 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
d52f2dc4 MN |
377 | |
378 | if (!ppmu->bhrb_nr) | |
379 | return; | |
380 | ||
f0322f7f | 381 | WARN_ON_ONCE(!cpuhw->bhrb_users); |
d52f2dc4 | 382 | cpuhw->bhrb_users--; |
acba3c7e | 383 | perf_sched_cb_dec(event->ctx->pmu); |
d52f2dc4 MN |
384 | |
385 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
386 | /* BHRB cannot be turned off when other | |
387 | * events are active on the PMU. | |
388 | */ | |
389 | ||
390 | /* avoid stale pointer */ | |
391 | cpuhw->bhrb_context = NULL; | |
392 | } | |
393 | } | |
394 | ||
395 | /* Called from ctxsw to prevent one process's branch entries to | |
396 | * mingle with the other process's entries during context switch. | |
397 | */ | |
acba3c7e | 398 | static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d52f2dc4 | 399 | { |
acba3c7e PZ |
400 | if (!ppmu->bhrb_nr) |
401 | return; | |
402 | ||
403 | if (sched_in) | |
d52f2dc4 MN |
404 | power_pmu_bhrb_reset(); |
405 | } | |
69123184 MN |
406 | /* Calculate the to address for a branch */ |
407 | static __u64 power_pmu_bhrb_to(u64 addr) | |
408 | { | |
409 | unsigned int instr; | |
410 | int ret; | |
411 | __u64 target; | |
412 | ||
413 | if (is_kernel_addr(addr)) | |
414 | return branch_target((unsigned int *)addr); | |
415 | ||
416 | /* Userspace: need copy instruction here then translate it */ | |
417 | pagefault_disable(); | |
418 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
419 | if (ret) { | |
420 | pagefault_enable(); | |
421 | return 0; | |
422 | } | |
423 | pagefault_enable(); | |
424 | ||
425 | target = branch_target(&instr); | |
426 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
427 | return target; | |
428 | ||
429 | /* Translate relative branch target from kernel to user address */ | |
430 | return target - (unsigned long)&instr + addr; | |
431 | } | |
d52f2dc4 | 432 | |
d52f2dc4 | 433 | /* Processing BHRB entries */ |
e51df2c1 | 434 | static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
435 | { |
436 | u64 val; | |
437 | u64 addr; | |
506e70d1 | 438 | int r_index, u_index, pred; |
d52f2dc4 MN |
439 | |
440 | r_index = 0; | |
441 | u_index = 0; | |
442 | while (r_index < ppmu->bhrb_nr) { | |
443 | /* Assembly read function */ | |
506e70d1 MN |
444 | val = read_bhrb(r_index++); |
445 | if (!val) | |
446 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 447 | break; |
506e70d1 | 448 | else { |
d52f2dc4 MN |
449 | addr = val & BHRB_EA; |
450 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 451 | |
506e70d1 MN |
452 | if (!addr) |
453 | /* invalid entry */ | |
d52f2dc4 | 454 | continue; |
d52f2dc4 | 455 | |
506e70d1 MN |
456 | /* Branches are read most recent first (ie. mfbhrb 0 is |
457 | * the most recent branch). | |
458 | * There are two types of valid entries: | |
459 | * 1) a target entry which is the to address of a | |
460 | * computed goto like a blr,bctr,btar. The next | |
461 | * entry read from the bhrb will be branch | |
462 | * corresponding to this target (ie. the actual | |
463 | * blr/bctr/btar instruction). | |
464 | * 2) a from address which is an actual branch. If a | |
465 | * target entry proceeds this, then this is the | |
466 | * matching branch for that target. If this is not | |
467 | * following a target entry, then this is a branch | |
468 | * where the target is given as an immediate field | |
469 | * in the instruction (ie. an i or b form branch). | |
470 | * In this case we need to read the instruction from | |
471 | * memory to determine the target/to address. | |
472 | */ | |
d52f2dc4 | 473 | |
d52f2dc4 | 474 | if (val & BHRB_TARGET) { |
506e70d1 MN |
475 | /* Target branches use two entries |
476 | * (ie. computed gotos/XL form) | |
477 | */ | |
478 | cpuhw->bhrb_entries[u_index].to = addr; | |
479 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
480 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 481 | |
506e70d1 MN |
482 | /* Get from address in next entry */ |
483 | val = read_bhrb(r_index++); | |
484 | addr = val & BHRB_EA; | |
485 | if (val & BHRB_TARGET) { | |
486 | /* Shouldn't have two targets in a | |
487 | row.. Reset index and try again */ | |
488 | r_index--; | |
489 | addr = 0; | |
490 | } | |
491 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 492 | } else { |
506e70d1 MN |
493 | /* Branches to immediate field |
494 | (ie I or B form) */ | |
d52f2dc4 | 495 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
496 | cpuhw->bhrb_entries[u_index].to = |
497 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
498 | cpuhw->bhrb_entries[u_index].mispred = pred; |
499 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 500 | } |
506e70d1 MN |
501 | u_index++; |
502 | ||
d52f2dc4 MN |
503 | } |
504 | } | |
505 | cpuhw->bhrb_stack.nr = u_index; | |
506 | return; | |
507 | } | |
508 | ||
330a1eb7 ME |
509 | static bool is_ebb_event(struct perf_event *event) |
510 | { | |
511 | /* | |
512 | * This could be a per-PMU callback, but we'd rather avoid the cost. We | |
513 | * check that the PMU supports EBB, meaning those that don't can still | |
514 | * use bit 63 of the event code for something else if they wish. | |
515 | */ | |
4d9690dd | 516 | return (ppmu->flags & PPMU_ARCH_207S) && |
8d7c55d0 | 517 | ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); |
330a1eb7 ME |
518 | } |
519 | ||
520 | static int ebb_event_check(struct perf_event *event) | |
521 | { | |
522 | struct perf_event *leader = event->group_leader; | |
523 | ||
524 | /* Event and group leader must agree on EBB */ | |
525 | if (is_ebb_event(leader) != is_ebb_event(event)) | |
526 | return -EINVAL; | |
527 | ||
528 | if (is_ebb_event(event)) { | |
529 | if (!(event->attach_state & PERF_ATTACH_TASK)) | |
530 | return -EINVAL; | |
531 | ||
532 | if (!leader->attr.pinned || !leader->attr.exclusive) | |
533 | return -EINVAL; | |
534 | ||
58b5fb00 ME |
535 | if (event->attr.freq || |
536 | event->attr.inherit || | |
537 | event->attr.sample_type || | |
538 | event->attr.sample_period || | |
539 | event->attr.enable_on_exec) | |
330a1eb7 ME |
540 | return -EINVAL; |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
546 | static void ebb_event_add(struct perf_event *event) | |
547 | { | |
548 | if (!is_ebb_event(event) || current->thread.used_ebb) | |
549 | return; | |
550 | ||
551 | /* | |
552 | * IFF this is the first time we've added an EBB event, set | |
553 | * PMXE in the user MMCR0 so we can detect when it's cleared by | |
554 | * userspace. We need this so that we can context switch while | |
555 | * userspace is in the EBB handler (where PMXE is 0). | |
556 | */ | |
557 | current->thread.used_ebb = 1; | |
558 | current->thread.mmcr0 |= MMCR0_PMXE; | |
559 | } | |
560 | ||
561 | static void ebb_switch_out(unsigned long mmcr0) | |
562 | { | |
563 | if (!(mmcr0 & MMCR0_EBE)) | |
564 | return; | |
565 | ||
566 | current->thread.siar = mfspr(SPRN_SIAR); | |
567 | current->thread.sier = mfspr(SPRN_SIER); | |
568 | current->thread.sdar = mfspr(SPRN_SDAR); | |
569 | current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; | |
570 | current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; | |
571 | } | |
572 | ||
9de5cb0f | 573 | static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) |
330a1eb7 | 574 | { |
9de5cb0f ME |
575 | unsigned long mmcr0 = cpuhw->mmcr[0]; |
576 | ||
330a1eb7 ME |
577 | if (!ebb) |
578 | goto out; | |
579 | ||
76cb8a78 ME |
580 | /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ |
581 | mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; | |
330a1eb7 | 582 | |
c2e37a26 ME |
583 | /* |
584 | * Add any bits from the user MMCR0, FC or PMAO. This is compatible | |
585 | * with pmao_restore_workaround() because we may add PMAO but we never | |
586 | * clear it here. | |
587 | */ | |
330a1eb7 ME |
588 | mmcr0 |= current->thread.mmcr0; |
589 | ||
c2e37a26 ME |
590 | /* |
591 | * Be careful not to set PMXE if userspace had it cleared. This is also | |
592 | * compatible with pmao_restore_workaround() because it has already | |
593 | * cleared PMXE and we leave PMAO alone. | |
594 | */ | |
330a1eb7 ME |
595 | if (!(current->thread.mmcr0 & MMCR0_PMXE)) |
596 | mmcr0 &= ~MMCR0_PMXE; | |
597 | ||
598 | mtspr(SPRN_SIAR, current->thread.siar); | |
599 | mtspr(SPRN_SIER, current->thread.sier); | |
600 | mtspr(SPRN_SDAR, current->thread.sdar); | |
9de5cb0f ME |
601 | |
602 | /* | |
603 | * Merge the kernel & user values of MMCR2. The semantics we implement | |
604 | * are that the user MMCR2 can set bits, ie. cause counters to freeze, | |
605 | * but not clear bits. If a task wants to be able to clear bits, ie. | |
606 | * unfreeze counters, it should not set exclude_xxx in its events and | |
607 | * instead manage the MMCR2 entirely by itself. | |
608 | */ | |
609 | mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2); | |
330a1eb7 ME |
610 | out: |
611 | return mmcr0; | |
612 | } | |
c2e37a26 ME |
613 | |
614 | static void pmao_restore_workaround(bool ebb) | |
615 | { | |
616 | unsigned pmcs[6]; | |
617 | ||
618 | if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) | |
619 | return; | |
620 | ||
621 | /* | |
622 | * On POWER8E there is a hardware defect which affects the PMU context | |
623 | * switch logic, ie. power_pmu_disable/enable(). | |
624 | * | |
625 | * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 | |
626 | * by the hardware. Sometime later the actual PMU exception is | |
627 | * delivered. | |
628 | * | |
629 | * If we context switch, or simply disable/enable, the PMU prior to the | |
630 | * exception arriving, the exception will be lost when we clear PMAO. | |
631 | * | |
632 | * When we reenable the PMU, we will write the saved MMCR0 with PMAO | |
633 | * set, and this _should_ generate an exception. However because of the | |
634 | * defect no exception is generated when we write PMAO, and we get | |
635 | * stuck with no counters counting but no exception delivered. | |
636 | * | |
637 | * The workaround is to detect this case and tweak the hardware to | |
638 | * create another pending PMU exception. | |
639 | * | |
640 | * We do that by setting up PMC6 (cycles) for an imminent overflow and | |
641 | * enabling the PMU. That causes a new exception to be generated in the | |
642 | * chip, but we don't take it yet because we have interrupts hard | |
643 | * disabled. We then write back the PMU state as we want it to be seen | |
644 | * by the exception handler. When we reenable interrupts the exception | |
645 | * handler will be called and see the correct state. | |
646 | * | |
647 | * The logic is the same for EBB, except that the exception is gated by | |
648 | * us having interrupts hard disabled as well as the fact that we are | |
649 | * not in userspace. The exception is finally delivered when we return | |
650 | * to userspace. | |
651 | */ | |
652 | ||
653 | /* Only if PMAO is set and PMAO_SYNC is clear */ | |
654 | if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) | |
655 | return; | |
656 | ||
657 | /* If we're doing EBB, only if BESCR[GE] is set */ | |
658 | if (ebb && !(current->thread.bescr & BESCR_GE)) | |
659 | return; | |
660 | ||
661 | /* | |
662 | * We are already soft-disabled in power_pmu_enable(). We need to hard | |
58bffb5b | 663 | * disable to actually prevent the PMU exception from firing. |
c2e37a26 ME |
664 | */ |
665 | hard_irq_disable(); | |
666 | ||
667 | /* | |
668 | * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. | |
669 | * Using read/write_pmc() in a for loop adds 12 function calls and | |
670 | * almost doubles our code size. | |
671 | */ | |
672 | pmcs[0] = mfspr(SPRN_PMC1); | |
673 | pmcs[1] = mfspr(SPRN_PMC2); | |
674 | pmcs[2] = mfspr(SPRN_PMC3); | |
675 | pmcs[3] = mfspr(SPRN_PMC4); | |
676 | pmcs[4] = mfspr(SPRN_PMC5); | |
677 | pmcs[5] = mfspr(SPRN_PMC6); | |
678 | ||
679 | /* Ensure all freeze bits are unset */ | |
680 | mtspr(SPRN_MMCR2, 0); | |
681 | ||
682 | /* Set up PMC6 to overflow in one cycle */ | |
683 | mtspr(SPRN_PMC6, 0x7FFFFFFE); | |
684 | ||
685 | /* Enable exceptions and unfreeze PMC6 */ | |
686 | mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); | |
687 | ||
688 | /* Now we need to refreeze and restore the PMCs */ | |
689 | mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); | |
690 | ||
691 | mtspr(SPRN_PMC1, pmcs[0]); | |
692 | mtspr(SPRN_PMC2, pmcs[1]); | |
693 | mtspr(SPRN_PMC3, pmcs[2]); | |
694 | mtspr(SPRN_PMC4, pmcs[3]); | |
695 | mtspr(SPRN_PMC5, pmcs[4]); | |
696 | mtspr(SPRN_PMC6, pmcs[5]); | |
697 | } | |
356d8ce3 MS |
698 | |
699 | static bool use_ic(u64 event) | |
700 | { | |
701 | if (cpu_has_feature(CPU_FTR_POWER9_DD1) && | |
702 | (event == 0x200f2 || event == 0x300f2)) | |
703 | return true; | |
704 | ||
705 | return false; | |
706 | } | |
98fb1807 PM |
707 | #endif /* CONFIG_PPC64 */ |
708 | ||
cdd6c482 | 709 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 710 | |
4574910e | 711 | /* |
57c0c15b | 712 | * Read one performance monitor counter (PMC). |
4574910e PM |
713 | */ |
714 | static unsigned long read_pmc(int idx) | |
715 | { | |
716 | unsigned long val; | |
717 | ||
718 | switch (idx) { | |
719 | case 1: | |
720 | val = mfspr(SPRN_PMC1); | |
721 | break; | |
722 | case 2: | |
723 | val = mfspr(SPRN_PMC2); | |
724 | break; | |
725 | case 3: | |
726 | val = mfspr(SPRN_PMC3); | |
727 | break; | |
728 | case 4: | |
729 | val = mfspr(SPRN_PMC4); | |
730 | break; | |
731 | case 5: | |
732 | val = mfspr(SPRN_PMC5); | |
733 | break; | |
734 | case 6: | |
735 | val = mfspr(SPRN_PMC6); | |
736 | break; | |
98fb1807 | 737 | #ifdef CONFIG_PPC64 |
4574910e PM |
738 | case 7: |
739 | val = mfspr(SPRN_PMC7); | |
740 | break; | |
741 | case 8: | |
742 | val = mfspr(SPRN_PMC8); | |
743 | break; | |
98fb1807 | 744 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
745 | default: |
746 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
747 | val = 0; | |
748 | } | |
749 | return val; | |
750 | } | |
751 | ||
752 | /* | |
753 | * Write one PMC. | |
754 | */ | |
755 | static void write_pmc(int idx, unsigned long val) | |
756 | { | |
757 | switch (idx) { | |
758 | case 1: | |
759 | mtspr(SPRN_PMC1, val); | |
760 | break; | |
761 | case 2: | |
762 | mtspr(SPRN_PMC2, val); | |
763 | break; | |
764 | case 3: | |
765 | mtspr(SPRN_PMC3, val); | |
766 | break; | |
767 | case 4: | |
768 | mtspr(SPRN_PMC4, val); | |
769 | break; | |
770 | case 5: | |
771 | mtspr(SPRN_PMC5, val); | |
772 | break; | |
773 | case 6: | |
774 | mtspr(SPRN_PMC6, val); | |
775 | break; | |
98fb1807 | 776 | #ifdef CONFIG_PPC64 |
4574910e PM |
777 | case 7: |
778 | mtspr(SPRN_PMC7, val); | |
779 | break; | |
780 | case 8: | |
781 | mtspr(SPRN_PMC8, val); | |
782 | break; | |
98fb1807 | 783 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
784 | default: |
785 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
786 | } | |
787 | } | |
788 | ||
5f6d0380 AK |
789 | /* Called from sysrq_handle_showregs() */ |
790 | void perf_event_print_debug(void) | |
791 | { | |
792 | unsigned long sdar, sier, flags; | |
793 | u32 pmcs[MAX_HWEVENTS]; | |
794 | int i; | |
795 | ||
4917fcb5 RB |
796 | if (!ppmu) { |
797 | pr_info("Performance monitor hardware not registered.\n"); | |
798 | return; | |
799 | } | |
800 | ||
5f6d0380 AK |
801 | if (!ppmu->n_counter) |
802 | return; | |
803 | ||
804 | local_irq_save(flags); | |
805 | ||
806 | pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", | |
807 | smp_processor_id(), ppmu->name, ppmu->n_counter); | |
808 | ||
809 | for (i = 0; i < ppmu->n_counter; i++) | |
810 | pmcs[i] = read_pmc(i + 1); | |
811 | ||
812 | for (; i < MAX_HWEVENTS; i++) | |
813 | pmcs[i] = 0xdeadbeef; | |
814 | ||
815 | pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", | |
816 | pmcs[0], pmcs[1], pmcs[2], pmcs[3]); | |
817 | ||
818 | if (ppmu->n_counter > 4) | |
819 | pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", | |
820 | pmcs[4], pmcs[5], pmcs[6], pmcs[7]); | |
821 | ||
822 | pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", | |
823 | mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); | |
824 | ||
825 | sdar = sier = 0; | |
826 | #ifdef CONFIG_PPC64 | |
827 | sdar = mfspr(SPRN_SDAR); | |
828 | ||
829 | if (ppmu->flags & PPMU_HAS_SIER) | |
830 | sier = mfspr(SPRN_SIER); | |
831 | ||
4d9690dd | 832 | if (ppmu->flags & PPMU_ARCH_207S) { |
5f6d0380 AK |
833 | pr_info("MMCR2: %016lx EBBHR: %016lx\n", |
834 | mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); | |
835 | pr_info("EBBRR: %016lx BESCR: %016lx\n", | |
836 | mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); | |
837 | } | |
838 | #endif | |
839 | pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", | |
840 | mfspr(SPRN_SIAR), sdar, sier); | |
841 | ||
842 | local_irq_restore(flags); | |
843 | } | |
844 | ||
4574910e PM |
845 | /* |
846 | * Check if a set of events can all go on the PMU at once. | |
847 | * If they can't, this will look at alternative codes for the events | |
848 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 849 | * The feasible set is returned in event_id[]. |
4574910e | 850 | */ |
cdd6c482 IM |
851 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
852 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 853 | int n_ev) |
4574910e | 854 | { |
448d64f8 | 855 | unsigned long mask, value, nv; |
cdd6c482 IM |
856 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
857 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 858 | int i, j; |
448d64f8 PM |
859 | unsigned long addf = ppmu->add_fields; |
860 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 861 | |
a8f90e90 | 862 | if (n_ev > ppmu->n_counter) |
4574910e PM |
863 | return -1; |
864 | ||
865 | /* First see if the events will go on as-is */ | |
866 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 867 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
868 | && !ppmu->limited_pmc_event(event_id[i])) { |
869 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 870 | cpuhw->alternatives[i]); |
cdd6c482 | 871 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 872 | } |
cdd6c482 | 873 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 874 | &cpuhw->avalues[i][0])) |
4574910e | 875 | return -1; |
4574910e PM |
876 | } |
877 | value = mask = 0; | |
878 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
879 | nv = (value | cpuhw->avalues[i][0]) + |
880 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 881 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
882 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
883 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
884 | break; |
885 | value = nv; | |
e51ee31e | 886 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
887 | } |
888 | if (i == n_ev) | |
889 | return 0; /* all OK */ | |
890 | ||
891 | /* doesn't work, gather alternatives... */ | |
892 | if (!ppmu->get_alternatives) | |
893 | return -1; | |
894 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 895 | choice[i] = 0; |
cdd6c482 | 896 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 897 | cpuhw->alternatives[i]); |
4574910e | 898 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
899 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
900 | &cpuhw->amasks[i][j], | |
901 | &cpuhw->avalues[i][j]); | |
4574910e PM |
902 | } |
903 | ||
904 | /* enumerate all possibilities and see if any will work */ | |
905 | i = 0; | |
906 | j = -1; | |
907 | value = mask = nv = 0; | |
908 | while (i < n_ev) { | |
909 | if (j >= 0) { | |
910 | /* we're backtracking, restore context */ | |
911 | value = svalues[i]; | |
912 | mask = smasks[i]; | |
913 | j = choice[i]; | |
914 | } | |
915 | /* | |
cdd6c482 | 916 | * See if any alternative k for event_id i, |
4574910e PM |
917 | * where k > j, will satisfy the constraints. |
918 | */ | |
919 | while (++j < n_alt[i]) { | |
e51ee31e PM |
920 | nv = (value | cpuhw->avalues[i][j]) + |
921 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 922 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
923 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
924 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
925 | break; |
926 | } | |
927 | if (j >= n_alt[i]) { | |
928 | /* | |
929 | * No feasible alternative, backtrack | |
cdd6c482 | 930 | * to event_id i-1 and continue enumerating its |
4574910e PM |
931 | * alternatives from where we got up to. |
932 | */ | |
933 | if (--i < 0) | |
934 | return -1; | |
935 | } else { | |
936 | /* | |
cdd6c482 IM |
937 | * Found a feasible alternative for event_id i, |
938 | * remember where we got up to with this event_id, | |
939 | * go on to the next event_id, and start with | |
4574910e PM |
940 | * the first alternative for it. |
941 | */ | |
942 | choice[i] = j; | |
943 | svalues[i] = value; | |
944 | smasks[i] = mask; | |
945 | value = nv; | |
e51ee31e | 946 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
947 | ++i; |
948 | j = -1; | |
949 | } | |
950 | } | |
951 | ||
952 | /* OK, we have a feasible combination, tell the caller the solution */ | |
953 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 954 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
955 | return 0; |
956 | } | |
957 | ||
0475f9ea | 958 | /* |
cdd6c482 | 959 | * Check if newly-added events have consistent settings for |
0475f9ea | 960 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 961 | * added events. |
0475f9ea | 962 | */ |
cdd6c482 | 963 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 964 | int n_prev, int n_new) |
0475f9ea | 965 | { |
ab7ef2e5 PM |
966 | int eu = 0, ek = 0, eh = 0; |
967 | int i, n, first; | |
cdd6c482 | 968 | struct perf_event *event; |
0475f9ea | 969 | |
9de5cb0f ME |
970 | /* |
971 | * If the PMU we're on supports per event exclude settings then we | |
972 | * don't need to do any of this logic. NB. This assumes no PMU has both | |
973 | * per event exclude and limited PMCs. | |
974 | */ | |
975 | if (ppmu->flags & PPMU_ARCH_207S) | |
976 | return 0; | |
977 | ||
0475f9ea PM |
978 | n = n_prev + n_new; |
979 | if (n <= 1) | |
980 | return 0; | |
981 | ||
ab7ef2e5 PM |
982 | first = 1; |
983 | for (i = 0; i < n; ++i) { | |
984 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
985 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
986 | continue; | |
987 | } | |
cdd6c482 | 988 | event = ctrs[i]; |
ab7ef2e5 | 989 | if (first) { |
cdd6c482 IM |
990 | eu = event->attr.exclude_user; |
991 | ek = event->attr.exclude_kernel; | |
992 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 993 | first = 0; |
cdd6c482 IM |
994 | } else if (event->attr.exclude_user != eu || |
995 | event->attr.exclude_kernel != ek || | |
996 | event->attr.exclude_hv != eh) { | |
0475f9ea | 997 | return -EAGAIN; |
ab7ef2e5 | 998 | } |
0475f9ea | 999 | } |
ab7ef2e5 PM |
1000 | |
1001 | if (eu || ek || eh) | |
1002 | for (i = 0; i < n; ++i) | |
1003 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
1004 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
1005 | ||
0475f9ea PM |
1006 | return 0; |
1007 | } | |
1008 | ||
86c74ab3 EM |
1009 | static u64 check_and_compute_delta(u64 prev, u64 val) |
1010 | { | |
1011 | u64 delta = (val - prev) & 0xfffffffful; | |
1012 | ||
1013 | /* | |
1014 | * POWER7 can roll back counter values, if the new value is smaller | |
1015 | * than the previous value it will cause the delta and the counter to | |
1016 | * have bogus values unless we rolled a counter over. If a coutner is | |
1017 | * rolled back, it will be smaller, but within 256, which is the maximum | |
027dfac6 | 1018 | * number of events to rollback at once. If we detect a rollback |
86c74ab3 EM |
1019 | * return 0. This can lead to a small lack of precision in the |
1020 | * counters. | |
1021 | */ | |
1022 | if (prev > val && (prev - val) < 256) | |
1023 | delta = 0; | |
1024 | ||
1025 | return delta; | |
1026 | } | |
1027 | ||
cdd6c482 | 1028 | static void power_pmu_read(struct perf_event *event) |
4574910e | 1029 | { |
98fb1807 | 1030 | s64 val, delta, prev; |
356d8ce3 | 1031 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
4574910e | 1032 | |
a4eaf7f1 PZ |
1033 | if (event->hw.state & PERF_HES_STOPPED) |
1034 | return; | |
1035 | ||
cdd6c482 | 1036 | if (!event->hw.idx) |
4574910e | 1037 | return; |
330a1eb7 ME |
1038 | |
1039 | if (is_ebb_event(event)) { | |
1040 | val = read_pmc(event->hw.idx); | |
356d8ce3 MS |
1041 | if (use_ic(event->attr.config)) { |
1042 | val = mfspr(SPRN_IC); | |
1043 | if (val > cpuhw->ic_init) | |
1044 | val = val - cpuhw->ic_init; | |
1045 | else | |
1046 | val = val + (0 - cpuhw->ic_init); | |
1047 | } | |
330a1eb7 ME |
1048 | local64_set(&event->hw.prev_count, val); |
1049 | return; | |
1050 | } | |
1051 | ||
4574910e PM |
1052 | /* |
1053 | * Performance monitor interrupts come even when interrupts | |
1054 | * are soft-disabled, as long as interrupts are hard-enabled. | |
1055 | * Therefore we treat them like NMIs. | |
1056 | */ | |
1057 | do { | |
e7850595 | 1058 | prev = local64_read(&event->hw.prev_count); |
4574910e | 1059 | barrier(); |
cdd6c482 | 1060 | val = read_pmc(event->hw.idx); |
356d8ce3 MS |
1061 | if (use_ic(event->attr.config)) { |
1062 | val = mfspr(SPRN_IC); | |
1063 | if (val > cpuhw->ic_init) | |
1064 | val = val - cpuhw->ic_init; | |
1065 | else | |
1066 | val = val + (0 - cpuhw->ic_init); | |
1067 | } | |
86c74ab3 EM |
1068 | delta = check_and_compute_delta(prev, val); |
1069 | if (!delta) | |
1070 | return; | |
e7850595 | 1071 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 1072 | |
e7850595 | 1073 | local64_add(delta, &event->count); |
f5602941 AB |
1074 | |
1075 | /* | |
1076 | * A number of places program the PMC with (0x80000000 - period_left). | |
1077 | * We never want period_left to be less than 1 because we will program | |
1078 | * the PMC with a value >= 0x800000000 and an edge detected PMC will | |
1079 | * roll around to 0 before taking an exception. We have seen this | |
1080 | * on POWER8. | |
1081 | * | |
1082 | * To fix this, clamp the minimum value of period_left to 1. | |
1083 | */ | |
1084 | do { | |
1085 | prev = local64_read(&event->hw.period_left); | |
1086 | val = prev - delta; | |
1087 | if (val < 1) | |
1088 | val = 1; | |
1089 | } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); | |
4574910e PM |
1090 | } |
1091 | ||
ab7ef2e5 PM |
1092 | /* |
1093 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
1094 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 1095 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
1096 | */ |
1097 | static int is_limited_pmc(int pmcnum) | |
1098 | { | |
0bbd0d4b PM |
1099 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
1100 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
1101 | } |
1102 | ||
a8f90e90 | 1103 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1104 | unsigned long pmc5, unsigned long pmc6) |
1105 | { | |
cdd6c482 | 1106 | struct perf_event *event; |
ab7ef2e5 PM |
1107 | u64 val, prev, delta; |
1108 | int i; | |
1109 | ||
1110 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1111 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 1112 | if (!event->hw.idx) |
ab7ef2e5 | 1113 | continue; |
cdd6c482 | 1114 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 1115 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 1116 | event->hw.idx = 0; |
86c74ab3 EM |
1117 | delta = check_and_compute_delta(prev, val); |
1118 | if (delta) | |
1119 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
1120 | } |
1121 | } | |
1122 | ||
a8f90e90 | 1123 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1124 | unsigned long pmc5, unsigned long pmc6) |
1125 | { | |
cdd6c482 | 1126 | struct perf_event *event; |
86c74ab3 | 1127 | u64 val, prev; |
ab7ef2e5 PM |
1128 | int i; |
1129 | ||
1130 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1131 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
1132 | event->hw.idx = cpuhw->limited_hwidx[i]; |
1133 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
1134 | prev = local64_read(&event->hw.prev_count); |
1135 | if (check_and_compute_delta(prev, val)) | |
1136 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 1137 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
1138 | } |
1139 | } | |
1140 | ||
1141 | /* | |
cdd6c482 | 1142 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 1143 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
1144 | * other events. We try to keep the values from the limited |
1145 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 1146 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
1147 | * the limited events as small and consistent as possible. |
1148 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
1149 | * both, and always in the same order, to minimize variability, |
1150 | * and do it inside the same asm that writes MMCR0. | |
1151 | */ | |
cdd6c482 | 1152 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
1153 | { |
1154 | unsigned long pmc5, pmc6; | |
1155 | ||
1156 | if (!cpuhw->n_limited) { | |
1157 | mtspr(SPRN_MMCR0, mmcr0); | |
1158 | return; | |
1159 | } | |
1160 | ||
1161 | /* | |
1162 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
1163 | * To ensure we don't get a performance monitor interrupt |
1164 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 1165 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 1166 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
1167 | */ |
1168 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
1169 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
1170 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
1171 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
1172 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
1173 | ||
1174 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 1175 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 1176 | else |
a8f90e90 | 1177 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
1178 | |
1179 | /* | |
cdd6c482 | 1180 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
1181 | * enable bits, if necessary. |
1182 | */ | |
1183 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1184 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
1185 | } |
1186 | ||
4574910e | 1187 | /* |
cdd6c482 IM |
1188 | * Disable all events to prevent PMU interrupts and to allow |
1189 | * events to be added or removed. | |
4574910e | 1190 | */ |
a4eaf7f1 | 1191 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 1192 | { |
cdd6c482 | 1193 | struct cpu_hw_events *cpuhw; |
330a1eb7 | 1194 | unsigned long flags, mmcr0, val; |
4574910e | 1195 | |
f36a1a13 PM |
1196 | if (!ppmu) |
1197 | return; | |
4574910e | 1198 | local_irq_save(flags); |
69111bac | 1199 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
4574910e | 1200 | |
448d64f8 | 1201 | if (!cpuhw->disabled) { |
01d0287f PM |
1202 | /* |
1203 | * Check if we ever enabled the PMU on this cpu. | |
1204 | */ | |
1205 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 1206 | ppc_enable_pmcs(); |
01d0287f PM |
1207 | cpuhw->pmcs_enabled = 1; |
1208 | } | |
1209 | ||
378a6ee9 | 1210 | /* |
76cb8a78 | 1211 | * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 |
378a6ee9 | 1212 | */ |
330a1eb7 | 1213 | val = mmcr0 = mfspr(SPRN_MMCR0); |
378a6ee9 | 1214 | val |= MMCR0_FC; |
76cb8a78 ME |
1215 | val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | |
1216 | MMCR0_FC56); | |
378a6ee9 ME |
1217 | |
1218 | /* | |
1219 | * The barrier is to make sure the mtspr has been | |
1220 | * executed and the PMU has frozen the events etc. | |
1221 | * before we return. | |
1222 | */ | |
1223 | write_mmcr0(cpuhw, val); | |
1224 | mb(); | |
1225 | ||
f708223d PM |
1226 | /* |
1227 | * Disable instruction sampling if it was enabled | |
1228 | */ | |
1229 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1230 | mtspr(SPRN_MMCRA, | |
1231 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
1232 | mb(); | |
1233 | } | |
1234 | ||
378a6ee9 ME |
1235 | cpuhw->disabled = 1; |
1236 | cpuhw->n_added = 0; | |
330a1eb7 ME |
1237 | |
1238 | ebb_switch_out(mmcr0); | |
4574910e | 1239 | } |
330a1eb7 | 1240 | |
4574910e | 1241 | local_irq_restore(flags); |
4574910e PM |
1242 | } |
1243 | ||
1244 | /* | |
cdd6c482 IM |
1245 | * Re-enable all events if disable == 0. |
1246 | * If we were previously disabled and events were added, then | |
4574910e PM |
1247 | * put the new config on the PMU. |
1248 | */ | |
a4eaf7f1 | 1249 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 1250 | { |
cdd6c482 IM |
1251 | struct perf_event *event; |
1252 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
1253 | unsigned long flags; |
1254 | long i; | |
330a1eb7 | 1255 | unsigned long val, mmcr0; |
4574910e | 1256 | s64 left; |
cdd6c482 | 1257 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
1258 | int n_lim; |
1259 | int idx; | |
330a1eb7 | 1260 | bool ebb; |
4574910e | 1261 | |
f36a1a13 PM |
1262 | if (!ppmu) |
1263 | return; | |
4574910e | 1264 | local_irq_save(flags); |
0a48843d | 1265 | |
69111bac | 1266 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
0a48843d ME |
1267 | if (!cpuhw->disabled) |
1268 | goto out; | |
1269 | ||
4ea355b5 ME |
1270 | if (cpuhw->n_events == 0) { |
1271 | ppc_set_pmu_inuse(0); | |
1272 | goto out; | |
1273 | } | |
1274 | ||
4574910e PM |
1275 | cpuhw->disabled = 0; |
1276 | ||
330a1eb7 ME |
1277 | /* |
1278 | * EBB requires an exclusive group and all events must have the EBB | |
1279 | * flag set, or not set, so we can just check a single event. Also we | |
1280 | * know we have at least one event. | |
1281 | */ | |
1282 | ebb = is_ebb_event(cpuhw->event[0]); | |
1283 | ||
4574910e | 1284 | /* |
cdd6c482 | 1285 | * If we didn't change anything, or only removed events, |
4574910e PM |
1286 | * no need to recalculate MMCR* settings and reset the PMCs. |
1287 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 1288 | * (possibly updated for removal of events). |
4574910e PM |
1289 | */ |
1290 | if (!cpuhw->n_added) { | |
f708223d | 1291 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 1292 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
f708223d | 1293 | goto out_enable; |
4574910e PM |
1294 | } |
1295 | ||
1296 | /* | |
79a4cb28 | 1297 | * Clear all MMCR settings and recompute them for the new set of events. |
4574910e | 1298 | */ |
79a4cb28 ME |
1299 | memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); |
1300 | ||
cdd6c482 | 1301 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
8abd818f | 1302 | cpuhw->mmcr, cpuhw->event)) { |
4574910e PM |
1303 | /* shouldn't ever get here */ |
1304 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
1305 | goto out; | |
1306 | } | |
1307 | ||
9de5cb0f ME |
1308 | if (!(ppmu->flags & PPMU_ARCH_207S)) { |
1309 | /* | |
1310 | * Add in MMCR0 freeze bits corresponding to the attr.exclude_* | |
1311 | * bits for the first event. We have already checked that all | |
1312 | * events have the same value for these bits as the first event. | |
1313 | */ | |
1314 | event = cpuhw->event[0]; | |
1315 | if (event->attr.exclude_user) | |
1316 | cpuhw->mmcr[0] |= MMCR0_FCP; | |
1317 | if (event->attr.exclude_kernel) | |
1318 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
1319 | if (event->attr.exclude_hv) | |
1320 | cpuhw->mmcr[0] |= MMCR0_FCHV; | |
1321 | } | |
0475f9ea | 1322 | |
4574910e PM |
1323 | /* |
1324 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
1325 | * bit set and set the hardware events to their initial values. |
1326 | * Then unfreeze the events. | |
4574910e | 1327 | */ |
a6dbf93a | 1328 | ppc_set_pmu_inuse(1); |
f708223d | 1329 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
1330 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
1331 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1332 | | MMCR0_FC); | |
9de5cb0f ME |
1333 | if (ppmu->flags & PPMU_ARCH_207S) |
1334 | mtspr(SPRN_MMCR2, cpuhw->mmcr[3]); | |
4574910e PM |
1335 | |
1336 | /* | |
cdd6c482 | 1337 | * Read off any pre-existing events that need to move |
4574910e PM |
1338 | * to another PMC. |
1339 | */ | |
cdd6c482 IM |
1340 | for (i = 0; i < cpuhw->n_events; ++i) { |
1341 | event = cpuhw->event[i]; | |
1342 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
1343 | power_pmu_read(event); | |
1344 | write_pmc(event->hw.idx, 0); | |
1345 | event->hw.idx = 0; | |
4574910e PM |
1346 | } |
1347 | } | |
1348 | ||
1349 | /* | |
cdd6c482 | 1350 | * Initialize the PMCs for all the new and moved events. |
4574910e | 1351 | */ |
ab7ef2e5 | 1352 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
1353 | for (i = 0; i < cpuhw->n_events; ++i) { |
1354 | event = cpuhw->event[i]; | |
1355 | if (event->hw.idx) | |
4574910e | 1356 | continue; |
ab7ef2e5 PM |
1357 | idx = hwc_index[i] + 1; |
1358 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 1359 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
1360 | cpuhw->limited_hwidx[n_lim] = idx; |
1361 | ++n_lim; | |
1362 | continue; | |
1363 | } | |
330a1eb7 ME |
1364 | |
1365 | if (ebb) | |
1366 | val = local64_read(&event->hw.prev_count); | |
1367 | else { | |
1368 | val = 0; | |
1369 | if (event->hw.sample_period) { | |
1370 | left = local64_read(&event->hw.period_left); | |
1371 | if (left < 0x80000000L) | |
1372 | val = 0x80000000L - left; | |
1373 | } | |
1374 | local64_set(&event->hw.prev_count, val); | |
4574910e | 1375 | } |
330a1eb7 | 1376 | |
cdd6c482 | 1377 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1378 | if (event->hw.state & PERF_HES_STOPPED) |
1379 | val = 0; | |
ab7ef2e5 | 1380 | write_pmc(idx, val); |
330a1eb7 | 1381 | |
cdd6c482 | 1382 | perf_event_update_userpage(event); |
4574910e | 1383 | } |
ab7ef2e5 | 1384 | cpuhw->n_limited = n_lim; |
4574910e | 1385 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1386 | |
1387 | out_enable: | |
c2e37a26 ME |
1388 | pmao_restore_workaround(ebb); |
1389 | ||
9de5cb0f | 1390 | mmcr0 = ebb_switch_in(ebb, cpuhw); |
330a1eb7 | 1391 | |
f708223d | 1392 | mb(); |
b4d6c06c AK |
1393 | if (cpuhw->bhrb_users) |
1394 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1395 | ||
330a1eb7 | 1396 | write_mmcr0(cpuhw, mmcr0); |
4574910e | 1397 | |
f708223d PM |
1398 | /* |
1399 | * Enable instruction sampling if necessary | |
1400 | */ | |
1401 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1402 | mb(); | |
1403 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1404 | } | |
1405 | ||
4574910e | 1406 | out: |
3925f46b | 1407 | |
4574910e PM |
1408 | local_irq_restore(flags); |
1409 | } | |
1410 | ||
cdd6c482 IM |
1411 | static int collect_events(struct perf_event *group, int max_count, |
1412 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1413 | unsigned int *flags) |
4574910e PM |
1414 | { |
1415 | int n = 0; | |
cdd6c482 | 1416 | struct perf_event *event; |
4574910e | 1417 | |
cdd6c482 | 1418 | if (!is_software_event(group)) { |
4574910e PM |
1419 | if (n >= max_count) |
1420 | return -1; | |
1421 | ctrs[n] = group; | |
cdd6c482 | 1422 | flags[n] = group->hw.event_base; |
4574910e PM |
1423 | events[n++] = group->hw.config; |
1424 | } | |
a8f90e90 | 1425 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1426 | if (!is_software_event(event) && |
1427 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1428 | if (n >= max_count) |
1429 | return -1; | |
cdd6c482 IM |
1430 | ctrs[n] = event; |
1431 | flags[n] = event->hw.event_base; | |
1432 | events[n++] = event->hw.config; | |
4574910e PM |
1433 | } |
1434 | } | |
1435 | return n; | |
1436 | } | |
1437 | ||
4574910e | 1438 | /* |
cdd6c482 IM |
1439 | * Add a event to the PMU. |
1440 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1441 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1442 | * actual work of reconfiguring the PMU. |
1443 | */ | |
a4eaf7f1 | 1444 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1445 | { |
cdd6c482 | 1446 | struct cpu_hw_events *cpuhw; |
4574910e | 1447 | unsigned long flags; |
4574910e PM |
1448 | int n0; |
1449 | int ret = -EAGAIN; | |
1450 | ||
1451 | local_irq_save(flags); | |
33696fc0 | 1452 | perf_pmu_disable(event->pmu); |
4574910e PM |
1453 | |
1454 | /* | |
cdd6c482 | 1455 | * Add the event to the list (if there is room) |
4574910e PM |
1456 | * and check whether the total set is still feasible. |
1457 | */ | |
69111bac | 1458 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1459 | n0 = cpuhw->n_events; |
a8f90e90 | 1460 | if (n0 >= ppmu->n_counter) |
4574910e | 1461 | goto out; |
cdd6c482 IM |
1462 | cpuhw->event[n0] = event; |
1463 | cpuhw->events[n0] = event->hw.config; | |
1464 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1465 | |
f53d168c | 1466 | /* |
1467 | * This event may have been disabled/stopped in record_and_restart() | |
1468 | * because we exceeded the ->event_limit. If re-starting the event, | |
1469 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1470 | * notification is re-enabled. | |
1471 | */ | |
a4eaf7f1 PZ |
1472 | if (!(ef_flags & PERF_EF_START)) |
1473 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1474 | else |
1475 | event->hw.state = 0; | |
a4eaf7f1 | 1476 | |
8e6d5573 LM |
1477 | /* |
1478 | * If group events scheduling transaction was started, | |
25985edc | 1479 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1480 | * at commit time(->commit_txn) as a whole |
1481 | */ | |
8f3e5684 | 1482 | if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) |
8e6d5573 LM |
1483 | goto nocheck; |
1484 | ||
cdd6c482 | 1485 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1486 | goto out; |
e51ee31e | 1487 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1488 | goto out; |
cdd6c482 | 1489 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1490 | |
1491 | nocheck: | |
330a1eb7 ME |
1492 | ebb_event_add(event); |
1493 | ||
cdd6c482 | 1494 | ++cpuhw->n_events; |
4574910e PM |
1495 | ++cpuhw->n_added; |
1496 | ||
1497 | ret = 0; | |
1498 | out: | |
ff3d79dc | 1499 | if (has_branch_stack(event)) { |
3925f46b | 1500 | power_pmu_bhrb_enable(event); |
ff3d79dc AK |
1501 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( |
1502 | event->attr.branch_sample_type); | |
1503 | } | |
3925f46b | 1504 | |
356d8ce3 MS |
1505 | /* |
1506 | * Workaround for POWER9 DD1 to use the Instruction Counter | |
1507 | * register value for instruction counting | |
1508 | */ | |
1509 | if (use_ic(event->attr.config)) | |
1510 | cpuhw->ic_init = mfspr(SPRN_IC); | |
1511 | ||
33696fc0 | 1512 | perf_pmu_enable(event->pmu); |
4574910e PM |
1513 | local_irq_restore(flags); |
1514 | return ret; | |
1515 | } | |
1516 | ||
1517 | /* | |
cdd6c482 | 1518 | * Remove a event from the PMU. |
4574910e | 1519 | */ |
a4eaf7f1 | 1520 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1521 | { |
cdd6c482 | 1522 | struct cpu_hw_events *cpuhw; |
4574910e | 1523 | long i; |
4574910e PM |
1524 | unsigned long flags; |
1525 | ||
1526 | local_irq_save(flags); | |
33696fc0 | 1527 | perf_pmu_disable(event->pmu); |
4574910e | 1528 | |
cdd6c482 IM |
1529 | power_pmu_read(event); |
1530 | ||
69111bac | 1531 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 IM |
1532 | for (i = 0; i < cpuhw->n_events; ++i) { |
1533 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1534 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1535 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1536 | cpuhw->events[i-1] = cpuhw->events[i]; |
1537 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1538 | } | |
cdd6c482 IM |
1539 | --cpuhw->n_events; |
1540 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1541 | if (event->hw.idx) { | |
1542 | write_pmc(event->hw.idx, 0); | |
1543 | event->hw.idx = 0; | |
ab7ef2e5 | 1544 | } |
cdd6c482 | 1545 | perf_event_update_userpage(event); |
4574910e PM |
1546 | break; |
1547 | } | |
1548 | } | |
ab7ef2e5 | 1549 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1550 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1551 | break; |
1552 | if (i < cpuhw->n_limited) { | |
1553 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1554 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1555 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1556 | } | |
1557 | --cpuhw->n_limited; | |
1558 | } | |
cdd6c482 IM |
1559 | if (cpuhw->n_events == 0) { |
1560 | /* disable exceptions if no events are running */ | |
4574910e PM |
1561 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1562 | } | |
1563 | ||
3925f46b AK |
1564 | if (has_branch_stack(event)) |
1565 | power_pmu_bhrb_disable(event); | |
1566 | ||
33696fc0 | 1567 | perf_pmu_enable(event->pmu); |
4574910e PM |
1568 | local_irq_restore(flags); |
1569 | } | |
1570 | ||
8a7b8cb9 | 1571 | /* |
a4eaf7f1 PZ |
1572 | * POWER-PMU does not support disabling individual counters, hence |
1573 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1574 | */ |
a4eaf7f1 PZ |
1575 | |
1576 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1577 | { |
8a7b8cb9 | 1578 | unsigned long flags; |
a4eaf7f1 | 1579 | s64 left; |
9a45a940 | 1580 | unsigned long val; |
8a7b8cb9 | 1581 | |
cdd6c482 | 1582 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1583 | return; |
a4eaf7f1 PZ |
1584 | |
1585 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1586 | return; | |
1587 | ||
1588 | if (ef_flags & PERF_EF_RELOAD) | |
1589 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1590 | ||
1591 | local_irq_save(flags); | |
1592 | perf_pmu_disable(event->pmu); | |
1593 | ||
1594 | event->hw.state = 0; | |
1595 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1596 | |
1597 | val = 0; | |
1598 | if (left < 0x80000000L) | |
1599 | val = 0x80000000L - left; | |
1600 | ||
1601 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1602 | |
1603 | perf_event_update_userpage(event); | |
1604 | perf_pmu_enable(event->pmu); | |
1605 | local_irq_restore(flags); | |
1606 | } | |
1607 | ||
1608 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1609 | { | |
1610 | unsigned long flags; | |
1611 | ||
1612 | if (!event->hw.idx || !event->hw.sample_period) | |
1613 | return; | |
1614 | ||
1615 | if (event->hw.state & PERF_HES_STOPPED) | |
1616 | return; | |
1617 | ||
8a7b8cb9 | 1618 | local_irq_save(flags); |
33696fc0 | 1619 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1620 | |
cdd6c482 | 1621 | power_pmu_read(event); |
a4eaf7f1 PZ |
1622 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1623 | write_pmc(event->hw.idx, 0); | |
1624 | ||
cdd6c482 | 1625 | perf_event_update_userpage(event); |
33696fc0 | 1626 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1627 | local_irq_restore(flags); |
1628 | } | |
1629 | ||
8e6d5573 LM |
1630 | /* |
1631 | * Start group events scheduling transaction | |
1632 | * Set the flag to make pmu::enable() not perform the | |
1633 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
1634 | * |
1635 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
1636 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
1637 | * transactions. | |
8e6d5573 | 1638 | */ |
fbbe0701 | 1639 | static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
8e6d5573 | 1640 | { |
69111bac | 1641 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
8e6d5573 | 1642 | |
fbbe0701 SB |
1643 | WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ |
1644 | ||
1645 | cpuhw->txn_flags = txn_flags; | |
1646 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1647 | return; | |
1648 | ||
33696fc0 | 1649 | perf_pmu_disable(pmu); |
8e6d5573 LM |
1650 | cpuhw->n_txn_start = cpuhw->n_events; |
1651 | } | |
1652 | ||
1653 | /* | |
1654 | * Stop group events scheduling transaction | |
1655 | * Clear the flag and pmu::enable() will perform the | |
1656 | * schedulability test. | |
1657 | */ | |
e51df2c1 | 1658 | static void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 | 1659 | { |
69111bac | 1660 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
fbbe0701 SB |
1661 | unsigned int txn_flags; |
1662 | ||
1663 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ | |
1664 | ||
1665 | txn_flags = cpuhw->txn_flags; | |
1666 | cpuhw->txn_flags = 0; | |
1667 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1668 | return; | |
8e6d5573 | 1669 | |
33696fc0 | 1670 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1671 | } |
1672 | ||
1673 | /* | |
1674 | * Commit group events scheduling transaction | |
1675 | * Perform the group schedulability test as a whole | |
1676 | * Return 0 if success | |
1677 | */ | |
e51df2c1 | 1678 | static int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1679 | { |
1680 | struct cpu_hw_events *cpuhw; | |
1681 | long i, n; | |
1682 | ||
1683 | if (!ppmu) | |
1684 | return -EAGAIN; | |
fbbe0701 | 1685 | |
69111bac | 1686 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
fbbe0701 SB |
1687 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ |
1688 | ||
1689 | if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { | |
1690 | cpuhw->txn_flags = 0; | |
1691 | return 0; | |
1692 | } | |
1693 | ||
8e6d5573 LM |
1694 | n = cpuhw->n_events; |
1695 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1696 | return -EAGAIN; | |
1697 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1698 | if (i < 0) | |
1699 | return -EAGAIN; | |
1700 | ||
1701 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1702 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1703 | ||
fbbe0701 | 1704 | cpuhw->txn_flags = 0; |
33696fc0 | 1705 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1706 | return 0; |
1707 | } | |
1708 | ||
ab7ef2e5 | 1709 | /* |
cdd6c482 | 1710 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1711 | * or 0 if not. |
cdd6c482 | 1712 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1713 | * that a limited PMC can count, doesn't require interrupts, and |
1714 | * doesn't exclude any processor mode. | |
1715 | */ | |
cdd6c482 | 1716 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1717 | unsigned int flags) |
1718 | { | |
1719 | int n; | |
ef923214 | 1720 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1721 | |
cdd6c482 IM |
1722 | if (event->attr.exclude_user |
1723 | || event->attr.exclude_kernel | |
1724 | || event->attr.exclude_hv | |
1725 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1726 | return 0; |
1727 | ||
1728 | if (ppmu->limited_pmc_event(ev)) | |
1729 | return 1; | |
1730 | ||
1731 | /* | |
cdd6c482 | 1732 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1733 | * see if any alternative code goes on a limited PMC. |
1734 | */ | |
1735 | if (!ppmu->get_alternatives) | |
1736 | return 0; | |
1737 | ||
1738 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1739 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1740 | |
ef923214 | 1741 | return n > 0; |
ab7ef2e5 PM |
1742 | } |
1743 | ||
1744 | /* | |
cdd6c482 IM |
1745 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1746 | * and return the event_id code, or 0 if there is no such alternative. | |
1747 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1748 | */ |
ef923214 | 1749 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1750 | { |
ef923214 | 1751 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1752 | int n; |
1753 | ||
1754 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1755 | n = ppmu->get_alternatives(ev, flags, alt); | |
1756 | if (!n) | |
1757 | return 0; | |
1758 | return alt[0]; | |
1759 | } | |
1760 | ||
cdd6c482 IM |
1761 | /* Number of perf_events counting hardware events */ |
1762 | static atomic_t num_events; | |
7595d63b PM |
1763 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1764 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1765 | ||
1766 | /* | |
cdd6c482 | 1767 | * Release the PMU if this is the last perf_event. |
7595d63b | 1768 | */ |
cdd6c482 | 1769 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1770 | { |
cdd6c482 | 1771 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1772 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1773 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1774 | release_pmc_hardware(); |
1775 | mutex_unlock(&pmc_reserve_mutex); | |
1776 | } | |
1777 | } | |
1778 | ||
106b506c | 1779 | /* |
cdd6c482 | 1780 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1781 | */ |
1782 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1783 | { | |
1784 | unsigned long type, op, result; | |
1785 | int ev; | |
1786 | ||
1787 | if (!ppmu->cache_events) | |
1788 | return -EINVAL; | |
1789 | ||
1790 | /* unpack config */ | |
1791 | type = config & 0xff; | |
1792 | op = (config >> 8) & 0xff; | |
1793 | result = (config >> 16) & 0xff; | |
1794 | ||
1795 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1796 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1797 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1798 | return -EINVAL; | |
1799 | ||
1800 | ev = (*ppmu->cache_events)[type][op][result]; | |
1801 | if (ev == 0) | |
1802 | return -EOPNOTSUPP; | |
1803 | if (ev == -1) | |
1804 | return -EINVAL; | |
1805 | *eventp = ev; | |
1806 | return 0; | |
1807 | } | |
1808 | ||
b0a873eb | 1809 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1810 | { |
ef923214 PM |
1811 | u64 ev; |
1812 | unsigned long flags; | |
cdd6c482 IM |
1813 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1814 | u64 events[MAX_HWEVENTS]; | |
1815 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1816 | int n; |
7595d63b | 1817 | int err; |
cdd6c482 | 1818 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1819 | |
1820 | if (!ppmu) | |
b0a873eb PZ |
1821 | return -ENOENT; |
1822 | ||
3925f46b AK |
1823 | if (has_branch_stack(event)) { |
1824 | /* PMU has BHRB enabled */ | |
4d9690dd | 1825 | if (!(ppmu->flags & PPMU_ARCH_207S)) |
3925f46b AK |
1826 | return -EOPNOTSUPP; |
1827 | } | |
2481c5fa | 1828 | |
cdd6c482 | 1829 | switch (event->attr.type) { |
106b506c | 1830 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1831 | ev = event->attr.config; |
9aaa131a | 1832 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1833 | return -EOPNOTSUPP; |
4574910e | 1834 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1835 | break; |
1836 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1837 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1838 | if (err) |
b0a873eb | 1839 | return err; |
106b506c PM |
1840 | break; |
1841 | case PERF_TYPE_RAW: | |
cdd6c482 | 1842 | ev = event->attr.config; |
106b506c | 1843 | break; |
90c8f954 | 1844 | default: |
b0a873eb | 1845 | return -ENOENT; |
4574910e | 1846 | } |
b0a873eb | 1847 | |
cdd6c482 IM |
1848 | event->hw.config_base = ev; |
1849 | event->hw.idx = 0; | |
4574910e | 1850 | |
0475f9ea PM |
1851 | /* |
1852 | * If we are not running on a hypervisor, force the | |
1853 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1854 | * the user set it to. |
0475f9ea PM |
1855 | */ |
1856 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1857 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1858 | |
1859 | /* | |
cdd6c482 | 1860 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1861 | * PM_RUN_* events interchangeably with their non RUN_* |
1862 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1863 | * XXX we should check if the task is an idle task. | |
1864 | */ | |
1865 | flags = 0; | |
57fa7214 | 1866 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1867 | flags |= PPMU_ONLY_COUNT_RUN; |
1868 | ||
1869 | /* | |
cdd6c482 IM |
1870 | * If this machine has limited events, check whether this |
1871 | * event_id could go on a limited event. | |
ab7ef2e5 | 1872 | */ |
0bbd0d4b | 1873 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1874 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1875 | flags |= PPMU_LIMITED_PMC_OK; |
1876 | } else if (ppmu->limited_pmc_event(ev)) { | |
1877 | /* | |
cdd6c482 | 1878 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1879 | * but we can't use a limited PMC; see if any |
1880 | * alternative goes on a normal PMC. | |
1881 | */ | |
1882 | ev = normal_pmc_alternative(ev, flags); | |
1883 | if (!ev) | |
b0a873eb | 1884 | return -EINVAL; |
ab7ef2e5 PM |
1885 | } |
1886 | } | |
1887 | ||
330a1eb7 ME |
1888 | /* Extra checks for EBB */ |
1889 | err = ebb_event_check(event); | |
1890 | if (err) | |
1891 | return err; | |
1892 | ||
4574910e PM |
1893 | /* |
1894 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1895 | * other hardware events in the group. We assume the event |
4574910e PM |
1896 | * hasn't been linked into its leader's sibling list at this point. |
1897 | */ | |
1898 | n = 0; | |
cdd6c482 | 1899 | if (event->group_leader != event) { |
a8f90e90 | 1900 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1901 | ctrs, events, cflags); |
4574910e | 1902 | if (n < 0) |
b0a873eb | 1903 | return -EINVAL; |
4574910e | 1904 | } |
0475f9ea | 1905 | events[n] = ev; |
cdd6c482 | 1906 | ctrs[n] = event; |
ab7ef2e5 PM |
1907 | cflags[n] = flags; |
1908 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1909 | return -EINVAL; |
e51ee31e | 1910 | |
cdd6c482 | 1911 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1912 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1913 | |
1914 | if (has_branch_stack(event)) { | |
1915 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1916 | event->attr.branch_sample_type); | |
1917 | ||
68de8867 JS |
1918 | if (cpuhw->bhrb_filter == -1) { |
1919 | put_cpu_var(cpu_hw_events); | |
3925f46b | 1920 | return -EOPNOTSUPP; |
68de8867 | 1921 | } |
3925f46b AK |
1922 | } |
1923 | ||
cdd6c482 | 1924 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1925 | if (err) |
b0a873eb | 1926 | return -EINVAL; |
4574910e | 1927 | |
cdd6c482 IM |
1928 | event->hw.config = events[n]; |
1929 | event->hw.event_base = cflags[n]; | |
1930 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1931 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b | 1932 | |
330a1eb7 ME |
1933 | /* |
1934 | * For EBB events we just context switch the PMC value, we don't do any | |
1935 | * of the sample_period logic. We use hw.prev_count for this. | |
1936 | */ | |
1937 | if (is_ebb_event(event)) | |
1938 | local64_set(&event->hw.prev_count, 0); | |
1939 | ||
7595d63b PM |
1940 | /* |
1941 | * See if we need to reserve the PMU. | |
cdd6c482 | 1942 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1943 | * mutex to ensure that we don't race with another task doing |
1944 | * reserve_pmc_hardware or release_pmc_hardware. | |
1945 | */ | |
1946 | err = 0; | |
cdd6c482 | 1947 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1948 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1949 | if (atomic_read(&num_events) == 0 && |
1950 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1951 | err = -EBUSY; |
1952 | else | |
cdd6c482 | 1953 | atomic_inc(&num_events); |
7595d63b PM |
1954 | mutex_unlock(&pmc_reserve_mutex); |
1955 | } | |
cdd6c482 | 1956 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1957 | |
b0a873eb | 1958 | return err; |
4574910e PM |
1959 | } |
1960 | ||
35edc2a5 PZ |
1961 | static int power_pmu_event_idx(struct perf_event *event) |
1962 | { | |
1963 | return event->hw.idx; | |
1964 | } | |
1965 | ||
1c53a270 SB |
1966 | ssize_t power_events_sysfs_show(struct device *dev, |
1967 | struct device_attribute *attr, char *page) | |
1968 | { | |
1969 | struct perf_pmu_events_attr *pmu_attr; | |
1970 | ||
1971 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1972 | ||
1973 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1974 | } | |
1975 | ||
e51df2c1 | 1976 | static struct pmu power_pmu = { |
a4eaf7f1 PZ |
1977 | .pmu_enable = power_pmu_enable, |
1978 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1979 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1980 | .add = power_pmu_add, |
1981 | .del = power_pmu_del, | |
1982 | .start = power_pmu_start, | |
1983 | .stop = power_pmu_stop, | |
b0a873eb | 1984 | .read = power_pmu_read, |
b0a873eb PZ |
1985 | .start_txn = power_pmu_start_txn, |
1986 | .cancel_txn = power_pmu_cancel_txn, | |
1987 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1988 | .event_idx = power_pmu_event_idx, |
acba3c7e | 1989 | .sched_task = power_pmu_sched_task, |
b0a873eb PZ |
1990 | }; |
1991 | ||
4574910e | 1992 | /* |
57c0c15b | 1993 | * A counter has overflowed; update its count and record |
4574910e PM |
1994 | * things if requested. Note that interrupts are hard-disabled |
1995 | * here so there is no possibility of being interrupted. | |
1996 | */ | |
cdd6c482 | 1997 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1998 | struct pt_regs *regs) |
4574910e | 1999 | { |
cdd6c482 | 2000 | u64 period = event->hw.sample_period; |
4574910e PM |
2001 | s64 prev, delta, left; |
2002 | int record = 0; | |
2003 | ||
a4eaf7f1 PZ |
2004 | if (event->hw.state & PERF_HES_STOPPED) { |
2005 | write_pmc(event->hw.idx, 0); | |
2006 | return; | |
2007 | } | |
2008 | ||
4574910e | 2009 | /* we don't have to worry about interrupts here */ |
e7850595 | 2010 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 2011 | delta = check_and_compute_delta(prev, val); |
e7850595 | 2012 | local64_add(delta, &event->count); |
4574910e PM |
2013 | |
2014 | /* | |
cdd6c482 | 2015 | * See if the total period for this event has expired, |
4574910e PM |
2016 | * and update for the next period. |
2017 | */ | |
2018 | val = 0; | |
e7850595 | 2019 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
2020 | if (delta == 0) |
2021 | left++; | |
60db5e09 | 2022 | if (period) { |
4574910e | 2023 | if (left <= 0) { |
60db5e09 | 2024 | left += period; |
4574910e | 2025 | if (left <= 0) |
60db5e09 | 2026 | left = period; |
e6878835 | 2027 | record = siar_valid(regs); |
4bca770e | 2028 | event->hw.last_period = event->hw.sample_period; |
4574910e | 2029 | } |
98fb1807 PM |
2030 | if (left < 0x80000000LL) |
2031 | val = 0x80000000LL - left; | |
4574910e | 2032 | } |
4574910e | 2033 | |
a4eaf7f1 PZ |
2034 | write_pmc(event->hw.idx, val); |
2035 | local64_set(&event->hw.prev_count, val); | |
2036 | local64_set(&event->hw.period_left, left); | |
2037 | perf_event_update_userpage(event); | |
2038 | ||
4574910e PM |
2039 | /* |
2040 | * Finally record data if requested. | |
2041 | */ | |
0bbd0d4b | 2042 | if (record) { |
dc1d628a PZ |
2043 | struct perf_sample_data data; |
2044 | ||
fd0d000b | 2045 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 2046 | |
fc7ce9c7 KL |
2047 | if (event->attr.sample_type & |
2048 | (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) | |
98fb1807 PM |
2049 | perf_get_data_addr(regs, &data.addr); |
2050 | ||
3925f46b AK |
2051 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
2052 | struct cpu_hw_events *cpuhw; | |
69111bac | 2053 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
3925f46b AK |
2054 | power_pmu_bhrb_read(cpuhw); |
2055 | data.br_stack = &cpuhw->bhrb_stack; | |
2056 | } | |
2057 | ||
79e96f8f MS |
2058 | if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && |
2059 | ppmu->get_mem_data_src) | |
2060 | ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs); | |
2061 | ||
170a315f MS |
2062 | if (event->attr.sample_type & PERF_SAMPLE_WEIGHT && |
2063 | ppmu->get_mem_weight) | |
2064 | ppmu->get_mem_weight(&data.weight); | |
2065 | ||
a8b0ca17 | 2066 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 2067 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
2068 | } |
2069 | } | |
2070 | ||
2071 | /* | |
2072 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 2073 | * for an event_id. |
0bbd0d4b PM |
2074 | */ |
2075 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2076 | { | |
98fb1807 | 2077 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 2078 | |
98fb1807 PM |
2079 | if (flags) |
2080 | return flags; | |
cdd6c482 IM |
2081 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
2082 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
2083 | } |
2084 | ||
2085 | /* | |
2086 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 2087 | * for an event_id. |
0bbd0d4b PM |
2088 | */ |
2089 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
2090 | { | |
33904054 | 2091 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 2092 | |
e6878835 | 2093 | if (use_siar && siar_valid(regs)) |
75382aa7 | 2094 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 2095 | else if (use_siar) |
2096 | return 0; // no valid instruction pointer | |
75382aa7 | 2097 | else |
1ce447b9 | 2098 | return regs->nip; |
4574910e PM |
2099 | } |
2100 | ||
bc09c219 | 2101 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 2102 | { |
0837e324 AB |
2103 | /* |
2104 | * Events on POWER7 can roll back if a speculative event doesn't | |
2105 | * eventually complete. Unfortunately in some rare cases they will | |
2106 | * raise a performance monitor exception. We need to catch this to | |
2107 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
2108 | * cycles from overflow. | |
2109 | * | |
2110 | * We only do this if the first pass fails to find any overflowing | |
2111 | * PMCs because a user might set a period of less than 256 and we | |
2112 | * don't want to mistakenly reset them. | |
2113 | */ | |
bc09c219 MN |
2114 | if ((0x80000000 - val) <= 256) |
2115 | return true; | |
2116 | ||
2117 | return false; | |
2118 | } | |
2119 | ||
2120 | static bool pmc_overflow(unsigned long val) | |
2121 | { | |
2122 | if ((int)val < 0) | |
0837e324 AB |
2123 | return true; |
2124 | ||
2125 | return false; | |
2126 | } | |
2127 | ||
4574910e PM |
2128 | /* |
2129 | * Performance monitor interrupt stuff | |
2130 | */ | |
cdd6c482 | 2131 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 2132 | { |
bc09c219 | 2133 | int i, j; |
69111bac | 2134 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 2135 | struct perf_event *event; |
bc09c219 MN |
2136 | unsigned long val[8]; |
2137 | int found, active; | |
ca8f2d7f PM |
2138 | int nmi; |
2139 | ||
ab7ef2e5 | 2140 | if (cpuhw->n_limited) |
a8f90e90 | 2141 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
2142 | mfspr(SPRN_PMC6)); |
2143 | ||
98fb1807 | 2144 | perf_read_regs(regs); |
0bbd0d4b | 2145 | |
98fb1807 | 2146 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
2147 | if (nmi) |
2148 | nmi_enter(); | |
2149 | else | |
2150 | irq_enter(); | |
4574910e | 2151 | |
bc09c219 MN |
2152 | /* Read all the PMCs since we'll need them a bunch of times */ |
2153 | for (i = 0; i < ppmu->n_counter; ++i) | |
2154 | val[i] = read_pmc(i + 1); | |
2155 | ||
2156 | /* Try to find what caused the IRQ */ | |
2157 | found = 0; | |
2158 | for (i = 0; i < ppmu->n_counter; ++i) { | |
2159 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 2160 | continue; |
bc09c219 MN |
2161 | if (is_limited_pmc(i + 1)) |
2162 | continue; /* these won't generate IRQs */ | |
2163 | /* | |
2164 | * We've found one that's overflowed. For active | |
2165 | * counters we need to log this. For inactive | |
2166 | * counters, we need to reset it anyway | |
2167 | */ | |
2168 | found = 1; | |
2169 | active = 0; | |
2170 | for (j = 0; j < cpuhw->n_events; ++j) { | |
2171 | event = cpuhw->event[j]; | |
2172 | if (event->hw.idx == (i + 1)) { | |
2173 | active = 1; | |
2174 | record_and_restart(event, val[i], regs); | |
2175 | break; | |
2176 | } | |
4574910e | 2177 | } |
bc09c219 MN |
2178 | if (!active) |
2179 | /* reset non active counters that have overflowed */ | |
2180 | write_pmc(i + 1, 0); | |
4574910e | 2181 | } |
bc09c219 MN |
2182 | if (!found && pvr_version_is(PVR_POWER7)) { |
2183 | /* check active counters for special buggy p7 overflow */ | |
2184 | for (i = 0; i < cpuhw->n_events; ++i) { | |
2185 | event = cpuhw->event[i]; | |
2186 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 2187 | continue; |
bc09c219 MN |
2188 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
2189 | /* event has overflowed in a buggy way*/ | |
2190 | found = 1; | |
2191 | record_and_restart(event, | |
2192 | val[event->hw.idx - 1], | |
2193 | regs); | |
2194 | } | |
4574910e PM |
2195 | } |
2196 | } | |
6772faa1 | 2197 | if (!found && !nmi && printk_ratelimit()) |
bc09c219 | 2198 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
4574910e PM |
2199 | |
2200 | /* | |
2201 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 2202 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 2203 | * and thus allow interrupts to occur again. |
cdd6c482 | 2204 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
2205 | * we get back out of this interrupt. |
2206 | */ | |
ab7ef2e5 | 2207 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 2208 | |
ca8f2d7f PM |
2209 | if (nmi) |
2210 | nmi_exit(); | |
2211 | else | |
db4fb5ac | 2212 | irq_exit(); |
4574910e PM |
2213 | } |
2214 | ||
7c98bd72 | 2215 | static int power_pmu_prepare_cpu(unsigned int cpu) |
01d0287f | 2216 | { |
cdd6c482 | 2217 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 2218 | |
57ecde42 TG |
2219 | if (ppmu) { |
2220 | memset(cpuhw, 0, sizeof(*cpuhw)); | |
2221 | cpuhw->mmcr[0] = MMCR0_FC; | |
3f6da390 | 2222 | } |
57ecde42 | 2223 | return 0; |
3f6da390 PZ |
2224 | } |
2225 | ||
061d19f2 | 2226 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 2227 | { |
079b3c56 PM |
2228 | if (ppmu) |
2229 | return -EBUSY; /* something's already registered */ | |
2230 | ||
2231 | ppmu = pmu; | |
2232 | pr_info("%s performance monitor hardware support registered\n", | |
2233 | pmu->name); | |
d095cd46 | 2234 | |
1c53a270 SB |
2235 | power_pmu.attr_groups = ppmu->attr_groups; |
2236 | ||
98fb1807 | 2237 | #ifdef MSR_HV |
d095cd46 PM |
2238 | /* |
2239 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
2240 | */ | |
2241 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 2242 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 2243 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 2244 | |
2e80a82a | 2245 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
73c1b41e | 2246 | cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", |
57ecde42 | 2247 | power_pmu_prepare_cpu, NULL); |
4574910e PM |
2248 | return 0; |
2249 | } |