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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
b0d436c7 | 27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL |
3925f46b | 28 | |
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 39 | unsigned long mmcr[3]; |
a8f90e90 PM |
40 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
41 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
42 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
43 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
44 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
45 | |
46 | unsigned int group_flag; | |
47 | int n_txn_start; | |
3925f46b AK |
48 | |
49 | /* BHRB bits */ | |
50 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
51 | int bhrb_users; | |
52 | void *bhrb_context; | |
53 | struct perf_branch_stack bhrb_stack; | |
54 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 55 | }; |
3925f46b | 56 | |
cdd6c482 | 57 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
58 | |
59 | struct power_pmu *ppmu; | |
60 | ||
d095cd46 | 61 | /* |
57c0c15b | 62 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
63 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
64 | * hypervisor bit set in the MSR, or if we are running on a processor | |
65 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
66 | * then we need to use the FCHV bit to ignore kernel events. | |
67 | */ | |
cdd6c482 | 68 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 69 | |
98fb1807 PM |
70 | /* |
71 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
72 | * and a few other names are different. | |
73 | */ | |
74 | #ifdef CONFIG_PPC32 | |
75 | ||
76 | #define MMCR0_FCHV 0 | |
77 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
7a7a41f9 | 78 | #define MMCR0_FC56 0 |
378a6ee9 | 79 | #define MMCR0_PMAO 0 |
330a1eb7 ME |
80 | #define MMCR0_EBE 0 |
81 | #define MMCR0_PMCC 0 | |
82 | #define MMCR0_PMCC_U6 0 | |
98fb1807 PM |
83 | |
84 | #define SPRN_MMCRA SPRN_MMCR2 | |
85 | #define MMCRA_SAMPLE_ENABLE 0 | |
86 | ||
87 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
88 | { | |
89 | return 0; | |
90 | } | |
98fb1807 PM |
91 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
92 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
93 | { | |
94 | return 0; | |
95 | } | |
75382aa7 AB |
96 | static inline void perf_read_regs(struct pt_regs *regs) |
97 | { | |
98 | regs->result = 0; | |
99 | } | |
98fb1807 PM |
100 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
101 | { | |
102 | return 0; | |
103 | } | |
104 | ||
e6878835 | 105 | static inline int siar_valid(struct pt_regs *regs) |
106 | { | |
107 | return 1; | |
108 | } | |
109 | ||
330a1eb7 ME |
110 | static bool is_ebb_event(struct perf_event *event) { return false; } |
111 | static int ebb_event_check(struct perf_event *event) { return 0; } | |
112 | static void ebb_event_add(struct perf_event *event) { } | |
113 | static void ebb_switch_out(unsigned long mmcr0) { } | |
114 | static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0) | |
115 | { | |
116 | return mmcr0; | |
117 | } | |
118 | ||
d52f2dc4 MN |
119 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
120 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
121 | void power_pmu_flush_branch_stack(void) {} | |
122 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} | |
98fb1807 PM |
123 | #endif /* CONFIG_PPC32 */ |
124 | ||
33904054 ME |
125 | static bool regs_use_siar(struct pt_regs *regs) |
126 | { | |
cbda6aa1 | 127 | return !!regs->result; |
33904054 ME |
128 | } |
129 | ||
98fb1807 PM |
130 | /* |
131 | * Things that are specific to 64-bit implementations. | |
132 | */ | |
133 | #ifdef CONFIG_PPC64 | |
134 | ||
135 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
136 | { | |
137 | unsigned long mmcra = regs->dsisr; | |
138 | ||
7a786832 | 139 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
140 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
141 | if (slot > 1) | |
142 | return 4 * (slot - 1); | |
143 | } | |
7a786832 | 144 | |
98fb1807 PM |
145 | return 0; |
146 | } | |
147 | ||
98fb1807 PM |
148 | /* |
149 | * The user wants a data address recorded. | |
150 | * If we're not doing instruction sampling, give them the SDAR | |
151 | * (sampled data address). If we are doing instruction sampling, then | |
152 | * only give them the SDAR if it corresponds to the instruction | |
58a032c3 ME |
153 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the |
154 | * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. | |
98fb1807 PM |
155 | */ |
156 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
157 | { | |
158 | unsigned long mmcra = regs->dsisr; | |
58a032c3 | 159 | bool sdar_valid; |
e6878835 | 160 | |
58a032c3 ME |
161 | if (ppmu->flags & PPMU_HAS_SIER) |
162 | sdar_valid = regs->dar & SIER_SDAR_VALID; | |
163 | else { | |
164 | unsigned long sdsync; | |
165 | ||
166 | if (ppmu->flags & PPMU_SIAR_VALID) | |
167 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
168 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
169 | sdsync = POWER6_MMCRA_SDSYNC; | |
170 | else | |
171 | sdsync = MMCRA_SDSYNC; | |
172 | ||
173 | sdar_valid = mmcra & sdsync; | |
174 | } | |
98fb1807 | 175 | |
58a032c3 | 176 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) |
98fb1807 PM |
177 | *addrp = mfspr(SPRN_SDAR); |
178 | } | |
179 | ||
5682c460 | 180 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
181 | { |
182 | unsigned long sihv = MMCRA_SIHV; | |
183 | ||
8f61aa32 ME |
184 | if (ppmu->flags & PPMU_HAS_SIER) |
185 | return !!(regs->dar & SIER_SIHV); | |
186 | ||
68b30bb9 AB |
187 | if (ppmu->flags & PPMU_ALT_SIPR) |
188 | sihv = POWER6_MMCRA_SIHV; | |
189 | ||
5682c460 | 190 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
191 | } |
192 | ||
5682c460 | 193 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
194 | { |
195 | unsigned long sipr = MMCRA_SIPR; | |
196 | ||
8f61aa32 ME |
197 | if (ppmu->flags & PPMU_HAS_SIER) |
198 | return !!(regs->dar & SIER_SIPR); | |
199 | ||
68b30bb9 AB |
200 | if (ppmu->flags & PPMU_ALT_SIPR) |
201 | sipr = POWER6_MMCRA_SIPR; | |
202 | ||
5682c460 | 203 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
204 | } |
205 | ||
1ce447b9 BH |
206 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
207 | { | |
208 | if (regs->msr & MSR_PR) | |
209 | return PERF_RECORD_MISC_USER; | |
210 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
211 | return PERF_RECORD_MISC_HYPERVISOR; | |
212 | return PERF_RECORD_MISC_KERNEL; | |
213 | } | |
214 | ||
98fb1807 PM |
215 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
216 | { | |
33904054 | 217 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 218 | |
75382aa7 | 219 | if (!use_siar) |
1ce447b9 BH |
220 | return perf_flags_from_msr(regs); |
221 | ||
222 | /* | |
223 | * If we don't have flags in MMCRA, rather than using | |
224 | * the MSR, we intuit the flags from the address in | |
225 | * SIAR which should give slightly more reliable | |
226 | * results | |
227 | */ | |
cbda6aa1 | 228 | if (ppmu->flags & PPMU_NO_SIPR) { |
1ce447b9 BH |
229 | unsigned long siar = mfspr(SPRN_SIAR); |
230 | if (siar >= PAGE_OFFSET) | |
231 | return PERF_RECORD_MISC_KERNEL; | |
232 | return PERF_RECORD_MISC_USER; | |
233 | } | |
98fb1807 | 234 | |
7abb840b | 235 | /* PR has priority over HV, so order below is important */ |
5682c460 | 236 | if (regs_sipr(regs)) |
7abb840b | 237 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
238 | |
239 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 240 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 241 | |
7abb840b | 242 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
243 | } |
244 | ||
245 | /* | |
246 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
247 | * on each interrupt. | |
8f61aa32 | 248 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
249 | * Overload regs->result to specify whether we should use the MSR (result |
250 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
251 | */ |
252 | static inline void perf_read_regs(struct pt_regs *regs) | |
253 | { | |
75382aa7 AB |
254 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
255 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
256 | int use_siar; | |
257 | ||
5682c460 | 258 | regs->dsisr = mmcra; |
8f61aa32 | 259 | |
cbda6aa1 ME |
260 | if (ppmu->flags & PPMU_HAS_SIER) |
261 | regs->dar = mfspr(SPRN_SIER); | |
8f61aa32 | 262 | |
5c093efa AB |
263 | /* |
264 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
265 | * not valid. Use pt_regs. | |
266 | * | |
267 | * If it is a marked event use the SIAR. | |
268 | * | |
269 | * If the PMU doesn't update the SIAR for non marked events use | |
270 | * pt_regs. | |
271 | * | |
272 | * If the PMU has HV/PR flags then check to see if they | |
273 | * place the exception in userspace. If so, use pt_regs. In | |
274 | * continuous sampling mode the SIAR and the PMU exception are | |
275 | * not synchronised, so they may be many instructions apart. | |
276 | * This can result in confusing backtraces. We still want | |
277 | * hypervisor samples as well as samples in the kernel with | |
278 | * interrupts off hence the userspace check. | |
279 | */ | |
75382aa7 AB |
280 | if (TRAP(regs) != 0xf00) |
281 | use_siar = 0; | |
5c093efa AB |
282 | else if (marked) |
283 | use_siar = 1; | |
284 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
285 | use_siar = 0; | |
cbda6aa1 | 286 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
287 | use_siar = 0; |
288 | else | |
289 | use_siar = 1; | |
290 | ||
cbda6aa1 | 291 | regs->result = use_siar; |
98fb1807 PM |
292 | } |
293 | ||
294 | /* | |
295 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
296 | * it as an NMI. | |
297 | */ | |
298 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
299 | { | |
300 | return !regs->softe; | |
301 | } | |
302 | ||
e6878835 | 303 | /* |
304 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
305 | * must be sampled only if the SIAR-valid bit is set. | |
306 | * | |
307 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
308 | * bit, assume that SIAR is valid. | |
309 | */ | |
310 | static inline int siar_valid(struct pt_regs *regs) | |
311 | { | |
312 | unsigned long mmcra = regs->dsisr; | |
313 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
314 | ||
58a032c3 ME |
315 | if (marked) { |
316 | if (ppmu->flags & PPMU_HAS_SIER) | |
317 | return regs->dar & SIER_SIAR_VALID; | |
318 | ||
319 | if (ppmu->flags & PPMU_SIAR_VALID) | |
320 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
321 | } | |
e6878835 | 322 | |
323 | return 1; | |
324 | } | |
325 | ||
d52f2dc4 MN |
326 | |
327 | /* Reset all possible BHRB entries */ | |
328 | static void power_pmu_bhrb_reset(void) | |
329 | { | |
330 | asm volatile(PPC_CLRBHRB); | |
331 | } | |
332 | ||
333 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
334 | { | |
335 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
336 | ||
337 | if (!ppmu->bhrb_nr) | |
338 | return; | |
339 | ||
340 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
341 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
342 | power_pmu_bhrb_reset(); | |
343 | cpuhw->bhrb_context = event->ctx; | |
344 | } | |
345 | cpuhw->bhrb_users++; | |
346 | } | |
347 | ||
348 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
349 | { | |
350 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
351 | ||
352 | if (!ppmu->bhrb_nr) | |
353 | return; | |
354 | ||
355 | cpuhw->bhrb_users--; | |
356 | WARN_ON_ONCE(cpuhw->bhrb_users < 0); | |
357 | ||
358 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
359 | /* BHRB cannot be turned off when other | |
360 | * events are active on the PMU. | |
361 | */ | |
362 | ||
363 | /* avoid stale pointer */ | |
364 | cpuhw->bhrb_context = NULL; | |
365 | } | |
366 | } | |
367 | ||
368 | /* Called from ctxsw to prevent one process's branch entries to | |
369 | * mingle with the other process's entries during context switch. | |
370 | */ | |
371 | void power_pmu_flush_branch_stack(void) | |
372 | { | |
373 | if (ppmu->bhrb_nr) | |
374 | power_pmu_bhrb_reset(); | |
375 | } | |
69123184 MN |
376 | /* Calculate the to address for a branch */ |
377 | static __u64 power_pmu_bhrb_to(u64 addr) | |
378 | { | |
379 | unsigned int instr; | |
380 | int ret; | |
381 | __u64 target; | |
382 | ||
383 | if (is_kernel_addr(addr)) | |
384 | return branch_target((unsigned int *)addr); | |
385 | ||
386 | /* Userspace: need copy instruction here then translate it */ | |
387 | pagefault_disable(); | |
388 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
389 | if (ret) { | |
390 | pagefault_enable(); | |
391 | return 0; | |
392 | } | |
393 | pagefault_enable(); | |
394 | ||
395 | target = branch_target(&instr); | |
396 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
397 | return target; | |
398 | ||
399 | /* Translate relative branch target from kernel to user address */ | |
400 | return target - (unsigned long)&instr + addr; | |
401 | } | |
d52f2dc4 | 402 | |
d52f2dc4 | 403 | /* Processing BHRB entries */ |
506e70d1 | 404 | void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
405 | { |
406 | u64 val; | |
407 | u64 addr; | |
506e70d1 | 408 | int r_index, u_index, pred; |
d52f2dc4 MN |
409 | |
410 | r_index = 0; | |
411 | u_index = 0; | |
412 | while (r_index < ppmu->bhrb_nr) { | |
413 | /* Assembly read function */ | |
506e70d1 MN |
414 | val = read_bhrb(r_index++); |
415 | if (!val) | |
416 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 417 | break; |
506e70d1 | 418 | else { |
d52f2dc4 MN |
419 | addr = val & BHRB_EA; |
420 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 421 | |
506e70d1 MN |
422 | if (!addr) |
423 | /* invalid entry */ | |
d52f2dc4 | 424 | continue; |
d52f2dc4 | 425 | |
506e70d1 MN |
426 | /* Branches are read most recent first (ie. mfbhrb 0 is |
427 | * the most recent branch). | |
428 | * There are two types of valid entries: | |
429 | * 1) a target entry which is the to address of a | |
430 | * computed goto like a blr,bctr,btar. The next | |
431 | * entry read from the bhrb will be branch | |
432 | * corresponding to this target (ie. the actual | |
433 | * blr/bctr/btar instruction). | |
434 | * 2) a from address which is an actual branch. If a | |
435 | * target entry proceeds this, then this is the | |
436 | * matching branch for that target. If this is not | |
437 | * following a target entry, then this is a branch | |
438 | * where the target is given as an immediate field | |
439 | * in the instruction (ie. an i or b form branch). | |
440 | * In this case we need to read the instruction from | |
441 | * memory to determine the target/to address. | |
442 | */ | |
d52f2dc4 | 443 | |
d52f2dc4 | 444 | if (val & BHRB_TARGET) { |
506e70d1 MN |
445 | /* Target branches use two entries |
446 | * (ie. computed gotos/XL form) | |
447 | */ | |
448 | cpuhw->bhrb_entries[u_index].to = addr; | |
449 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
450 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 451 | |
506e70d1 MN |
452 | /* Get from address in next entry */ |
453 | val = read_bhrb(r_index++); | |
454 | addr = val & BHRB_EA; | |
455 | if (val & BHRB_TARGET) { | |
456 | /* Shouldn't have two targets in a | |
457 | row.. Reset index and try again */ | |
458 | r_index--; | |
459 | addr = 0; | |
460 | } | |
461 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 462 | } else { |
506e70d1 MN |
463 | /* Branches to immediate field |
464 | (ie I or B form) */ | |
d52f2dc4 | 465 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
466 | cpuhw->bhrb_entries[u_index].to = |
467 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
468 | cpuhw->bhrb_entries[u_index].mispred = pred; |
469 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 470 | } |
506e70d1 MN |
471 | u_index++; |
472 | ||
d52f2dc4 MN |
473 | } |
474 | } | |
475 | cpuhw->bhrb_stack.nr = u_index; | |
476 | return; | |
477 | } | |
478 | ||
330a1eb7 ME |
479 | static bool is_ebb_event(struct perf_event *event) |
480 | { | |
481 | /* | |
482 | * This could be a per-PMU callback, but we'd rather avoid the cost. We | |
483 | * check that the PMU supports EBB, meaning those that don't can still | |
484 | * use bit 63 of the event code for something else if they wish. | |
485 | */ | |
486 | return (ppmu->flags & PPMU_EBB) && | |
8d7c55d0 | 487 | ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); |
330a1eb7 ME |
488 | } |
489 | ||
490 | static int ebb_event_check(struct perf_event *event) | |
491 | { | |
492 | struct perf_event *leader = event->group_leader; | |
493 | ||
494 | /* Event and group leader must agree on EBB */ | |
495 | if (is_ebb_event(leader) != is_ebb_event(event)) | |
496 | return -EINVAL; | |
497 | ||
498 | if (is_ebb_event(event)) { | |
499 | if (!(event->attach_state & PERF_ATTACH_TASK)) | |
500 | return -EINVAL; | |
501 | ||
502 | if (!leader->attr.pinned || !leader->attr.exclusive) | |
503 | return -EINVAL; | |
504 | ||
505 | if (event->attr.inherit || event->attr.sample_period || | |
506 | event->attr.enable_on_exec || event->attr.freq) | |
507 | return -EINVAL; | |
508 | } | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
513 | static void ebb_event_add(struct perf_event *event) | |
514 | { | |
515 | if (!is_ebb_event(event) || current->thread.used_ebb) | |
516 | return; | |
517 | ||
518 | /* | |
519 | * IFF this is the first time we've added an EBB event, set | |
520 | * PMXE in the user MMCR0 so we can detect when it's cleared by | |
521 | * userspace. We need this so that we can context switch while | |
522 | * userspace is in the EBB handler (where PMXE is 0). | |
523 | */ | |
524 | current->thread.used_ebb = 1; | |
525 | current->thread.mmcr0 |= MMCR0_PMXE; | |
526 | } | |
527 | ||
528 | static void ebb_switch_out(unsigned long mmcr0) | |
529 | { | |
530 | if (!(mmcr0 & MMCR0_EBE)) | |
531 | return; | |
532 | ||
533 | current->thread.siar = mfspr(SPRN_SIAR); | |
534 | current->thread.sier = mfspr(SPRN_SIER); | |
535 | current->thread.sdar = mfspr(SPRN_SDAR); | |
536 | current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; | |
537 | current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; | |
538 | } | |
539 | ||
540 | static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0) | |
541 | { | |
542 | if (!ebb) | |
543 | goto out; | |
544 | ||
545 | /* Enable EBB and read/write to all 6 PMCs for userspace */ | |
546 | mmcr0 |= MMCR0_EBE | MMCR0_PMCC_U6; | |
547 | ||
548 | /* Add any bits from the user reg, FC or PMAO */ | |
549 | mmcr0 |= current->thread.mmcr0; | |
550 | ||
551 | /* Be careful not to set PMXE if userspace had it cleared */ | |
552 | if (!(current->thread.mmcr0 & MMCR0_PMXE)) | |
553 | mmcr0 &= ~MMCR0_PMXE; | |
554 | ||
555 | mtspr(SPRN_SIAR, current->thread.siar); | |
556 | mtspr(SPRN_SIER, current->thread.sier); | |
557 | mtspr(SPRN_SDAR, current->thread.sdar); | |
558 | mtspr(SPRN_MMCR2, current->thread.mmcr2); | |
559 | out: | |
560 | return mmcr0; | |
561 | } | |
98fb1807 PM |
562 | #endif /* CONFIG_PPC64 */ |
563 | ||
cdd6c482 | 564 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 565 | |
cdd6c482 | 566 | void perf_event_print_debug(void) |
4574910e PM |
567 | { |
568 | } | |
569 | ||
4574910e | 570 | /* |
57c0c15b | 571 | * Read one performance monitor counter (PMC). |
4574910e PM |
572 | */ |
573 | static unsigned long read_pmc(int idx) | |
574 | { | |
575 | unsigned long val; | |
576 | ||
577 | switch (idx) { | |
578 | case 1: | |
579 | val = mfspr(SPRN_PMC1); | |
580 | break; | |
581 | case 2: | |
582 | val = mfspr(SPRN_PMC2); | |
583 | break; | |
584 | case 3: | |
585 | val = mfspr(SPRN_PMC3); | |
586 | break; | |
587 | case 4: | |
588 | val = mfspr(SPRN_PMC4); | |
589 | break; | |
590 | case 5: | |
591 | val = mfspr(SPRN_PMC5); | |
592 | break; | |
593 | case 6: | |
594 | val = mfspr(SPRN_PMC6); | |
595 | break; | |
98fb1807 | 596 | #ifdef CONFIG_PPC64 |
4574910e PM |
597 | case 7: |
598 | val = mfspr(SPRN_PMC7); | |
599 | break; | |
600 | case 8: | |
601 | val = mfspr(SPRN_PMC8); | |
602 | break; | |
98fb1807 | 603 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
604 | default: |
605 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
606 | val = 0; | |
607 | } | |
608 | return val; | |
609 | } | |
610 | ||
611 | /* | |
612 | * Write one PMC. | |
613 | */ | |
614 | static void write_pmc(int idx, unsigned long val) | |
615 | { | |
616 | switch (idx) { | |
617 | case 1: | |
618 | mtspr(SPRN_PMC1, val); | |
619 | break; | |
620 | case 2: | |
621 | mtspr(SPRN_PMC2, val); | |
622 | break; | |
623 | case 3: | |
624 | mtspr(SPRN_PMC3, val); | |
625 | break; | |
626 | case 4: | |
627 | mtspr(SPRN_PMC4, val); | |
628 | break; | |
629 | case 5: | |
630 | mtspr(SPRN_PMC5, val); | |
631 | break; | |
632 | case 6: | |
633 | mtspr(SPRN_PMC6, val); | |
634 | break; | |
98fb1807 | 635 | #ifdef CONFIG_PPC64 |
4574910e PM |
636 | case 7: |
637 | mtspr(SPRN_PMC7, val); | |
638 | break; | |
639 | case 8: | |
640 | mtspr(SPRN_PMC8, val); | |
641 | break; | |
98fb1807 | 642 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
643 | default: |
644 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
645 | } | |
646 | } | |
647 | ||
648 | /* | |
649 | * Check if a set of events can all go on the PMU at once. | |
650 | * If they can't, this will look at alternative codes for the events | |
651 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 652 | * The feasible set is returned in event_id[]. |
4574910e | 653 | */ |
cdd6c482 IM |
654 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
655 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 656 | int n_ev) |
4574910e | 657 | { |
448d64f8 | 658 | unsigned long mask, value, nv; |
cdd6c482 IM |
659 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
660 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 661 | int i, j; |
448d64f8 PM |
662 | unsigned long addf = ppmu->add_fields; |
663 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 664 | |
a8f90e90 | 665 | if (n_ev > ppmu->n_counter) |
4574910e PM |
666 | return -1; |
667 | ||
668 | /* First see if the events will go on as-is */ | |
669 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 670 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
671 | && !ppmu->limited_pmc_event(event_id[i])) { |
672 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 673 | cpuhw->alternatives[i]); |
cdd6c482 | 674 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 675 | } |
cdd6c482 | 676 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 677 | &cpuhw->avalues[i][0])) |
4574910e | 678 | return -1; |
4574910e PM |
679 | } |
680 | value = mask = 0; | |
681 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
682 | nv = (value | cpuhw->avalues[i][0]) + |
683 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 684 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
685 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
686 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
687 | break; |
688 | value = nv; | |
e51ee31e | 689 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
690 | } |
691 | if (i == n_ev) | |
692 | return 0; /* all OK */ | |
693 | ||
694 | /* doesn't work, gather alternatives... */ | |
695 | if (!ppmu->get_alternatives) | |
696 | return -1; | |
697 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 698 | choice[i] = 0; |
cdd6c482 | 699 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 700 | cpuhw->alternatives[i]); |
4574910e | 701 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
702 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
703 | &cpuhw->amasks[i][j], | |
704 | &cpuhw->avalues[i][j]); | |
4574910e PM |
705 | } |
706 | ||
707 | /* enumerate all possibilities and see if any will work */ | |
708 | i = 0; | |
709 | j = -1; | |
710 | value = mask = nv = 0; | |
711 | while (i < n_ev) { | |
712 | if (j >= 0) { | |
713 | /* we're backtracking, restore context */ | |
714 | value = svalues[i]; | |
715 | mask = smasks[i]; | |
716 | j = choice[i]; | |
717 | } | |
718 | /* | |
cdd6c482 | 719 | * See if any alternative k for event_id i, |
4574910e PM |
720 | * where k > j, will satisfy the constraints. |
721 | */ | |
722 | while (++j < n_alt[i]) { | |
e51ee31e PM |
723 | nv = (value | cpuhw->avalues[i][j]) + |
724 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 725 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
726 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
727 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
728 | break; |
729 | } | |
730 | if (j >= n_alt[i]) { | |
731 | /* | |
732 | * No feasible alternative, backtrack | |
cdd6c482 | 733 | * to event_id i-1 and continue enumerating its |
4574910e PM |
734 | * alternatives from where we got up to. |
735 | */ | |
736 | if (--i < 0) | |
737 | return -1; | |
738 | } else { | |
739 | /* | |
cdd6c482 IM |
740 | * Found a feasible alternative for event_id i, |
741 | * remember where we got up to with this event_id, | |
742 | * go on to the next event_id, and start with | |
4574910e PM |
743 | * the first alternative for it. |
744 | */ | |
745 | choice[i] = j; | |
746 | svalues[i] = value; | |
747 | smasks[i] = mask; | |
748 | value = nv; | |
e51ee31e | 749 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
750 | ++i; |
751 | j = -1; | |
752 | } | |
753 | } | |
754 | ||
755 | /* OK, we have a feasible combination, tell the caller the solution */ | |
756 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 757 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
758 | return 0; |
759 | } | |
760 | ||
0475f9ea | 761 | /* |
cdd6c482 | 762 | * Check if newly-added events have consistent settings for |
0475f9ea | 763 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 764 | * added events. |
0475f9ea | 765 | */ |
cdd6c482 | 766 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 767 | int n_prev, int n_new) |
0475f9ea | 768 | { |
ab7ef2e5 PM |
769 | int eu = 0, ek = 0, eh = 0; |
770 | int i, n, first; | |
cdd6c482 | 771 | struct perf_event *event; |
0475f9ea PM |
772 | |
773 | n = n_prev + n_new; | |
774 | if (n <= 1) | |
775 | return 0; | |
776 | ||
ab7ef2e5 PM |
777 | first = 1; |
778 | for (i = 0; i < n; ++i) { | |
779 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
780 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
781 | continue; | |
782 | } | |
cdd6c482 | 783 | event = ctrs[i]; |
ab7ef2e5 | 784 | if (first) { |
cdd6c482 IM |
785 | eu = event->attr.exclude_user; |
786 | ek = event->attr.exclude_kernel; | |
787 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 788 | first = 0; |
cdd6c482 IM |
789 | } else if (event->attr.exclude_user != eu || |
790 | event->attr.exclude_kernel != ek || | |
791 | event->attr.exclude_hv != eh) { | |
0475f9ea | 792 | return -EAGAIN; |
ab7ef2e5 | 793 | } |
0475f9ea | 794 | } |
ab7ef2e5 PM |
795 | |
796 | if (eu || ek || eh) | |
797 | for (i = 0; i < n; ++i) | |
798 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
799 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
800 | ||
0475f9ea PM |
801 | return 0; |
802 | } | |
803 | ||
86c74ab3 EM |
804 | static u64 check_and_compute_delta(u64 prev, u64 val) |
805 | { | |
806 | u64 delta = (val - prev) & 0xfffffffful; | |
807 | ||
808 | /* | |
809 | * POWER7 can roll back counter values, if the new value is smaller | |
810 | * than the previous value it will cause the delta and the counter to | |
811 | * have bogus values unless we rolled a counter over. If a coutner is | |
812 | * rolled back, it will be smaller, but within 256, which is the maximum | |
813 | * number of events to rollback at once. If we dectect a rollback | |
814 | * return 0. This can lead to a small lack of precision in the | |
815 | * counters. | |
816 | */ | |
817 | if (prev > val && (prev - val) < 256) | |
818 | delta = 0; | |
819 | ||
820 | return delta; | |
821 | } | |
822 | ||
cdd6c482 | 823 | static void power_pmu_read(struct perf_event *event) |
4574910e | 824 | { |
98fb1807 | 825 | s64 val, delta, prev; |
4574910e | 826 | |
a4eaf7f1 PZ |
827 | if (event->hw.state & PERF_HES_STOPPED) |
828 | return; | |
829 | ||
cdd6c482 | 830 | if (!event->hw.idx) |
4574910e | 831 | return; |
330a1eb7 ME |
832 | |
833 | if (is_ebb_event(event)) { | |
834 | val = read_pmc(event->hw.idx); | |
835 | local64_set(&event->hw.prev_count, val); | |
836 | return; | |
837 | } | |
838 | ||
4574910e PM |
839 | /* |
840 | * Performance monitor interrupts come even when interrupts | |
841 | * are soft-disabled, as long as interrupts are hard-enabled. | |
842 | * Therefore we treat them like NMIs. | |
843 | */ | |
844 | do { | |
e7850595 | 845 | prev = local64_read(&event->hw.prev_count); |
4574910e | 846 | barrier(); |
cdd6c482 | 847 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
848 | delta = check_and_compute_delta(prev, val); |
849 | if (!delta) | |
850 | return; | |
e7850595 | 851 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 852 | |
e7850595 PZ |
853 | local64_add(delta, &event->count); |
854 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
855 | } |
856 | ||
ab7ef2e5 PM |
857 | /* |
858 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
859 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 860 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
861 | */ |
862 | static int is_limited_pmc(int pmcnum) | |
863 | { | |
0bbd0d4b PM |
864 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
865 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
866 | } |
867 | ||
a8f90e90 | 868 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
869 | unsigned long pmc5, unsigned long pmc6) |
870 | { | |
cdd6c482 | 871 | struct perf_event *event; |
ab7ef2e5 PM |
872 | u64 val, prev, delta; |
873 | int i; | |
874 | ||
875 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 876 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 877 | if (!event->hw.idx) |
ab7ef2e5 | 878 | continue; |
cdd6c482 | 879 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 880 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 881 | event->hw.idx = 0; |
86c74ab3 EM |
882 | delta = check_and_compute_delta(prev, val); |
883 | if (delta) | |
884 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
885 | } |
886 | } | |
887 | ||
a8f90e90 | 888 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
889 | unsigned long pmc5, unsigned long pmc6) |
890 | { | |
cdd6c482 | 891 | struct perf_event *event; |
86c74ab3 | 892 | u64 val, prev; |
ab7ef2e5 PM |
893 | int i; |
894 | ||
895 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 896 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
897 | event->hw.idx = cpuhw->limited_hwidx[i]; |
898 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
899 | prev = local64_read(&event->hw.prev_count); |
900 | if (check_and_compute_delta(prev, val)) | |
901 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 902 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
903 | } |
904 | } | |
905 | ||
906 | /* | |
cdd6c482 | 907 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 908 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
909 | * other events. We try to keep the values from the limited |
910 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 911 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
912 | * the limited events as small and consistent as possible. |
913 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
914 | * both, and always in the same order, to minimize variability, |
915 | * and do it inside the same asm that writes MMCR0. | |
916 | */ | |
cdd6c482 | 917 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
918 | { |
919 | unsigned long pmc5, pmc6; | |
920 | ||
921 | if (!cpuhw->n_limited) { | |
922 | mtspr(SPRN_MMCR0, mmcr0); | |
923 | return; | |
924 | } | |
925 | ||
926 | /* | |
927 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
928 | * To ensure we don't get a performance monitor interrupt |
929 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 930 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 931 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
932 | */ |
933 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
934 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
935 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
936 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
937 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
938 | ||
939 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 940 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 941 | else |
a8f90e90 | 942 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
943 | |
944 | /* | |
cdd6c482 | 945 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
946 | * enable bits, if necessary. |
947 | */ | |
948 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
949 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
950 | } |
951 | ||
4574910e | 952 | /* |
cdd6c482 IM |
953 | * Disable all events to prevent PMU interrupts and to allow |
954 | * events to be added or removed. | |
4574910e | 955 | */ |
a4eaf7f1 | 956 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 957 | { |
cdd6c482 | 958 | struct cpu_hw_events *cpuhw; |
330a1eb7 | 959 | unsigned long flags, mmcr0, val; |
4574910e | 960 | |
f36a1a13 PM |
961 | if (!ppmu) |
962 | return; | |
4574910e | 963 | local_irq_save(flags); |
cdd6c482 | 964 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 965 | |
448d64f8 | 966 | if (!cpuhw->disabled) { |
01d0287f PM |
967 | /* |
968 | * Check if we ever enabled the PMU on this cpu. | |
969 | */ | |
970 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 971 | ppc_enable_pmcs(); |
01d0287f PM |
972 | cpuhw->pmcs_enabled = 1; |
973 | } | |
974 | ||
378a6ee9 | 975 | /* |
330a1eb7 | 976 | * Set the 'freeze counters' bit, clear EBE/PMCC/PMAO/FC56. |
378a6ee9 | 977 | */ |
330a1eb7 | 978 | val = mmcr0 = mfspr(SPRN_MMCR0); |
378a6ee9 | 979 | val |= MMCR0_FC; |
330a1eb7 | 980 | val &= ~(MMCR0_EBE | MMCR0_PMCC | MMCR0_PMAO | MMCR0_FC56); |
378a6ee9 ME |
981 | |
982 | /* | |
983 | * The barrier is to make sure the mtspr has been | |
984 | * executed and the PMU has frozen the events etc. | |
985 | * before we return. | |
986 | */ | |
987 | write_mmcr0(cpuhw, val); | |
988 | mb(); | |
989 | ||
f708223d PM |
990 | /* |
991 | * Disable instruction sampling if it was enabled | |
992 | */ | |
993 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
994 | mtspr(SPRN_MMCRA, | |
995 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
996 | mb(); | |
997 | } | |
998 | ||
378a6ee9 ME |
999 | cpuhw->disabled = 1; |
1000 | cpuhw->n_added = 0; | |
330a1eb7 ME |
1001 | |
1002 | ebb_switch_out(mmcr0); | |
4574910e | 1003 | } |
330a1eb7 | 1004 | |
4574910e | 1005 | local_irq_restore(flags); |
4574910e PM |
1006 | } |
1007 | ||
1008 | /* | |
cdd6c482 IM |
1009 | * Re-enable all events if disable == 0. |
1010 | * If we were previously disabled and events were added, then | |
4574910e PM |
1011 | * put the new config on the PMU. |
1012 | */ | |
a4eaf7f1 | 1013 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 1014 | { |
cdd6c482 IM |
1015 | struct perf_event *event; |
1016 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
1017 | unsigned long flags; |
1018 | long i; | |
330a1eb7 | 1019 | unsigned long val, mmcr0; |
4574910e | 1020 | s64 left; |
cdd6c482 | 1021 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
1022 | int n_lim; |
1023 | int idx; | |
330a1eb7 | 1024 | bool ebb; |
4574910e | 1025 | |
f36a1a13 PM |
1026 | if (!ppmu) |
1027 | return; | |
4574910e | 1028 | local_irq_save(flags); |
0a48843d | 1029 | |
cdd6c482 | 1030 | cpuhw = &__get_cpu_var(cpu_hw_events); |
0a48843d ME |
1031 | if (!cpuhw->disabled) |
1032 | goto out; | |
1033 | ||
4ea355b5 ME |
1034 | if (cpuhw->n_events == 0) { |
1035 | ppc_set_pmu_inuse(0); | |
1036 | goto out; | |
1037 | } | |
1038 | ||
4574910e PM |
1039 | cpuhw->disabled = 0; |
1040 | ||
330a1eb7 ME |
1041 | /* |
1042 | * EBB requires an exclusive group and all events must have the EBB | |
1043 | * flag set, or not set, so we can just check a single event. Also we | |
1044 | * know we have at least one event. | |
1045 | */ | |
1046 | ebb = is_ebb_event(cpuhw->event[0]); | |
1047 | ||
4574910e | 1048 | /* |
cdd6c482 | 1049 | * If we didn't change anything, or only removed events, |
4574910e PM |
1050 | * no need to recalculate MMCR* settings and reset the PMCs. |
1051 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 1052 | * (possibly updated for removal of events). |
4574910e PM |
1053 | */ |
1054 | if (!cpuhw->n_added) { | |
f708223d | 1055 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 1056 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
f708223d | 1057 | goto out_enable; |
4574910e PM |
1058 | } |
1059 | ||
1060 | /* | |
cdd6c482 | 1061 | * Compute MMCR* values for the new set of events |
4574910e | 1062 | */ |
cdd6c482 | 1063 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
1064 | cpuhw->mmcr)) { |
1065 | /* shouldn't ever get here */ | |
1066 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
1067 | goto out; | |
1068 | } | |
1069 | ||
0475f9ea PM |
1070 | /* |
1071 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
1072 | * attr.exclude_* bits for the first event. |
1073 | * We have already checked that all events have the | |
1074 | * same values for these bits as the first event. | |
0475f9ea | 1075 | */ |
cdd6c482 IM |
1076 | event = cpuhw->event[0]; |
1077 | if (event->attr.exclude_user) | |
0475f9ea | 1078 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
1079 | if (event->attr.exclude_kernel) |
1080 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
1081 | if (event->attr.exclude_hv) | |
0475f9ea PM |
1082 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
1083 | ||
4574910e PM |
1084 | /* |
1085 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
1086 | * bit set and set the hardware events to their initial values. |
1087 | * Then unfreeze the events. | |
4574910e | 1088 | */ |
a6dbf93a | 1089 | ppc_set_pmu_inuse(1); |
f708223d | 1090 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
1091 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
1092 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1093 | | MMCR0_FC); | |
1094 | ||
1095 | /* | |
cdd6c482 | 1096 | * Read off any pre-existing events that need to move |
4574910e PM |
1097 | * to another PMC. |
1098 | */ | |
cdd6c482 IM |
1099 | for (i = 0; i < cpuhw->n_events; ++i) { |
1100 | event = cpuhw->event[i]; | |
1101 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
1102 | power_pmu_read(event); | |
1103 | write_pmc(event->hw.idx, 0); | |
1104 | event->hw.idx = 0; | |
4574910e PM |
1105 | } |
1106 | } | |
1107 | ||
1108 | /* | |
cdd6c482 | 1109 | * Initialize the PMCs for all the new and moved events. |
4574910e | 1110 | */ |
ab7ef2e5 | 1111 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
1112 | for (i = 0; i < cpuhw->n_events; ++i) { |
1113 | event = cpuhw->event[i]; | |
1114 | if (event->hw.idx) | |
4574910e | 1115 | continue; |
ab7ef2e5 PM |
1116 | idx = hwc_index[i] + 1; |
1117 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 1118 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
1119 | cpuhw->limited_hwidx[n_lim] = idx; |
1120 | ++n_lim; | |
1121 | continue; | |
1122 | } | |
330a1eb7 ME |
1123 | |
1124 | if (ebb) | |
1125 | val = local64_read(&event->hw.prev_count); | |
1126 | else { | |
1127 | val = 0; | |
1128 | if (event->hw.sample_period) { | |
1129 | left = local64_read(&event->hw.period_left); | |
1130 | if (left < 0x80000000L) | |
1131 | val = 0x80000000L - left; | |
1132 | } | |
1133 | local64_set(&event->hw.prev_count, val); | |
4574910e | 1134 | } |
330a1eb7 | 1135 | |
cdd6c482 | 1136 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1137 | if (event->hw.state & PERF_HES_STOPPED) |
1138 | val = 0; | |
ab7ef2e5 | 1139 | write_pmc(idx, val); |
330a1eb7 | 1140 | |
cdd6c482 | 1141 | perf_event_update_userpage(event); |
4574910e | 1142 | } |
ab7ef2e5 | 1143 | cpuhw->n_limited = n_lim; |
4574910e | 1144 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1145 | |
1146 | out_enable: | |
330a1eb7 ME |
1147 | mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]); |
1148 | ||
f708223d | 1149 | mb(); |
b4d6c06c AK |
1150 | if (cpuhw->bhrb_users) |
1151 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1152 | ||
330a1eb7 | 1153 | write_mmcr0(cpuhw, mmcr0); |
4574910e | 1154 | |
f708223d PM |
1155 | /* |
1156 | * Enable instruction sampling if necessary | |
1157 | */ | |
1158 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1159 | mb(); | |
1160 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1161 | } | |
1162 | ||
4574910e | 1163 | out: |
3925f46b | 1164 | |
4574910e PM |
1165 | local_irq_restore(flags); |
1166 | } | |
1167 | ||
cdd6c482 IM |
1168 | static int collect_events(struct perf_event *group, int max_count, |
1169 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1170 | unsigned int *flags) |
4574910e PM |
1171 | { |
1172 | int n = 0; | |
cdd6c482 | 1173 | struct perf_event *event; |
4574910e | 1174 | |
cdd6c482 | 1175 | if (!is_software_event(group)) { |
4574910e PM |
1176 | if (n >= max_count) |
1177 | return -1; | |
1178 | ctrs[n] = group; | |
cdd6c482 | 1179 | flags[n] = group->hw.event_base; |
4574910e PM |
1180 | events[n++] = group->hw.config; |
1181 | } | |
a8f90e90 | 1182 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1183 | if (!is_software_event(event) && |
1184 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1185 | if (n >= max_count) |
1186 | return -1; | |
cdd6c482 IM |
1187 | ctrs[n] = event; |
1188 | flags[n] = event->hw.event_base; | |
1189 | events[n++] = event->hw.config; | |
4574910e PM |
1190 | } |
1191 | } | |
1192 | return n; | |
1193 | } | |
1194 | ||
4574910e | 1195 | /* |
cdd6c482 IM |
1196 | * Add a event to the PMU. |
1197 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1198 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1199 | * actual work of reconfiguring the PMU. |
1200 | */ | |
a4eaf7f1 | 1201 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1202 | { |
cdd6c482 | 1203 | struct cpu_hw_events *cpuhw; |
4574910e | 1204 | unsigned long flags; |
4574910e PM |
1205 | int n0; |
1206 | int ret = -EAGAIN; | |
1207 | ||
1208 | local_irq_save(flags); | |
33696fc0 | 1209 | perf_pmu_disable(event->pmu); |
4574910e PM |
1210 | |
1211 | /* | |
cdd6c482 | 1212 | * Add the event to the list (if there is room) |
4574910e PM |
1213 | * and check whether the total set is still feasible. |
1214 | */ | |
cdd6c482 IM |
1215 | cpuhw = &__get_cpu_var(cpu_hw_events); |
1216 | n0 = cpuhw->n_events; | |
a8f90e90 | 1217 | if (n0 >= ppmu->n_counter) |
4574910e | 1218 | goto out; |
cdd6c482 IM |
1219 | cpuhw->event[n0] = event; |
1220 | cpuhw->events[n0] = event->hw.config; | |
1221 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1222 | |
f53d168c | 1223 | /* |
1224 | * This event may have been disabled/stopped in record_and_restart() | |
1225 | * because we exceeded the ->event_limit. If re-starting the event, | |
1226 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1227 | * notification is re-enabled. | |
1228 | */ | |
a4eaf7f1 PZ |
1229 | if (!(ef_flags & PERF_EF_START)) |
1230 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1231 | else |
1232 | event->hw.state = 0; | |
a4eaf7f1 | 1233 | |
8e6d5573 LM |
1234 | /* |
1235 | * If group events scheduling transaction was started, | |
25985edc | 1236 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1237 | * at commit time(->commit_txn) as a whole |
1238 | */ | |
8d2cacbb | 1239 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
1240 | goto nocheck; |
1241 | ||
cdd6c482 | 1242 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1243 | goto out; |
e51ee31e | 1244 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1245 | goto out; |
cdd6c482 | 1246 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1247 | |
1248 | nocheck: | |
330a1eb7 ME |
1249 | ebb_event_add(event); |
1250 | ||
cdd6c482 | 1251 | ++cpuhw->n_events; |
4574910e PM |
1252 | ++cpuhw->n_added; |
1253 | ||
1254 | ret = 0; | |
1255 | out: | |
ff3d79dc | 1256 | if (has_branch_stack(event)) { |
3925f46b | 1257 | power_pmu_bhrb_enable(event); |
ff3d79dc AK |
1258 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( |
1259 | event->attr.branch_sample_type); | |
1260 | } | |
3925f46b | 1261 | |
33696fc0 | 1262 | perf_pmu_enable(event->pmu); |
4574910e PM |
1263 | local_irq_restore(flags); |
1264 | return ret; | |
1265 | } | |
1266 | ||
1267 | /* | |
cdd6c482 | 1268 | * Remove a event from the PMU. |
4574910e | 1269 | */ |
a4eaf7f1 | 1270 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1271 | { |
cdd6c482 | 1272 | struct cpu_hw_events *cpuhw; |
4574910e | 1273 | long i; |
4574910e PM |
1274 | unsigned long flags; |
1275 | ||
1276 | local_irq_save(flags); | |
33696fc0 | 1277 | perf_pmu_disable(event->pmu); |
4574910e | 1278 | |
cdd6c482 IM |
1279 | power_pmu_read(event); |
1280 | ||
1281 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1282 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1283 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1284 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1285 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1286 | cpuhw->events[i-1] = cpuhw->events[i]; |
1287 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1288 | } | |
cdd6c482 IM |
1289 | --cpuhw->n_events; |
1290 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1291 | if (event->hw.idx) { | |
1292 | write_pmc(event->hw.idx, 0); | |
1293 | event->hw.idx = 0; | |
ab7ef2e5 | 1294 | } |
cdd6c482 | 1295 | perf_event_update_userpage(event); |
4574910e PM |
1296 | break; |
1297 | } | |
1298 | } | |
ab7ef2e5 | 1299 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1300 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1301 | break; |
1302 | if (i < cpuhw->n_limited) { | |
1303 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1304 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1305 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1306 | } | |
1307 | --cpuhw->n_limited; | |
1308 | } | |
cdd6c482 IM |
1309 | if (cpuhw->n_events == 0) { |
1310 | /* disable exceptions if no events are running */ | |
4574910e PM |
1311 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1312 | } | |
1313 | ||
3925f46b AK |
1314 | if (has_branch_stack(event)) |
1315 | power_pmu_bhrb_disable(event); | |
1316 | ||
33696fc0 | 1317 | perf_pmu_enable(event->pmu); |
4574910e PM |
1318 | local_irq_restore(flags); |
1319 | } | |
1320 | ||
8a7b8cb9 | 1321 | /* |
a4eaf7f1 PZ |
1322 | * POWER-PMU does not support disabling individual counters, hence |
1323 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1324 | */ |
a4eaf7f1 PZ |
1325 | |
1326 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1327 | { |
8a7b8cb9 | 1328 | unsigned long flags; |
a4eaf7f1 | 1329 | s64 left; |
9a45a940 | 1330 | unsigned long val; |
8a7b8cb9 | 1331 | |
cdd6c482 | 1332 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1333 | return; |
a4eaf7f1 PZ |
1334 | |
1335 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1336 | return; | |
1337 | ||
1338 | if (ef_flags & PERF_EF_RELOAD) | |
1339 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1340 | ||
1341 | local_irq_save(flags); | |
1342 | perf_pmu_disable(event->pmu); | |
1343 | ||
1344 | event->hw.state = 0; | |
1345 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1346 | |
1347 | val = 0; | |
1348 | if (left < 0x80000000L) | |
1349 | val = 0x80000000L - left; | |
1350 | ||
1351 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1352 | |
1353 | perf_event_update_userpage(event); | |
1354 | perf_pmu_enable(event->pmu); | |
1355 | local_irq_restore(flags); | |
1356 | } | |
1357 | ||
1358 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1359 | { | |
1360 | unsigned long flags; | |
1361 | ||
1362 | if (!event->hw.idx || !event->hw.sample_period) | |
1363 | return; | |
1364 | ||
1365 | if (event->hw.state & PERF_HES_STOPPED) | |
1366 | return; | |
1367 | ||
8a7b8cb9 | 1368 | local_irq_save(flags); |
33696fc0 | 1369 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1370 | |
cdd6c482 | 1371 | power_pmu_read(event); |
a4eaf7f1 PZ |
1372 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1373 | write_pmc(event->hw.idx, 0); | |
1374 | ||
cdd6c482 | 1375 | perf_event_update_userpage(event); |
33696fc0 | 1376 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1377 | local_irq_restore(flags); |
1378 | } | |
1379 | ||
8e6d5573 LM |
1380 | /* |
1381 | * Start group events scheduling transaction | |
1382 | * Set the flag to make pmu::enable() not perform the | |
1383 | * schedulability test, it will be performed at commit time | |
1384 | */ | |
51b0fe39 | 1385 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
1386 | { |
1387 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1388 | ||
33696fc0 | 1389 | perf_pmu_disable(pmu); |
8d2cacbb | 1390 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1391 | cpuhw->n_txn_start = cpuhw->n_events; |
1392 | } | |
1393 | ||
1394 | /* | |
1395 | * Stop group events scheduling transaction | |
1396 | * Clear the flag and pmu::enable() will perform the | |
1397 | * schedulability test. | |
1398 | */ | |
51b0fe39 | 1399 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
1400 | { |
1401 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1402 | ||
8d2cacbb | 1403 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1404 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1405 | } |
1406 | ||
1407 | /* | |
1408 | * Commit group events scheduling transaction | |
1409 | * Perform the group schedulability test as a whole | |
1410 | * Return 0 if success | |
1411 | */ | |
51b0fe39 | 1412 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1413 | { |
1414 | struct cpu_hw_events *cpuhw; | |
1415 | long i, n; | |
1416 | ||
1417 | if (!ppmu) | |
1418 | return -EAGAIN; | |
1419 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1420 | n = cpuhw->n_events; | |
1421 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1422 | return -EAGAIN; | |
1423 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1424 | if (i < 0) | |
1425 | return -EAGAIN; | |
1426 | ||
1427 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1428 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1429 | ||
8d2cacbb | 1430 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1431 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1432 | return 0; |
1433 | } | |
1434 | ||
ab7ef2e5 | 1435 | /* |
cdd6c482 | 1436 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1437 | * or 0 if not. |
cdd6c482 | 1438 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1439 | * that a limited PMC can count, doesn't require interrupts, and |
1440 | * doesn't exclude any processor mode. | |
1441 | */ | |
cdd6c482 | 1442 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1443 | unsigned int flags) |
1444 | { | |
1445 | int n; | |
ef923214 | 1446 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1447 | |
cdd6c482 IM |
1448 | if (event->attr.exclude_user |
1449 | || event->attr.exclude_kernel | |
1450 | || event->attr.exclude_hv | |
1451 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1452 | return 0; |
1453 | ||
1454 | if (ppmu->limited_pmc_event(ev)) | |
1455 | return 1; | |
1456 | ||
1457 | /* | |
cdd6c482 | 1458 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1459 | * see if any alternative code goes on a limited PMC. |
1460 | */ | |
1461 | if (!ppmu->get_alternatives) | |
1462 | return 0; | |
1463 | ||
1464 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1465 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1466 | |
ef923214 | 1467 | return n > 0; |
ab7ef2e5 PM |
1468 | } |
1469 | ||
1470 | /* | |
cdd6c482 IM |
1471 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1472 | * and return the event_id code, or 0 if there is no such alternative. | |
1473 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1474 | */ |
ef923214 | 1475 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1476 | { |
ef923214 | 1477 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1478 | int n; |
1479 | ||
1480 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1481 | n = ppmu->get_alternatives(ev, flags, alt); | |
1482 | if (!n) | |
1483 | return 0; | |
1484 | return alt[0]; | |
1485 | } | |
1486 | ||
cdd6c482 IM |
1487 | /* Number of perf_events counting hardware events */ |
1488 | static atomic_t num_events; | |
7595d63b PM |
1489 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1490 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1491 | ||
1492 | /* | |
cdd6c482 | 1493 | * Release the PMU if this is the last perf_event. |
7595d63b | 1494 | */ |
cdd6c482 | 1495 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1496 | { |
cdd6c482 | 1497 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1498 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1499 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1500 | release_pmc_hardware(); |
1501 | mutex_unlock(&pmc_reserve_mutex); | |
1502 | } | |
1503 | } | |
1504 | ||
106b506c | 1505 | /* |
cdd6c482 | 1506 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1507 | */ |
1508 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1509 | { | |
1510 | unsigned long type, op, result; | |
1511 | int ev; | |
1512 | ||
1513 | if (!ppmu->cache_events) | |
1514 | return -EINVAL; | |
1515 | ||
1516 | /* unpack config */ | |
1517 | type = config & 0xff; | |
1518 | op = (config >> 8) & 0xff; | |
1519 | result = (config >> 16) & 0xff; | |
1520 | ||
1521 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1522 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1523 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1524 | return -EINVAL; | |
1525 | ||
1526 | ev = (*ppmu->cache_events)[type][op][result]; | |
1527 | if (ev == 0) | |
1528 | return -EOPNOTSUPP; | |
1529 | if (ev == -1) | |
1530 | return -EINVAL; | |
1531 | *eventp = ev; | |
1532 | return 0; | |
1533 | } | |
1534 | ||
b0a873eb | 1535 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1536 | { |
ef923214 PM |
1537 | u64 ev; |
1538 | unsigned long flags; | |
cdd6c482 IM |
1539 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1540 | u64 events[MAX_HWEVENTS]; | |
1541 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1542 | int n; |
7595d63b | 1543 | int err; |
cdd6c482 | 1544 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1545 | |
1546 | if (!ppmu) | |
b0a873eb PZ |
1547 | return -ENOENT; |
1548 | ||
3925f46b AK |
1549 | if (has_branch_stack(event)) { |
1550 | /* PMU has BHRB enabled */ | |
1551 | if (!(ppmu->flags & PPMU_BHRB)) | |
1552 | return -EOPNOTSUPP; | |
1553 | } | |
2481c5fa | 1554 | |
cdd6c482 | 1555 | switch (event->attr.type) { |
106b506c | 1556 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1557 | ev = event->attr.config; |
9aaa131a | 1558 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1559 | return -EOPNOTSUPP; |
4574910e | 1560 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1561 | break; |
1562 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1563 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1564 | if (err) |
b0a873eb | 1565 | return err; |
106b506c PM |
1566 | break; |
1567 | case PERF_TYPE_RAW: | |
cdd6c482 | 1568 | ev = event->attr.config; |
106b506c | 1569 | break; |
90c8f954 | 1570 | default: |
b0a873eb | 1571 | return -ENOENT; |
4574910e | 1572 | } |
b0a873eb | 1573 | |
cdd6c482 IM |
1574 | event->hw.config_base = ev; |
1575 | event->hw.idx = 0; | |
4574910e | 1576 | |
0475f9ea PM |
1577 | /* |
1578 | * If we are not running on a hypervisor, force the | |
1579 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1580 | * the user set it to. |
0475f9ea PM |
1581 | */ |
1582 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1583 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1584 | |
1585 | /* | |
cdd6c482 | 1586 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1587 | * PM_RUN_* events interchangeably with their non RUN_* |
1588 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1589 | * XXX we should check if the task is an idle task. | |
1590 | */ | |
1591 | flags = 0; | |
57fa7214 | 1592 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1593 | flags |= PPMU_ONLY_COUNT_RUN; |
1594 | ||
1595 | /* | |
cdd6c482 IM |
1596 | * If this machine has limited events, check whether this |
1597 | * event_id could go on a limited event. | |
ab7ef2e5 | 1598 | */ |
0bbd0d4b | 1599 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1600 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1601 | flags |= PPMU_LIMITED_PMC_OK; |
1602 | } else if (ppmu->limited_pmc_event(ev)) { | |
1603 | /* | |
cdd6c482 | 1604 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1605 | * but we can't use a limited PMC; see if any |
1606 | * alternative goes on a normal PMC. | |
1607 | */ | |
1608 | ev = normal_pmc_alternative(ev, flags); | |
1609 | if (!ev) | |
b0a873eb | 1610 | return -EINVAL; |
ab7ef2e5 PM |
1611 | } |
1612 | } | |
1613 | ||
330a1eb7 ME |
1614 | /* Extra checks for EBB */ |
1615 | err = ebb_event_check(event); | |
1616 | if (err) | |
1617 | return err; | |
1618 | ||
4574910e PM |
1619 | /* |
1620 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1621 | * other hardware events in the group. We assume the event |
4574910e PM |
1622 | * hasn't been linked into its leader's sibling list at this point. |
1623 | */ | |
1624 | n = 0; | |
cdd6c482 | 1625 | if (event->group_leader != event) { |
a8f90e90 | 1626 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1627 | ctrs, events, cflags); |
4574910e | 1628 | if (n < 0) |
b0a873eb | 1629 | return -EINVAL; |
4574910e | 1630 | } |
0475f9ea | 1631 | events[n] = ev; |
cdd6c482 | 1632 | ctrs[n] = event; |
ab7ef2e5 PM |
1633 | cflags[n] = flags; |
1634 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1635 | return -EINVAL; |
e51ee31e | 1636 | |
cdd6c482 | 1637 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1638 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1639 | |
1640 | if (has_branch_stack(event)) { | |
1641 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1642 | event->attr.branch_sample_type); | |
1643 | ||
1644 | if(cpuhw->bhrb_filter == -1) | |
1645 | return -EOPNOTSUPP; | |
1646 | } | |
1647 | ||
cdd6c482 | 1648 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1649 | if (err) |
b0a873eb | 1650 | return -EINVAL; |
4574910e | 1651 | |
cdd6c482 IM |
1652 | event->hw.config = events[n]; |
1653 | event->hw.event_base = cflags[n]; | |
1654 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1655 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b | 1656 | |
330a1eb7 ME |
1657 | /* |
1658 | * For EBB events we just context switch the PMC value, we don't do any | |
1659 | * of the sample_period logic. We use hw.prev_count for this. | |
1660 | */ | |
1661 | if (is_ebb_event(event)) | |
1662 | local64_set(&event->hw.prev_count, 0); | |
1663 | ||
7595d63b PM |
1664 | /* |
1665 | * See if we need to reserve the PMU. | |
cdd6c482 | 1666 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1667 | * mutex to ensure that we don't race with another task doing |
1668 | * reserve_pmc_hardware or release_pmc_hardware. | |
1669 | */ | |
1670 | err = 0; | |
cdd6c482 | 1671 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1672 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1673 | if (atomic_read(&num_events) == 0 && |
1674 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1675 | err = -EBUSY; |
1676 | else | |
cdd6c482 | 1677 | atomic_inc(&num_events); |
7595d63b PM |
1678 | mutex_unlock(&pmc_reserve_mutex); |
1679 | } | |
cdd6c482 | 1680 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1681 | |
b0a873eb | 1682 | return err; |
4574910e PM |
1683 | } |
1684 | ||
35edc2a5 PZ |
1685 | static int power_pmu_event_idx(struct perf_event *event) |
1686 | { | |
1687 | return event->hw.idx; | |
1688 | } | |
1689 | ||
1c53a270 SB |
1690 | ssize_t power_events_sysfs_show(struct device *dev, |
1691 | struct device_attribute *attr, char *page) | |
1692 | { | |
1693 | struct perf_pmu_events_attr *pmu_attr; | |
1694 | ||
1695 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1696 | ||
1697 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1698 | } | |
1699 | ||
b0a873eb | 1700 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1701 | .pmu_enable = power_pmu_enable, |
1702 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1703 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1704 | .add = power_pmu_add, |
1705 | .del = power_pmu_del, | |
1706 | .start = power_pmu_start, | |
1707 | .stop = power_pmu_stop, | |
b0a873eb | 1708 | .read = power_pmu_read, |
b0a873eb PZ |
1709 | .start_txn = power_pmu_start_txn, |
1710 | .cancel_txn = power_pmu_cancel_txn, | |
1711 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1712 | .event_idx = power_pmu_event_idx, |
3925f46b | 1713 | .flush_branch_stack = power_pmu_flush_branch_stack, |
b0a873eb PZ |
1714 | }; |
1715 | ||
4574910e | 1716 | /* |
57c0c15b | 1717 | * A counter has overflowed; update its count and record |
4574910e PM |
1718 | * things if requested. Note that interrupts are hard-disabled |
1719 | * here so there is no possibility of being interrupted. | |
1720 | */ | |
cdd6c482 | 1721 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1722 | struct pt_regs *regs) |
4574910e | 1723 | { |
cdd6c482 | 1724 | u64 period = event->hw.sample_period; |
4574910e PM |
1725 | s64 prev, delta, left; |
1726 | int record = 0; | |
1727 | ||
a4eaf7f1 PZ |
1728 | if (event->hw.state & PERF_HES_STOPPED) { |
1729 | write_pmc(event->hw.idx, 0); | |
1730 | return; | |
1731 | } | |
1732 | ||
4574910e | 1733 | /* we don't have to worry about interrupts here */ |
e7850595 | 1734 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1735 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1736 | local64_add(delta, &event->count); |
4574910e PM |
1737 | |
1738 | /* | |
cdd6c482 | 1739 | * See if the total period for this event has expired, |
4574910e PM |
1740 | * and update for the next period. |
1741 | */ | |
1742 | val = 0; | |
e7850595 | 1743 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1744 | if (delta == 0) |
1745 | left++; | |
60db5e09 | 1746 | if (period) { |
4574910e | 1747 | if (left <= 0) { |
60db5e09 | 1748 | left += period; |
4574910e | 1749 | if (left <= 0) |
60db5e09 | 1750 | left = period; |
e6878835 | 1751 | record = siar_valid(regs); |
4bca770e | 1752 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1753 | } |
98fb1807 PM |
1754 | if (left < 0x80000000LL) |
1755 | val = 0x80000000LL - left; | |
4574910e | 1756 | } |
4574910e | 1757 | |
a4eaf7f1 PZ |
1758 | write_pmc(event->hw.idx, val); |
1759 | local64_set(&event->hw.prev_count, val); | |
1760 | local64_set(&event->hw.period_left, left); | |
1761 | perf_event_update_userpage(event); | |
1762 | ||
4574910e PM |
1763 | /* |
1764 | * Finally record data if requested. | |
1765 | */ | |
0bbd0d4b | 1766 | if (record) { |
dc1d628a PZ |
1767 | struct perf_sample_data data; |
1768 | ||
fd0d000b | 1769 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1770 | |
cdd6c482 | 1771 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1772 | perf_get_data_addr(regs, &data.addr); |
1773 | ||
3925f46b AK |
1774 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
1775 | struct cpu_hw_events *cpuhw; | |
1776 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1777 | power_pmu_bhrb_read(cpuhw); | |
1778 | data.br_stack = &cpuhw->bhrb_stack; | |
1779 | } | |
1780 | ||
a8b0ca17 | 1781 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1782 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1783 | } |
1784 | } | |
1785 | ||
1786 | /* | |
1787 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1788 | * for an event_id. |
0bbd0d4b PM |
1789 | */ |
1790 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1791 | { | |
98fb1807 | 1792 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1793 | |
98fb1807 PM |
1794 | if (flags) |
1795 | return flags; | |
cdd6c482 IM |
1796 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1797 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1798 | } |
1799 | ||
1800 | /* | |
1801 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1802 | * for an event_id. |
0bbd0d4b PM |
1803 | */ |
1804 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1805 | { | |
33904054 | 1806 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 1807 | |
e6878835 | 1808 | if (use_siar && siar_valid(regs)) |
75382aa7 | 1809 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 1810 | else if (use_siar) |
1811 | return 0; // no valid instruction pointer | |
75382aa7 | 1812 | else |
1ce447b9 | 1813 | return regs->nip; |
4574910e PM |
1814 | } |
1815 | ||
bc09c219 | 1816 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 1817 | { |
0837e324 AB |
1818 | /* |
1819 | * Events on POWER7 can roll back if a speculative event doesn't | |
1820 | * eventually complete. Unfortunately in some rare cases they will | |
1821 | * raise a performance monitor exception. We need to catch this to | |
1822 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1823 | * cycles from overflow. | |
1824 | * | |
1825 | * We only do this if the first pass fails to find any overflowing | |
1826 | * PMCs because a user might set a period of less than 256 and we | |
1827 | * don't want to mistakenly reset them. | |
1828 | */ | |
bc09c219 MN |
1829 | if ((0x80000000 - val) <= 256) |
1830 | return true; | |
1831 | ||
1832 | return false; | |
1833 | } | |
1834 | ||
1835 | static bool pmc_overflow(unsigned long val) | |
1836 | { | |
1837 | if ((int)val < 0) | |
0837e324 AB |
1838 | return true; |
1839 | ||
1840 | return false; | |
1841 | } | |
1842 | ||
4574910e PM |
1843 | /* |
1844 | * Performance monitor interrupt stuff | |
1845 | */ | |
cdd6c482 | 1846 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 1847 | { |
bc09c219 | 1848 | int i, j; |
cdd6c482 IM |
1849 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1850 | struct perf_event *event; | |
bc09c219 MN |
1851 | unsigned long val[8]; |
1852 | int found, active; | |
ca8f2d7f PM |
1853 | int nmi; |
1854 | ||
ab7ef2e5 | 1855 | if (cpuhw->n_limited) |
a8f90e90 | 1856 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1857 | mfspr(SPRN_PMC6)); |
1858 | ||
98fb1807 | 1859 | perf_read_regs(regs); |
0bbd0d4b | 1860 | |
98fb1807 | 1861 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1862 | if (nmi) |
1863 | nmi_enter(); | |
1864 | else | |
1865 | irq_enter(); | |
4574910e | 1866 | |
bc09c219 MN |
1867 | /* Read all the PMCs since we'll need them a bunch of times */ |
1868 | for (i = 0; i < ppmu->n_counter; ++i) | |
1869 | val[i] = read_pmc(i + 1); | |
1870 | ||
1871 | /* Try to find what caused the IRQ */ | |
1872 | found = 0; | |
1873 | for (i = 0; i < ppmu->n_counter; ++i) { | |
1874 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 1875 | continue; |
bc09c219 MN |
1876 | if (is_limited_pmc(i + 1)) |
1877 | continue; /* these won't generate IRQs */ | |
1878 | /* | |
1879 | * We've found one that's overflowed. For active | |
1880 | * counters we need to log this. For inactive | |
1881 | * counters, we need to reset it anyway | |
1882 | */ | |
1883 | found = 1; | |
1884 | active = 0; | |
1885 | for (j = 0; j < cpuhw->n_events; ++j) { | |
1886 | event = cpuhw->event[j]; | |
1887 | if (event->hw.idx == (i + 1)) { | |
1888 | active = 1; | |
1889 | record_and_restart(event, val[i], regs); | |
1890 | break; | |
1891 | } | |
4574910e | 1892 | } |
bc09c219 MN |
1893 | if (!active) |
1894 | /* reset non active counters that have overflowed */ | |
1895 | write_pmc(i + 1, 0); | |
4574910e | 1896 | } |
bc09c219 MN |
1897 | if (!found && pvr_version_is(PVR_POWER7)) { |
1898 | /* check active counters for special buggy p7 overflow */ | |
1899 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1900 | event = cpuhw->event[i]; | |
1901 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1902 | continue; |
bc09c219 MN |
1903 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
1904 | /* event has overflowed in a buggy way*/ | |
1905 | found = 1; | |
1906 | record_and_restart(event, | |
1907 | val[event->hw.idx - 1], | |
1908 | regs); | |
1909 | } | |
4574910e PM |
1910 | } |
1911 | } | |
6772faa1 | 1912 | if (!found && !nmi && printk_ratelimit()) |
bc09c219 | 1913 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
4574910e PM |
1914 | |
1915 | /* | |
1916 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1917 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1918 | * and thus allow interrupts to occur again. |
cdd6c482 | 1919 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1920 | * we get back out of this interrupt. |
1921 | */ | |
ab7ef2e5 | 1922 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1923 | |
ca8f2d7f PM |
1924 | if (nmi) |
1925 | nmi_exit(); | |
1926 | else | |
db4fb5ac | 1927 | irq_exit(); |
4574910e PM |
1928 | } |
1929 | ||
3f6da390 | 1930 | static void power_pmu_setup(int cpu) |
01d0287f | 1931 | { |
cdd6c482 | 1932 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1933 | |
f36a1a13 PM |
1934 | if (!ppmu) |
1935 | return; | |
01d0287f PM |
1936 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1937 | cpuhw->mmcr[0] = MMCR0_FC; | |
1938 | } | |
1939 | ||
061d19f2 | 1940 | static int |
85cfabbc | 1941 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1942 | { |
1943 | unsigned int cpu = (long)hcpu; | |
1944 | ||
1945 | switch (action & ~CPU_TASKS_FROZEN) { | |
1946 | case CPU_UP_PREPARE: | |
1947 | power_pmu_setup(cpu); | |
1948 | break; | |
1949 | ||
1950 | default: | |
1951 | break; | |
1952 | } | |
1953 | ||
1954 | return NOTIFY_OK; | |
1955 | } | |
1956 | ||
061d19f2 | 1957 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 1958 | { |
079b3c56 PM |
1959 | if (ppmu) |
1960 | return -EBUSY; /* something's already registered */ | |
1961 | ||
1962 | ppmu = pmu; | |
1963 | pr_info("%s performance monitor hardware support registered\n", | |
1964 | pmu->name); | |
d095cd46 | 1965 | |
1c53a270 SB |
1966 | power_pmu.attr_groups = ppmu->attr_groups; |
1967 | ||
98fb1807 | 1968 | #ifdef MSR_HV |
d095cd46 PM |
1969 | /* |
1970 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1971 | */ | |
1972 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1973 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1974 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1975 | |
2e80a82a | 1976 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
1977 | perf_cpu_notifier(power_pmu_notifier); |
1978 | ||
4574910e PM |
1979 | return 0; |
1980 | } |