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91bd6109 1/*
e00c5498 2 * MPC8272 ADS board support
91bd6109 3 *
e00c5498
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4 * Copyright 2007 Freescale Semiconductor, Inc.
5 * Author: Scott Wood <scottwood@freescale.com>
91bd6109 6 *
e00c5498 7 * Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
91bd6109
VB
8 * Copyright (c) 2006 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
91bd6109 16#include <linux/init.h>
91bd6109 17#include <linux/interrupt.h>
91bd6109 18#include <linux/fsl_devices.h>
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19#include <linux/of_platform.h>
20#include <linux/io.h>
91bd6109 21
91bd6109
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22#include <asm/cpm2.h>
23#include <asm/udbg.h>
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24#include <asm/machdep.h>
25#include <asm/time.h>
26
27#include <platforms/82xx/pq2.h>
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28
29#include <sysdev/fsl_soc.h>
14305601 30#include <sysdev/cpm2_pic.h>
91bd6109 31
5427828e 32#include "pq2ads.h"
e00c5498 33#include "pq2.h"
91bd6109 34
2d2294ae 35static void __init mpc8272_ads_pic_init(void)
91bd6109 36{
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37 struct device_node *np = of_find_compatible_node(NULL, NULL,
38 "fsl,cpm2-pic");
39 if (!np) {
40 printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
91bd6109
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41 return;
42 }
e00c5498 43
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44 cpm2_pic_init(np);
45 of_node_put(np);
46
91bd6109 47 /* Initialize stuff for the 82xx CPLD IC and install demux */
e00c5498 48 pq2ads_pci_init_irq();
91bd6109
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49}
50
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51struct cpm_pin {
52 int port, pin, flags;
53};
91bd6109 54
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55static struct cpm_pin mpc8272_ads_pins[] = {
56 /* SCC1 */
57 {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
58 {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
59
60 /* SCC4 */
61 {3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
62 {3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
63
64 /* FCC1 */
65 {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
66 {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
67 {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
68 {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
69 {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
70 {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
71 {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
72 {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
73 {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
74 {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
75 {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
76 {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
77 {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
78 {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
79 {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
80 {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
81
82 /* FCC2 */
83 {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
84 {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
85 {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
86 {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
87 {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
88 {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
89 {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
90 {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
91 {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
92 {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
93 {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
94 {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
95 {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
96 {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
97 {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
98 {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
a5d28c8e
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99
100 /* I2C */
101 {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
102 {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
e00c5498 103};
91bd6109 104
e00c5498 105static void __init init_ioports(void)
91bd6109 106{
e00c5498 107 int i;
91bd6109 108
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109 for (i = 0; i < ARRAY_SIZE(mpc8272_ads_pins); i++) {
110 struct cpm_pin *pin = &mpc8272_ads_pins[i];
111 cpm2_set_pin(pin->port, pin->pin, pin->flags);
91bd6109 112 }
91bd6109 113
e00c5498
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114 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
115 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
116 cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_RX);
117 cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_TX);
118 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
119 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
120 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK15, CPM_CLK_RX);
121 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK16, CPM_CLK_TX);
91bd6109
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122}
123
e00c5498 124static void __init mpc8272_ads_setup_arch(void)
91bd6109 125{
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126 struct device_node *np;
127 __be32 __iomem *bcsr;
91bd6109 128
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129 if (ppc_md.progress)
130 ppc_md.progress("mpc8272_ads_setup_arch()", 0);
91bd6109 131
e00c5498 132 cpm2_reset();
91bd6109 133
e00c5498 134 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8272ads-bcsr");
91bd6109 135 if (!np) {
e00c5498 136 printk(KERN_ERR "No bcsr in device tree\n");
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137 return;
138 }
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139
140 bcsr = of_iomap(np, 0);
75e89b02 141 of_node_put(np);
e00c5498
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142 if (!bcsr) {
143 printk(KERN_ERR "Cannot map BCSR registers\n");
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144 return;
145 }
91bd6109 146
e00c5498
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147 clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
148 setbits32(&bcsr[1], BCSR1_FETH_RST);
91bd6109 149
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150 clrbits32(&bcsr[3], BCSR3_FETHIEN2);
151 setbits32(&bcsr[3], BCSR3_FETH2_RST);
91bd6109 152
e00c5498 153 iounmap(bcsr);
91bd6109 154
e00c5498
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155 init_ioports();
156 pq2_init_pci();
91bd6109 157
e00c5498
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158 if (ppc_md.progress)
159 ppc_md.progress("mpc8272_ads_setup_arch(), finish", 0);
91bd6109
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160}
161
e00c5498
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162static struct of_device_id __initdata of_bus_ids[] = {
163 { .name = "soc", },
164 { .name = "cpm", },
165 { .name = "localbus", },
166 {},
91bd6109
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167};
168
e00c5498 169static int __init declare_of_platform_devices(void)
91bd6109 170{
e00c5498
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171 /* Publish the QE devices */
172 of_platform_bus_probe(NULL, of_bus_ids, NULL);
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173 return 0;
174}
ca956f0e 175machine_device_initcall(mpc8272_ads, declare_of_platform_devices);
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176
177/*
178 * Called very early, device-tree isn't unflattened
179 */
2d2294ae 180static int __init mpc8272_ads_probe(void)
91bd6109 181{
e00c5498
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182 unsigned long root = of_get_flat_dt_root();
183 return of_flat_dt_is_compatible(root, "fsl,mpc8272ads");
91bd6109
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184}
185
2d2294ae 186define_machine(mpc8272_ads)
91bd6109 187{
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188 .name = "Freescale MPC8272 ADS",
189 .probe = mpc8272_ads_probe,
190 .setup_arch = mpc8272_ads_setup_arch,
191 .init_IRQ = mpc8272_ads_pic_init,
192 .get_irq = cpm2_get_irq,
4ff62e1c 193 .calibrate_decr = generic_calibrate_decr,
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194 .restart = pq2_restart,
195 .progress = udbg_progress,
91bd6109 196};