[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / platforms / 85xx / mpc85xx_cds.c

/*
 * MPC85xx setup and early boot code plus other random bits.
 *
 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
 *
 * Copyright 2005 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/fsl_devices.h>
#include <linux/of_platform.h>

#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <linux/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/ipic.h>
#include <asm/pci-bridge.h>
#include <asm/irq.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <asm/i8259.h>

#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>

/* CADMUS info */
/* xxx - galak, move into device tree */
#define CADMUS_BASE (0xf8004000)
#define CADMUS_SIZE (256)
#define CM_VER	(0)
#define CM_CSR	(1)
#define CM_RST	(2)


static int cds_pci_slot = 2;
static volatile u8 *cadmus;

#ifdef CONFIG_PCI

#define ARCADIA_HOST_BRIDGE_IDSEL	17
#define ARCADIA_2ND_BRIDGE_IDSEL	3

static int mpc85xx_exclude_device(struct pci_controller *hose,
				  u_char bus, u_char devfn)
{
	/* We explicitly do not go past the Tundra 320 Bridge */
	if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
		return PCIBIOS_DEVICE_NOT_FOUND;
	if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
		return PCIBIOS_DEVICE_NOT_FOUND;
	else
		return PCIBIOS_SUCCESSFUL;
}

static void mpc85xx_cds_restart(char *cmd)
{
	struct pci_dev *dev;
	u_char tmp;

	if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
					NULL))) {

		/* Use the VIA Super Southbridge to force a PCI reset */
		pci_read_config_byte(dev, 0x47, &tmp);
		pci_write_config_byte(dev, 0x47, tmp | 1);

		/* Flush the outbound PCI write queues */
		pci_read_config_byte(dev, 0x47, &tmp);

		/*
		 *  At this point, the harware reset should have triggered.
		 *  However, if it doesn't work for some mysterious reason,
		 *  just fall through to the default reset below.
		 */

		pci_dev_put(dev);
	}

	/*
	 *  If we can't find the VIA chip (maybe the P2P bridge is disabled)
	 *  or the VIA chip reset didn't work, just use the default reset.
	 */
	fsl_rstcr_restart(NULL);
}

static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
{
	u_char c;
	if (dev->vendor == PCI_VENDOR_ID_VIA) {
		switch (dev->device) {
		case PCI_DEVICE_ID_VIA_82C586_1:
			/*
			 * U-Boot does not set the enable bits
			 * for the IDE device. Force them on here.
			 */
			pci_read_config_byte(dev, 0x40, &c);
			c |= 0x03; /* IDE: Chip Enable Bits */
			pci_write_config_byte(dev, 0x40, c);

			/*
			 * Since only primary interface works, force the
			 * IDE function to standard primary IDE interrupt
			 * w/ 8259 offset
			 */
			dev->irq = 14;
			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
			break;
		/*
		 * Force legacy USB interrupt routing
		 */
		case PCI_DEVICE_ID_VIA_82C586_2:
		/* There are two USB controllers.
		 * Identify them by functon number
		 */
			if (PCI_FUNC(dev->devfn) == 3)
				dev->irq = 11;
			else
				dev->irq = 10;
			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
		default:
			break;
		}
	}
}

static void __devinit skip_fake_bridge(struct pci_dev *dev)
{
	/* Make it an error to skip the fake bridge
	 * in pci_setup_device() in probe.c */
	dev->hdr_type = 0x7f;
}
DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);

#ifdef CONFIG_PPC_I8259
static void mpc85xx_8259_cascade_handler(unsigned int irq,
					 struct irq_desc *desc)
{
	unsigned int cascade_irq = i8259_irq();

	if (cascade_irq != NO_IRQ)
		/* handle an interrupt from the 8259 */
		generic_handle_irq(cascade_irq);

	/* check for any interrupts from the shared IRQ line */
	handle_fasteoi_irq(irq, desc);
}

static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
{
	return IRQ_HANDLED;
}

static struct irqaction mpc85xxcds_8259_irqaction = {
	.handler = mpc85xx_8259_cascade_action,
	.flags = IRQF_SHARED,
	.name = "8259 cascade",
};
#endif /* PPC_I8259 */
#endif /* CONFIG_PCI */

static void __init mpc85xx_cds_pic_init(void)
{
	struct mpic *mpic;
	struct resource r;
	struct device_node *np = NULL;

	np = of_find_node_by_type(np, "open-pic");

	if (np == NULL) {
		printk(KERN_ERR "Could not find open-pic node\n");
		return;
	}

	if (of_address_to_resource(np, 0, &r)) {
		printk(KERN_ERR "Failed to map mpic register space\n");
		of_node_put(np);
		return;
	}

	mpic = mpic_alloc(np, r.start,
			MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
			0, 256, " OpenPIC  ");
	BUG_ON(mpic == NULL);

	/* Return the mpic node */
	of_node_put(np);

	mpic_init(mpic);
}

#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
static int mpc85xx_cds_8259_attach(void)
{
	int ret;
	struct device_node *np = NULL;
	struct device_node *cascade_node = NULL;
	int cascade_irq;

	/* Initialize the i8259 controller */
	for_each_node_by_type(np, "interrupt-controller")
		if (of_device_is_compatible(np, "chrp,iic")) {
			cascade_node = np;
			break;
		}

	if (cascade_node == NULL) {
		printk(KERN_DEBUG "Could not find i8259 PIC\n");
		return -ENODEV;
	}

	cascade_irq = irq_of_parse_and_map(cascade_node, 0);
	if (cascade_irq == NO_IRQ) {
		printk(KERN_ERR "Failed to map cascade interrupt\n");
		return -ENXIO;
	}

	i8259_init(cascade_node, 0);
	of_node_put(cascade_node);

	/*
	 *  Hook the interrupt to make sure desc->action is never NULL.
	 *  This is required to ensure that the interrupt does not get
	 *  disabled when the last user of the shared IRQ line frees their
	 *  interrupt.
	 */
	if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
		printk(KERN_ERR "Failed to setup cascade interrupt\n");
		return ret;
	}

	/* Success. Connect our low-level cascade handler. */
	irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);

	return 0;
}
machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);

#endif /* CONFIG_PPC_I8259 */

/*
 * Setup the architecture
 */
static void __init mpc85xx_cds_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
#endif

	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_cds_setup_arch()", 0);

	cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
	cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;

	if (ppc_md.progress) {
		char buf[40];
		snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
				cadmus[CM_VER], cds_pci_slot);
		ppc_md.progress(buf, 0);
	}

#ifdef CONFIG_PCI
	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
		    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
			struct resource rsrc;
			of_address_to_resource(np, 0, &rsrc);
			if ((rsrc.start & 0xfffff) == 0x8000)
				fsl_add_bridge(np, 1);
			else
				fsl_add_bridge(np, 0);
		}
	}

	ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
}

static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
{
	uint pvid, svid, phid1;

	pvid = mfspr(SPRN_PVR);
	svid = mfspr(SPRN_SVR);

	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
	seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
	seq_printf(m, "SVR\t\t: 0x%x\n", svid);

	/* Display cpu Pll setting */
	phid1 = mfspr(SPRN_HID1);
	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
}


/*
 * Called very early, device-tree isn't unflattened
 */
static int __init mpc85xx_cds_probe(void)
{
        unsigned long root = of_get_flat_dt_root();

        return of_flat_dt_is_compatible(root, "MPC85xxCDS");
}

static struct of_device_id __initdata of_bus_ids[] = {
	{ .type = "soc", },
	{ .compatible = "soc", },
	{ .compatible = "simple-bus", },
	{ .compatible = "gianfar", },
	{},
};

static int __init declare_of_platform_devices(void)
{
	return of_platform_bus_probe(NULL, of_bus_ids, NULL);
}
machine_device_initcall(mpc85xx_cds, declare_of_platform_devices);

define_machine(mpc85xx_cds) {
	.name		= "MPC85xx CDS",
	.probe		= mpc85xx_cds_probe,
	.setup_arch	= mpc85xx_cds_setup_arch,
	.init_IRQ	= mpc85xx_cds_pic_init,
	.show_cpuinfo	= mpc85xx_cds_show_cpuinfo,
	.get_irq	= mpic_get_irq,
#ifdef CONFIG_PCI
	.restart	= mpc85xx_cds_restart,
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#else
	.restart	= fsl_rstcr_restart,
#endif
	.calibrate_decr = generic_calibrate_decr,
	.progress	= udbg_progress,
};
Commit	Line	Data
591f0a42 AF	1	/*
	2	* MPC85xx setup and early boot code plus other random bits.
	3	*
	4	* Maintained by Kumar Gala (see MAINTAINERS for contact information)
	5	*
	6	* Copyright 2005 Freescale Semiconductor Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
591f0a42 AF	14	#include <linux/stddef.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/errno.h>
	18	#include <linux/reboot.h>
	19	#include <linux/pci.h>
	20	#include <linux/kdev_t.h>
	21	#include <linux/major.h>
	22	#include <linux/console.h>
	23	#include <linux/delay.h>
	24	#include <linux/seq_file.h>
591f0a42 AF	25	#include <linux/initrd.h>
591f0a42 AF	26	#include <linux/module.h>
3620fc1d	27	#include <linux/interrupt.h>
591f0a42	28	#include <linux/fsl_devices.h>
a64887eb	29	#include <linux/of_platform.h>
591f0a42 AF	30
	31	#include <asm/system.h>
	32	#include <asm/pgtable.h>
	33	#include <asm/page.h>
60063497	34	#include <linux/atomic.h>
591f0a42 AF	35	#include <asm/time.h>
	36	#include <asm/io.h>
	37	#include <asm/machdep.h>
	38	#include <asm/ipic.h>
591f0a42	39	#include <asm/pci-bridge.h>
591f0a42 AF	40	#include <asm/irq.h>
	41	#include <mm/mmu_decl.h>
	42	#include <asm/prom.h>
	43	#include <asm/udbg.h>
	44	#include <asm/mpic.h>
	45	#include <asm/i8259.h>
	46
	47	#include <sysdev/fsl_soc.h>
3f6c5dae	48	#include <sysdev/fsl_pci.h>
591f0a42	49
0bfd5df5 KG	50	/* CADMUS info */
	51	/* xxx - galak, move into device tree */
	52	#define CADMUS_BASE (0xf8004000)
	53	#define CADMUS_SIZE (256)
	54	#define CM_VER (0)
	55	#define CM_CSR (1)
	56	#define CM_RST (2)
	57
	58
591f0a42 AF	59	static int cds_pci_slot = 2;
	60	static volatile u8 *cadmus;
	61
591f0a42	62	#ifdef CONFIG_PCI
591f0a42 AF	63
	64	#define ARCADIA_HOST_BRIDGE_IDSEL 17
	65	#define ARCADIA_2ND_BRIDGE_IDSEL 3
	66
7d52c7b0 KG	67	static int mpc85xx_exclude_device(struct pci_controller *hose,
7d52c7b0 KG	68	u_char bus, u_char devfn)
591f0a42	69	{
591f0a42 AF	70	/* We explicitly do not go past the Tundra 320 Bridge */
	71	if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
	72	return PCIBIOS_DEVICE_NOT_FOUND;
	73	if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
	74	return PCIBIOS_DEVICE_NOT_FOUND;
	75	else
	76	return PCIBIOS_SUCCESSFUL;
	77	}
	78
637e9e13 RV	79	static void mpc85xx_cds_restart(char *cmd)
	80	{
	81	struct pci_dev *dev;
	82	u_char tmp;
	83
	84	if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
	85	NULL))) {
	86
	87	/* Use the VIA Super Southbridge to force a PCI reset */
	88	pci_read_config_byte(dev, 0x47, &tmp);
	89	pci_write_config_byte(dev, 0x47, tmp \| 1);
	90
	91	/* Flush the outbound PCI write queues */
	92	pci_read_config_byte(dev, 0x47, &tmp);
	93
	94	/*
	95	* At this point, the harware reset should have triggered.
	96	* However, if it doesn't work for some mysterious reason,
	97	* just fall through to the default reset below.
	98	*/
	99
	100	pci_dev_put(dev);
	101	}
	102
	103	/*
	104	* If we can't find the VIA chip (maybe the P2P bridge is disabled)
	105	* or the VIA chip reset didn't work, just use the default reset.
	106	*/
e1c1575f	107	fsl_rstcr_restart(NULL);
637e9e13 RV	108	}
637e9e13 RV	109
749e8081	110	static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
591f0a42	111	{
749e8081 RZ	112	u_char c;
	113	if (dev->vendor == PCI_VENDOR_ID_VIA) {
	114	switch (dev->device) {
	115	case PCI_DEVICE_ID_VIA_82C586_1:
	116	/*
	117	* U-Boot does not set the enable bits
	118	* for the IDE device. Force them on here.
	119	*/
	120	pci_read_config_byte(dev, 0x40, &c);
	121	c \|= 0x03; /* IDE: Chip Enable Bits */
	122	pci_write_config_byte(dev, 0x40, c);
	123
	124	/*
	125	* Since only primary interface works, force the
	126	* IDE function to standard primary IDE interrupt
	127	* w/ 8259 offset
	128	*/
	129	dev->irq = 14;
	130	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
	131	break;
591f0a42	132	/*
749e8081	133	* Force legacy USB interrupt routing
591f0a42	134	*/
749e8081 RZ	135	case PCI_DEVICE_ID_VIA_82C586_2:
	136	/* There are two USB controllers.
	137	* Identify them by functon number
591f0a42	138	*/
8d7bc8f9	139	if (PCI_FUNC(dev->devfn) == 3)
749e8081 RZ	140	dev->irq = 11;
	141	else
	142	dev->irq = 10;
	143	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
	144	default:
	145	break;
	146	}
591f0a42	147	}
ddd64159 AF	148	}
ddd64159 AF	149
4e798211 KG	150	static void __devinit skip_fake_bridge(struct pci_dev *dev)
	151	{
	152	/* Make it an error to skip the fake bridge
	153	* in pci_setup_device() in probe.c */
	154	dev->hdr_type = 0x7f;
	155	}
	156	DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
	157	DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
	158	DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
	159
ddd64159	160	#ifdef CONFIG_PPC_I8259
3620fc1d RV	161	static void mpc85xx_8259_cascade_handler(unsigned int irq,
3620fc1d RV	162	struct irq_desc *desc)
ddd64159	163	{
35a84c2f	164	unsigned int cascade_irq = i8259_irq();
ddd64159 AF	165
ddd64159 AF	166	if (cascade_irq != NO_IRQ)
3620fc1d	167	/* handle an interrupt from the 8259 */
49f19ce4	168	generic_handle_irq(cascade_irq);
ddd64159	169
3620fc1d RV	170	/* check for any interrupts from the shared IRQ line */
3620fc1d RV	171	handle_fasteoi_irq(irq, desc);
591f0a42	172	}
3620fc1d RV	173
	174	static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
	175	{
	176	return IRQ_HANDLED;
	177	}
	178
	179	static struct irqaction mpc85xxcds_8259_irqaction = {
	180	.handler = mpc85xx_8259_cascade_action,
	181	.flags = IRQF_SHARED,
3620fc1d RV	182	.name = "8259 cascade",
3620fc1d RV	183	};
ddd64159	184	#endif /* PPC_I8259 */
591f0a42 AF	185	#endif /* CONFIG_PCI */
591f0a42 AF	186
27630bec	187	static void __init mpc85xx_cds_pic_init(void)
591f0a42	188	{
ddd64159 AF	189	struct mpic *mpic;
	190	struct resource r;
	191	struct device_node *np = NULL;
591f0a42	192
ddd64159 AF	193	np = of_find_node_by_type(np, "open-pic");
	194
	195	if (np == NULL) {
	196	printk(KERN_ERR "Could not find open-pic node\n");
	197	return;
	198	}
591f0a42	199
ddd64159 AF	200	if (of_address_to_resource(np, 0, &r)) {
	201	printk(KERN_ERR "Failed to map mpic register space\n");
	202	of_node_put(np);
	203	return;
	204	}
	205
	206	mpic = mpic_alloc(np, r.start,
591f0a42	207	MPIC_PRIMARY \| MPIC_WANTS_RESET \| MPIC_BIG_ENDIAN,
b533f8ae	208	0, 256, " OpenPIC ");
ddd64159 AF	209	BUG_ON(mpic == NULL);
	210
	211	/* Return the mpic node */
	212	of_node_put(np);
	213
ddd64159	214	mpic_init(mpic);
bca03c6b	215	}
ddd64159	216
3620fc1d	217	#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
bca03c6b RV	218	static int mpc85xx_cds_8259_attach(void)
	219	{
	220	int ret;
	221	struct device_node *np = NULL;
	222	struct device_node *cascade_node = NULL;
	223	int cascade_irq;
	224
ddd64159 AF	225	/* Initialize the i8259 controller */
ddd64159 AF	226	for_each_node_by_type(np, "interrupt-controller")
55b61fec	227	if (of_device_is_compatible(np, "chrp,iic")) {
ddd64159 AF	228	cascade_node = np;
	229	break;
	230	}
	231
	232	if (cascade_node == NULL) {
	233	printk(KERN_DEBUG "Could not find i8259 PIC\n");
bca03c6b	234	return -ENODEV;
ddd64159	235	}
591f0a42	236
ddd64159 AF	237	cascade_irq = irq_of_parse_and_map(cascade_node, 0);
	238	if (cascade_irq == NO_IRQ) {
	239	printk(KERN_ERR "Failed to map cascade interrupt\n");
bca03c6b	240	return -ENXIO;
ddd64159	241	}
591f0a42	242
ddd64159 AF	243	i8259_init(cascade_node, 0);
	244	of_node_put(cascade_node);
	245
3620fc1d RV	246	/*
	247	* Hook the interrupt to make sure desc->action is never NULL.
	248	* This is required to ensure that the interrupt does not get
	249	* disabled when the last user of the shared IRQ line frees their
	250	* interrupt.
	251	*/
bca03c6b	252	if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
3620fc1d	253	printk(KERN_ERR "Failed to setup cascade interrupt\n");
bca03c6b RV	254	return ret;
	255	}
	256
	257	/* Success. Connect our low-level cascade handler. */
ec775d0e	258	irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
bca03c6b RV	259
bca03c6b RV	260	return 0;
591f0a42	261	}
277982e2	262	machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
bca03c6b RV	263
	264	#endif /* CONFIG_PPC_I8259 */
	265
591f0a42 AF	266	/*
	267	* Setup the architecture
	268	*/
27630bec	269	static void __init mpc85xx_cds_setup_arch(void)
591f0a42	270	{
591f0a42 AF	271	#ifdef CONFIG_PCI
	272	struct device_node *np;
	273	#endif
	274
	275	if (ppc_md.progress)
	276	ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
	277
591f0a42 AF	278	cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
	279	cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
	280
	281	if (ppc_md.progress) {
	282	char buf[40];
	283	snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
	284	cadmus[CM_VER], cds_pci_slot);
	285	ppc_md.progress(buf, 0);
	286	}
	287
	288	#ifdef CONFIG_PCI
c9438aff KG	289	for_each_node_by_type(np, "pci") {
	290	if (of_device_is_compatible(np, "fsl,mpc8540-pci") \|\|
	291	of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
	292	struct resource rsrc;
	293	of_address_to_resource(np, 0, &rsrc);
	294	if ((rsrc.start & 0xfffff) == 0x8000)
	295	fsl_add_bridge(np, 1);
	296	else
	297	fsl_add_bridge(np, 0);
	298	}
3f6c5dae	299	}
c9438aff	300
749e8081	301	ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
591f0a42 AF	302	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
591f0a42 AF	303	#endif
591f0a42 AF	304	}
591f0a42 AF	305
27630bec	306	static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
591f0a42 AF	307	{
591f0a42 AF	308	uint pvid, svid, phid1;
591f0a42 AF	309
	310	pvid = mfspr(SPRN_PVR);
	311	svid = mfspr(SPRN_SVR);
	312
	313	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
	314	seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
	315	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
	316	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
	317
	318	/* Display cpu Pll setting */
	319	phid1 = mfspr(SPRN_HID1);
	320	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
591f0a42 AF	321	}
	322
	323
	324	/*
	325	* Called very early, device-tree isn't unflattened
	326	*/
	327	static int __init mpc85xx_cds_probe(void)
	328	{
6936c625 KG	329	unsigned long root = of_get_flat_dt_root();
	330
	331	return of_flat_dt_is_compatible(root, "MPC85xxCDS");
591f0a42 AF	332	}
591f0a42 AF	333
a64887eb DJ	334	static struct of_device_id __initdata of_bus_ids[] = {
	335	{ .type = "soc", },
	336	{ .compatible = "soc", },
	337	{ .compatible = "simple-bus", },
84ba4a58	338	{ .compatible = "gianfar", },
a64887eb DJ	339	{},
	340	};
	341
	342	static int __init declare_of_platform_devices(void)
	343	{
	344	return of_platform_bus_probe(NULL, of_bus_ids, NULL);
	345	}
	346	machine_device_initcall(mpc85xx_cds, declare_of_platform_devices);
	347
591f0a42 AF	348	define_machine(mpc85xx_cds) {
	349	.name = "MPC85xx CDS",
	350	.probe = mpc85xx_cds_probe,
	351	.setup_arch = mpc85xx_cds_setup_arch,
	352	.init_IRQ = mpc85xx_cds_pic_init,
	353	.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
	354	.get_irq = mpic_get_irq,
637e9e13 RV	355	#ifdef CONFIG_PCI
637e9e13 RV	356	.restart = mpc85xx_cds_restart,
2af8569d	357	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
637e9e13	358	#else
e1c1575f	359	.restart = fsl_rstcr_restart,
637e9e13	360	#endif
591f0a42 AF	361	.calibrate_decr = generic_calibrate_decr,
	362	.progress = udbg_progress,
	363	};