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4ca4b627 JL |
1 | /* |
2 | * Author: Xianghua Xiao <x.xiao@freescale.com> | |
3 | * Zhang Wei <wei.zhang@freescale.com> | |
4 | * | |
5 | * Copyright 2006 Freescale Semiconductor Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
4ca4b627 JL |
13 | #include <linux/stddef.h> |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | ||
aaddd3ea | 18 | #include <asm/code-patching.h> |
4ca4b627 | 19 | #include <asm/page.h> |
f1a1eb29 | 20 | #include <asm/pgtable.h> |
4ca4b627 JL |
21 | #include <asm/pci-bridge.h> |
22 | #include <asm-powerpc/mpic.h> | |
23 | #include <asm/mpc86xx.h> | |
24 | #include <asm/cacheflush.h> | |
25 | ||
26 | #include <sysdev/fsl_soc.h> | |
27 | ||
28 | #include "mpc86xx.h" | |
29 | ||
30 | extern void __secondary_start_mpc86xx(void); | |
31 | extern unsigned long __secondary_hold_acknowledge; | |
32 | ||
33 | ||
34 | static void __init | |
35 | smp_86xx_release_core(int nr) | |
36 | { | |
9ad494f6 KG |
37 | __be32 __iomem *mcm_vaddr; |
38 | unsigned long pcr; | |
4ca4b627 JL |
39 | |
40 | if (nr < 0 || nr >= NR_CPUS) | |
41 | return; | |
42 | ||
43 | /* | |
44 | * Startup Core #nr. | |
45 | */ | |
46 | mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET, | |
47 | MPC86xx_MCM_SIZE); | |
9ad494f6 | 48 | pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2)); |
4ca4b627 | 49 | pcr |= 1 << (nr + 24); |
9ad494f6 | 50 | out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr); |
4ca4b627 JL |
51 | } |
52 | ||
53 | ||
54 | static void __init | |
55 | smp_86xx_kick_cpu(int nr) | |
56 | { | |
57 | unsigned int save_vector; | |
58 | unsigned long target, flags; | |
59 | int n = 0; | |
e7a57273 | 60 | unsigned int *vector = (unsigned int *)(KERNELBASE + 0x100); |
4ca4b627 JL |
61 | |
62 | if (nr < 0 || nr >= NR_CPUS) | |
63 | return; | |
64 | ||
65 | pr_debug("smp_86xx_kick_cpu: kick CPU #%d\n", nr); | |
66 | ||
67 | local_irq_save(flags); | |
4ca4b627 JL |
68 | |
69 | /* Save reset vector */ | |
70 | save_vector = *vector; | |
71 | ||
72 | /* Setup fake reset vector to call __secondary_start_mpc86xx. */ | |
73 | target = (unsigned long) __secondary_start_mpc86xx; | |
e7a57273 | 74 | patch_branch(vector, target, BRANCH_SET_LINK); |
4ca4b627 JL |
75 | |
76 | /* Kick that CPU */ | |
77 | smp_86xx_release_core(nr); | |
78 | ||
79 | /* Wait a bit for the CPU to take the exception. */ | |
80 | while ((__secondary_hold_acknowledge != nr) && (n++, n < 1000)) | |
81 | mdelay(1); | |
82 | ||
83 | /* Restore the exception vector */ | |
84 | *vector = save_vector; | |
85 | flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); | |
86 | ||
87 | local_irq_restore(flags); | |
88 | ||
89 | pr_debug("wait CPU #%d for %d msecs.\n", nr, n); | |
90 | } | |
91 | ||
92 | ||
93 | static void __init | |
94 | smp_86xx_setup_cpu(int cpu_nr) | |
95 | { | |
96 | mpic_setup_this_cpu(); | |
97 | } | |
98 | ||
99 | ||
100 | struct smp_ops_t smp_86xx_ops = { | |
101 | .message_pass = smp_mpic_message_pass, | |
102 | .probe = smp_mpic_probe, | |
103 | .kick_cpu = smp_86xx_kick_cpu, | |
104 | .setup_cpu = smp_86xx_setup_cpu, | |
105 | .take_timebase = smp_generic_take_timebase, | |
106 | .give_timebase = smp_generic_give_timebase, | |
107 | }; | |
108 | ||
109 | ||
110 | void __init | |
111 | mpc86xx_smp_init(void) | |
112 | { | |
113 | smp_ops = &smp_86xx_ops; | |
114 | } |