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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2001 Allan Trautman, IBM Corporation |
1dee2026 | 3 | * Copyright (C) 2005,2007 Stephen Rothwell, IBM Corp |
1da177e4 LT |
4 | * |
5 | * iSeries specific routines for PCI. | |
d387899f | 6 | * |
1da177e4 LT |
7 | * Based on code from pci.c and iSeries_pci.c 32bit |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
d387899f | 13 | * |
1da177e4 LT |
14 | * This program is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
d387899f | 18 | * |
1da177e4 LT |
19 | * You should have received a copy of the GNU General Public License |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
50c9bc2f BH |
23 | |
24 | #undef DEBUG | |
25 | ||
59861bc6 | 26 | #include <linux/jiffies.h> |
1da177e4 | 27 | #include <linux/kernel.h> |
d387899f | 28 | #include <linux/list.h> |
1da177e4 | 29 | #include <linux/string.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include <linux/init.h> |
32 | #include <linux/module.h> | |
1da177e4 | 33 | #include <linux/pci.h> |
885b86e4 | 34 | #include <linux/of.h> |
1da177e4 | 35 | |
1dee2026 | 36 | #include <asm/types.h> |
1da177e4 LT |
37 | #include <asm/io.h> |
38 | #include <asm/irq.h> | |
39 | #include <asm/prom.h> | |
40 | #include <asm/machdep.h> | |
41 | #include <asm/pci-bridge.h> | |
1da177e4 | 42 | #include <asm/iommu.h> |
426c1a11 | 43 | #include <asm/abs_addr.h> |
caf81329 | 44 | #include <asm/firmware.h> |
1da177e4 | 45 | |
1dee2026 | 46 | #include <asm/iseries/hv_types.h> |
8021b8a7 | 47 | #include <asm/iseries/hv_call_xm.h> |
bbc8b628 | 48 | #include <asm/iseries/mf.h> |
c7f0e8cb | 49 | #include <asm/iseries/iommu.h> |
1da177e4 | 50 | |
d387899f | 51 | #include <asm/ppc-pci.h> |
1da177e4 | 52 | |
b08567cb | 53 | #include "irq.h" |
426c1a11 | 54 | #include "pci.h" |
c6d2ea92 | 55 | #include "call_pci.h" |
b08567cb | 56 | |
b9b1812c SR |
57 | #define PCI_RETRY_MAX 3 |
58 | static int limit_pci_retries = 1; /* Set Retry Error on. */ | |
1da177e4 | 59 | |
1da177e4 LT |
60 | /* |
61 | * Table defines | |
62 | * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space. | |
63 | */ | |
64 | #define IOMM_TABLE_MAX_ENTRIES 1024 | |
65 | #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL | |
66 | #define BASE_IO_MEMORY 0xE000000000000000UL | |
50c9bc2f | 67 | #define END_IO_MEMORY 0xEFFFFFFFFFFFFFFFUL |
1da177e4 | 68 | |
b58b7f98 | 69 | static unsigned long max_io_memory = BASE_IO_MEMORY; |
1da177e4 LT |
70 | static long current_iomm_table_entry; |
71 | ||
72 | /* | |
73 | * Lookup Tables. | |
74 | */ | |
b58b7f98 | 75 | static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES]; |
885b86e4 | 76 | static u64 ds_addr_table[IOMM_TABLE_MAX_ENTRIES]; |
1da177e4 | 77 | |
1da177e4 LT |
78 | static DEFINE_SPINLOCK(iomm_table_lock); |
79 | ||
2cd1008c SR |
80 | /* |
81 | * Generate a Direct Select Address for the Hypervisor | |
82 | */ | |
83 | static inline u64 iseries_ds_addr(struct device_node *node) | |
84 | { | |
85 | struct pci_dn *pdn = PCI_DN(node); | |
885b86e4 | 86 | const u32 *sbp = of_get_property(node, "linux,subbus", NULL); |
2cd1008c | 87 | |
885b86e4 | 88 | return ((u64)pdn->busno << 48) + ((u64)(sbp ? *sbp : 0) << 40) |
2cd1008c SR |
89 | + ((u64)0x10 << 32); |
90 | } | |
91 | ||
1dee2026 SR |
92 | /* |
93 | * Size of Bus VPD data | |
94 | */ | |
95 | #define BUS_VPDSIZE 1024 | |
96 | ||
97 | /* | |
98 | * Bus Vpd Tags | |
99 | */ | |
100 | #define VPD_END_OF_AREA 0x79 | |
101 | #define VPD_ID_STRING 0x82 | |
102 | #define VPD_VENDOR_AREA 0x84 | |
103 | ||
104 | /* | |
105 | * Mfg Area Tags | |
106 | */ | |
107 | #define VPD_FRU_FRAME_ID 0x4649 /* "FI" */ | |
108 | #define VPD_SLOT_MAP_FORMAT 0x4D46 /* "MF" */ | |
109 | #define VPD_SLOT_MAP 0x534D /* "SM" */ | |
110 | ||
111 | /* | |
112 | * Structures of the areas | |
113 | */ | |
114 | struct mfg_vpd_area { | |
115 | u16 tag; | |
116 | u8 length; | |
117 | u8 data1; | |
118 | u8 data2; | |
119 | }; | |
120 | #define MFG_ENTRY_SIZE 3 | |
121 | ||
122 | struct slot_map { | |
123 | u8 agent; | |
124 | u8 secondary_agent; | |
125 | u8 phb; | |
126 | char card_location[3]; | |
127 | char parms[8]; | |
128 | char reserved[2]; | |
129 | }; | |
130 | #define SLOT_ENTRY_SIZE 16 | |
131 | ||
132 | /* | |
133 | * Parse the Slot Area | |
134 | */ | |
135 | static void __init iseries_parse_slot_area(struct slot_map *map, int len, | |
136 | HvAgentId agent, u8 *phb, char card[4]) | |
137 | { | |
138 | /* | |
139 | * Parse Slot label until we find the one requested | |
140 | */ | |
141 | while (len > 0) { | |
142 | if (map->agent == agent) { | |
143 | /* | |
144 | * If Phb wasn't found, grab the entry first one found. | |
145 | */ | |
146 | if (*phb == 0xff) | |
147 | *phb = map->phb; | |
148 | /* Found it, extract the data. */ | |
149 | if (map->phb == *phb) { | |
150 | memcpy(card, &map->card_location, 3); | |
151 | card[3] = 0; | |
152 | break; | |
153 | } | |
154 | } | |
155 | /* Point to the next Slot */ | |
156 | map = (struct slot_map *)((char *)map + SLOT_ENTRY_SIZE); | |
157 | len -= SLOT_ENTRY_SIZE; | |
158 | } | |
159 | } | |
160 | ||
161 | /* | |
162 | * Parse the Mfg Area | |
163 | */ | |
164 | static void __init iseries_parse_mfg_area(struct mfg_vpd_area *area, int len, | |
165 | HvAgentId agent, u8 *phb, u8 *frame, char card[4]) | |
166 | { | |
167 | u16 slot_map_fmt = 0; | |
168 | ||
169 | /* Parse Mfg Data */ | |
170 | while (len > 0) { | |
171 | int mfg_tag_len = area->length; | |
172 | /* Frame ID (FI 4649020310 ) */ | |
173 | if (area->tag == VPD_FRU_FRAME_ID) | |
174 | *frame = area->data1; | |
175 | /* Slot Map Format (MF 4D46020004 ) */ | |
176 | else if (area->tag == VPD_SLOT_MAP_FORMAT) | |
177 | slot_map_fmt = (area->data1 * 256) | |
178 | + area->data2; | |
179 | /* Slot Map (SM 534D90 */ | |
180 | else if (area->tag == VPD_SLOT_MAP) { | |
181 | struct slot_map *slot_map; | |
182 | ||
183 | if (slot_map_fmt == 0x1004) | |
184 | slot_map = (struct slot_map *)((char *)area | |
185 | + MFG_ENTRY_SIZE + 1); | |
186 | else | |
187 | slot_map = (struct slot_map *)((char *)area | |
188 | + MFG_ENTRY_SIZE); | |
189 | iseries_parse_slot_area(slot_map, mfg_tag_len, | |
190 | agent, phb, card); | |
191 | } | |
192 | /* | |
193 | * Point to the next Mfg Area | |
194 | * Use defined size, sizeof give wrong answer | |
195 | */ | |
196 | area = (struct mfg_vpd_area *)((char *)area + mfg_tag_len | |
197 | + MFG_ENTRY_SIZE); | |
198 | len -= (mfg_tag_len + MFG_ENTRY_SIZE); | |
199 | } | |
200 | } | |
201 | ||
202 | /* | |
203 | * Look for "BUS".. Data is not Null terminated. | |
204 | * PHBID of 0xFF indicates PHB was not found in VPD Data. | |
205 | */ | |
206 | static u8 __init iseries_parse_phbid(u8 *area, int len) | |
207 | { | |
208 | while (len > 0) { | |
209 | if ((*area == 'B') && (*(area + 1) == 'U') | |
210 | && (*(area + 2) == 'S')) { | |
211 | area += 3; | |
212 | while (*area == ' ') | |
213 | area++; | |
214 | return *area & 0x0F; | |
215 | } | |
216 | area++; | |
217 | len--; | |
218 | } | |
219 | return 0xff; | |
220 | } | |
221 | ||
222 | /* | |
223 | * Parse out the VPD Areas | |
224 | */ | |
225 | static void __init iseries_parse_vpd(u8 *data, int data_len, | |
226 | HvAgentId agent, u8 *frame, char card[4]) | |
227 | { | |
228 | u8 phb = 0xff; | |
229 | ||
230 | while (data_len > 0) { | |
231 | int len; | |
232 | u8 tag = *data; | |
233 | ||
234 | if (tag == VPD_END_OF_AREA) | |
235 | break; | |
236 | len = *(data + 1) + (*(data + 2) * 256); | |
237 | data += 3; | |
238 | data_len -= 3; | |
239 | if (tag == VPD_ID_STRING) | |
240 | phb = iseries_parse_phbid(data, len); | |
241 | else if (tag == VPD_VENDOR_AREA) | |
242 | iseries_parse_mfg_area((struct mfg_vpd_area *)data, len, | |
243 | agent, &phb, frame, card); | |
244 | /* Point to next Area. */ | |
245 | data += len; | |
246 | data_len -= len; | |
247 | } | |
248 | } | |
249 | ||
250 | static int __init iseries_get_location_code(u16 bus, HvAgentId agent, | |
251 | u8 *frame, char card[4]) | |
252 | { | |
253 | int status = 0; | |
254 | int bus_vpd_len = 0; | |
255 | u8 *bus_vpd = kmalloc(BUS_VPDSIZE, GFP_KERNEL); | |
256 | ||
257 | if (bus_vpd == NULL) { | |
258 | printk("PCI: Bus VPD Buffer allocation failure.\n"); | |
259 | return 0; | |
260 | } | |
261 | bus_vpd_len = HvCallPci_getBusVpd(bus, iseries_hv_addr(bus_vpd), | |
262 | BUS_VPDSIZE); | |
263 | if (bus_vpd_len == 0) { | |
264 | printk("PCI: Bus VPD Buffer zero length.\n"); | |
265 | goto out_free; | |
266 | } | |
267 | /* printk("PCI: bus_vpd: %p, %d\n",bus_vpd, bus_vpd_len); */ | |
268 | /* Make sure this is what I think it is */ | |
269 | if (*bus_vpd != VPD_ID_STRING) { | |
270 | printk("PCI: Bus VPD Buffer missing starting tag.\n"); | |
271 | goto out_free; | |
272 | } | |
273 | iseries_parse_vpd(bus_vpd, bus_vpd_len, agent, frame, card); | |
274 | status = 1; | |
275 | out_free: | |
276 | kfree(bus_vpd); | |
277 | return status; | |
278 | } | |
279 | ||
280 | /* | |
281 | * Prints the device information. | |
282 | * - Pass in pci_dev* pointer to the device. | |
283 | * - Pass in the device count | |
284 | * | |
285 | * Format: | |
286 | * PCI: Bus 0, Device 26, Vendor 0x12AE Frame 1, Card C10 Ethernet | |
287 | * controller | |
288 | */ | |
50c9bc2f BH |
289 | static void __init iseries_device_information(struct pci_dev *pdev, |
290 | u16 bus, HvSubBusNumber subbus) | |
1dee2026 SR |
291 | { |
292 | u8 frame = 0; | |
293 | char card[4]; | |
294 | HvAgentId agent; | |
295 | ||
296 | agent = ISERIES_PCI_AGENTID(ISERIES_GET_DEVICE_FROM_SUBBUS(subbus), | |
297 | ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus)); | |
298 | ||
299 | if (iseries_get_location_code(bus, agent, &frame, card)) { | |
50c9bc2f BH |
300 | printk(KERN_INFO "PCI: %s, Vendor %04X Frame%3d, " |
301 | "Card %4s 0x%04X\n", pci_name(pdev), pdev->vendor, | |
302 | frame, card, (int)(pdev->class >> 8)); | |
1dee2026 SR |
303 | } |
304 | } | |
305 | ||
1da177e4 LT |
306 | /* |
307 | * iomm_table_allocate_entry | |
308 | * | |
309 | * Adds pci_dev entry in address translation table | |
310 | * | |
311 | * - Allocates the number of entries required in table base on BAR | |
312 | * size. | |
313 | * - Allocates starting at BASE_IO_MEMORY and increases. | |
314 | * - The size is round up to be a multiple of entry size. | |
315 | * - CurrentIndex is incremented to keep track of the last entry. | |
316 | * - Builds the resource entry for allocated BARs. | |
317 | */ | |
1e105904 | 318 | static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) |
1da177e4 LT |
319 | { |
320 | struct resource *bar_res = &dev->resource[bar_num]; | |
321 | long bar_size = pci_resource_len(dev, bar_num); | |
d7b41b1f | 322 | struct device_node *dn = pci_device_to_OF_node(dev); |
1da177e4 LT |
323 | |
324 | /* | |
325 | * No space to allocate, quick exit, skip Allocation. | |
326 | */ | |
327 | if (bar_size == 0) | |
328 | return; | |
329 | /* | |
330 | * Set Resource values. | |
331 | */ | |
332 | spin_lock(&iomm_table_lock); | |
b58b7f98 | 333 | bar_res->start = BASE_IO_MEMORY + |
1da177e4 | 334 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
1da177e4 LT |
335 | bar_res->end = bar_res->start + bar_size - 1; |
336 | /* | |
337 | * Allocate the number of table entries needed for BAR. | |
338 | */ | |
339 | while (bar_size > 0 ) { | |
d7b41b1f | 340 | iomm_table[current_iomm_table_entry] = dn; |
885b86e4 | 341 | ds_addr_table[current_iomm_table_entry] = |
d7b41b1f | 342 | iseries_ds_addr(dn) | (bar_num << 24); |
1da177e4 LT |
343 | bar_size -= IOMM_TABLE_ENTRY_SIZE; |
344 | ++current_iomm_table_entry; | |
345 | } | |
346 | max_io_memory = BASE_IO_MEMORY + | |
b58b7f98 | 347 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
1da177e4 LT |
348 | spin_unlock(&iomm_table_lock); |
349 | } | |
350 | ||
351 | /* | |
352 | * allocate_device_bars | |
353 | * | |
354 | * - Allocates ALL pci_dev BAR's and updates the resources with the | |
355 | * BAR value. BARS with zero length will have the resources | |
356 | * The HvCallPci_getBarParms is used to get the size of the BAR | |
357 | * space. It calls iomm_table_allocate_entry to allocate | |
358 | * each entry. | |
359 | * - Loops through The Bar resources(0 - 5) including the ROM | |
360 | * is resource(6). | |
361 | */ | |
1e105904 | 362 | static void __init allocate_device_bars(struct pci_dev *dev) |
1da177e4 | 363 | { |
1da177e4 LT |
364 | int bar_num; |
365 | ||
b58b7f98 | 366 | for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) |
1da177e4 | 367 | iomm_table_allocate_entry(dev, bar_num); |
1da177e4 LT |
368 | } |
369 | ||
370 | /* | |
371 | * Log error information to system console. | |
372 | * Filter out the device not there errors. | |
373 | * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx | |
374 | * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx | |
375 | * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx | |
376 | */ | |
7a73bd7f SR |
377 | static void pci_log_error(char *error, int bus, int subbus, |
378 | int agent, int hv_res) | |
1da177e4 | 379 | { |
7a73bd7f | 380 | if (hv_res == 0x0302) |
1da177e4 LT |
381 | return; |
382 | printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", | |
7a73bd7f | 383 | error, bus, subbus, agent, hv_res); |
1da177e4 LT |
384 | } |
385 | ||
9103eb7d SR |
386 | /* |
387 | * Look down the chain to find the matching Device Device | |
388 | */ | |
7a73bd7f | 389 | static struct device_node *find_device_node(int bus, int devfn) |
9103eb7d SR |
390 | { |
391 | struct device_node *node; | |
392 | ||
393 | for (node = NULL; (node = of_find_all_nodes(node)); ) { | |
394 | struct pci_dn *pdn = PCI_DN(node); | |
395 | ||
396 | if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn)) | |
397 | return node; | |
398 | } | |
399 | return NULL; | |
400 | } | |
401 | ||
1da177e4 | 402 | /* |
50c9bc2f BH |
403 | * iSeries_pcibios_fixup_resources |
404 | * | |
405 | * Fixes up all resources for devices | |
1da177e4 | 406 | */ |
50c9bc2f | 407 | void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev) |
1da177e4 | 408 | { |
50c9bc2f BH |
409 | const u32 *agent; |
410 | const u32 *sub_bus; | |
411 | unsigned char bus = pdev->bus->number; | |
252e75a5 | 412 | struct device_node *node; |
50c9bc2f BH |
413 | int i; |
414 | ||
d7b41b1f | 415 | node = pci_device_to_OF_node(pdev); |
50c9bc2f BH |
416 | pr_debug("PCI: iSeries %s, pdev %p, node %p\n", |
417 | pci_name(pdev), pdev, node); | |
418 | if (!node) { | |
419 | printk("PCI: %s disabled, device tree entry not found !\n", | |
420 | pci_name(pdev)); | |
421 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
422 | pdev->resource[i].flags = 0; | |
423 | return; | |
424 | } | |
425 | sub_bus = of_get_property(node, "linux,subbus", NULL); | |
426 | agent = of_get_property(node, "linux,agent-id", NULL); | |
427 | if (agent && sub_bus) { | |
428 | u8 irq = iSeries_allocate_IRQ(bus, 0, *sub_bus); | |
429 | int err; | |
430 | ||
431 | err = HvCallXm_connectBusUnit(bus, *sub_bus, *agent, irq); | |
432 | if (err) | |
433 | pci_log_error("Connect Bus Unit", | |
434 | bus, *sub_bus, *agent, err); | |
435 | else { | |
436 | err = HvCallPci_configStore8(bus, *sub_bus, | |
53761746 | 437 | *agent, PCI_INTERRUPT_LINE, irq); |
50c9bc2f BH |
438 | if (err) |
439 | pci_log_error("PciCfgStore Irq Failed!", | |
53761746 | 440 | bus, *sub_bus, *agent, err); |
50c9bc2f BH |
441 | else |
442 | pdev->irq = irq; | |
3f178632 | 443 | } |
1da177e4 | 444 | } |
50c9bc2f | 445 | |
50c9bc2f BH |
446 | allocate_device_bars(pdev); |
447 | iseries_device_information(pdev, bus, *sub_bus); | |
50c9bc2f BH |
448 | } |
449 | ||
450 | /* | |
451 | * iSeries_pci_final_fixup(void) | |
452 | */ | |
453 | void __init iSeries_pci_final_fixup(void) | |
454 | { | |
455 | /* Fix up at the device node and pci_dev relationship */ | |
456 | mf_display_src(0xC9000100); | |
1da177e4 LT |
457 | iSeries_activate_IRQs(); |
458 | mf_display_src(0xC9000200); | |
459 | } | |
460 | ||
1da177e4 LT |
461 | /* |
462 | * Config space read and write functions. | |
463 | * For now at least, we look for the device node for the bus and devfn | |
464 | * that we are asked to access. It may be possible to translate the devfn | |
465 | * to a subbus and deviceid more directly. | |
466 | */ | |
467 | static u64 hv_cfg_read_func[4] = { | |
468 | HvCallPciConfigLoad8, HvCallPciConfigLoad16, | |
469 | HvCallPciConfigLoad32, HvCallPciConfigLoad32 | |
470 | }; | |
471 | ||
472 | static u64 hv_cfg_write_func[4] = { | |
473 | HvCallPciConfigStore8, HvCallPciConfigStore16, | |
474 | HvCallPciConfigStore32, HvCallPciConfigStore32 | |
475 | }; | |
476 | ||
477 | /* | |
478 | * Read PCI config space | |
479 | */ | |
480 | static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, | |
481 | int offset, int size, u32 *val) | |
482 | { | |
7a73bd7f | 483 | struct device_node *node = find_device_node(bus->number, devfn); |
1da177e4 LT |
484 | u64 fn; |
485 | struct HvCallPci_LoadReturn ret; | |
486 | ||
487 | if (node == NULL) | |
488 | return PCIBIOS_DEVICE_NOT_FOUND; | |
489 | if (offset > 255) { | |
490 | *val = ~0; | |
491 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
492 | } | |
493 | ||
494 | fn = hv_cfg_read_func[(size - 1) & 3]; | |
20f48ccf | 495 | HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0); |
1da177e4 LT |
496 | |
497 | if (ret.rc != 0) { | |
498 | *val = ~0; | |
499 | return PCIBIOS_DEVICE_NOT_FOUND; /* or something */ | |
500 | } | |
501 | ||
502 | *val = ret.value; | |
503 | return 0; | |
504 | } | |
505 | ||
506 | /* | |
507 | * Write PCI config space | |
508 | */ | |
509 | ||
510 | static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, | |
511 | int offset, int size, u32 val) | |
512 | { | |
7a73bd7f | 513 | struct device_node *node = find_device_node(bus->number, devfn); |
1da177e4 LT |
514 | u64 fn; |
515 | u64 ret; | |
516 | ||
517 | if (node == NULL) | |
518 | return PCIBIOS_DEVICE_NOT_FOUND; | |
519 | if (offset > 255) | |
520 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
521 | ||
522 | fn = hv_cfg_write_func[(size - 1) & 3]; | |
20f48ccf | 523 | ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0); |
1da177e4 LT |
524 | |
525 | if (ret != 0) | |
526 | return PCIBIOS_DEVICE_NOT_FOUND; | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
531 | static struct pci_ops iSeries_pci_ops = { | |
532 | .read = iSeries_pci_read_config, | |
533 | .write = iSeries_pci_write_config | |
534 | }; | |
535 | ||
536 | /* | |
537 | * Check Return Code | |
538 | * -> On Failure, print and log information. | |
539 | * Increment Retry Count, if exceeds max, panic partition. | |
1da177e4 LT |
540 | * |
541 | * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234 | |
542 | * PCI: Device 23.90 ReadL Retry( 1) | |
543 | * PCI: Device 23.90 ReadL Retry Successful(1) | |
544 | */ | |
7a73bd7f | 545 | static int check_return_code(char *type, struct device_node *dn, |
a2ebaf25 | 546 | int *retry, u64 ret) |
1da177e4 LT |
547 | { |
548 | if (ret != 0) { | |
7a73bd7f | 549 | struct pci_dn *pdn = PCI_DN(dn); |
252e75a5 | 550 | |
a2ebaf25 | 551 | (*retry)++; |
1da177e4 | 552 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", |
7a73bd7f | 553 | type, pdn->busno, pdn->devfn, |
a2ebaf25 | 554 | *retry, (int)ret); |
1da177e4 LT |
555 | /* |
556 | * Bump the retry and check for retry count exceeded. | |
557 | * If, Exceeded, panic the system. | |
558 | */ | |
b9b1812c SR |
559 | if (((*retry) > PCI_RETRY_MAX) && |
560 | (limit_pci_retries > 0)) { | |
1da177e4 | 561 | mf_display_src(0xB6000103); |
a2ebaf25 | 562 | panic_timeout = 0; |
1da177e4 LT |
563 | panic("PCI: Hardware I/O Error, SRC B6000103, " |
564 | "Automatic Reboot Disabled.\n"); | |
565 | } | |
566 | return -1; /* Retry Try */ | |
567 | } | |
a2ebaf25 | 568 | return 0; |
1da177e4 LT |
569 | } |
570 | ||
571 | /* | |
572 | * Translate the I/O Address into a device node, bar, and bar offset. | |
573 | * Note: Make sure the passed variable end up on the stack to avoid | |
574 | * the exposure of being device global. | |
575 | */ | |
252e75a5 | 576 | static inline struct device_node *xlate_iomm_address( |
7a73bd7f | 577 | const volatile void __iomem *addr, |
0d416f2a | 578 | u64 *dsaptr, u64 *bar_offset, const char *func) |
1da177e4 | 579 | { |
7a73bd7f SR |
580 | unsigned long orig_addr; |
581 | unsigned long base_addr; | |
582 | unsigned long ind; | |
583 | struct device_node *dn; | |
1da177e4 | 584 | |
7a73bd7f | 585 | orig_addr = (unsigned long __force)addr; |
0d416f2a SR |
586 | if ((orig_addr < BASE_IO_MEMORY) || (orig_addr >= max_io_memory)) { |
587 | static unsigned long last_jiffies; | |
588 | static int num_printed; | |
589 | ||
59861bc6 | 590 | if (time_after(jiffies, last_jiffies + 60 * HZ)) { |
0d416f2a SR |
591 | last_jiffies = jiffies; |
592 | num_printed = 0; | |
593 | } | |
594 | if (num_printed++ < 10) | |
595 | printk(KERN_ERR | |
596 | "iSeries_%s: invalid access at IO address %p\n", | |
597 | func, addr); | |
1da177e4 | 598 | return NULL; |
0d416f2a | 599 | } |
7a73bd7f SR |
600 | base_addr = orig_addr - BASE_IO_MEMORY; |
601 | ind = base_addr / IOMM_TABLE_ENTRY_SIZE; | |
602 | dn = iomm_table[ind]; | |
603 | ||
604 | if (dn != NULL) { | |
885b86e4 | 605 | *dsaptr = ds_addr_table[ind]; |
7a73bd7f | 606 | *bar_offset = base_addr % IOMM_TABLE_ENTRY_SIZE; |
1da177e4 | 607 | } else |
7a73bd7f SR |
608 | panic("PCI: Invalid PCI IO address detected!\n"); |
609 | return dn; | |
1da177e4 LT |
610 | } |
611 | ||
612 | /* | |
613 | * Read MM I/O Instructions for the iSeries | |
614 | * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal | |
4cb3cee0 | 615 | * else, data is returned in Big Endian format. |
1da177e4 | 616 | */ |
34489388 | 617 | static u8 iseries_readb(const volatile void __iomem *addr) |
1da177e4 | 618 | { |
7a73bd7f | 619 | u64 bar_offset; |
1da177e4 | 620 | u64 dsa; |
a2ebaf25 | 621 | int retry = 0; |
1da177e4 | 622 | struct HvCallPci_LoadReturn ret; |
7a73bd7f | 623 | struct device_node *dn = |
0d416f2a | 624 | xlate_iomm_address(addr, &dsa, &bar_offset, "read_byte"); |
1da177e4 | 625 | |
0d416f2a | 626 | if (dn == NULL) |
1da177e4 | 627 | return 0xff; |
1da177e4 | 628 | do { |
7a73bd7f SR |
629 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, bar_offset, 0); |
630 | } while (check_return_code("RDB", dn, &retry, ret.rc) != 0); | |
1da177e4 | 631 | |
4cb3cee0 | 632 | return ret.value; |
1da177e4 | 633 | } |
1da177e4 | 634 | |
34489388 | 635 | static u16 iseries_readw_be(const volatile void __iomem *addr) |
1da177e4 | 636 | { |
7a73bd7f | 637 | u64 bar_offset; |
1da177e4 | 638 | u64 dsa; |
a2ebaf25 | 639 | int retry = 0; |
1da177e4 | 640 | struct HvCallPci_LoadReturn ret; |
7a73bd7f | 641 | struct device_node *dn = |
0d416f2a | 642 | xlate_iomm_address(addr, &dsa, &bar_offset, "read_word"); |
1da177e4 | 643 | |
0d416f2a | 644 | if (dn == NULL) |
1da177e4 | 645 | return 0xffff; |
1da177e4 | 646 | do { |
1da177e4 | 647 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, |
7a73bd7f SR |
648 | bar_offset, 0); |
649 | } while (check_return_code("RDW", dn, &retry, ret.rc) != 0); | |
1da177e4 | 650 | |
4cb3cee0 | 651 | return ret.value; |
1da177e4 | 652 | } |
1da177e4 | 653 | |
34489388 | 654 | static u32 iseries_readl_be(const volatile void __iomem *addr) |
1da177e4 | 655 | { |
7a73bd7f | 656 | u64 bar_offset; |
1da177e4 | 657 | u64 dsa; |
a2ebaf25 | 658 | int retry = 0; |
1da177e4 | 659 | struct HvCallPci_LoadReturn ret; |
7a73bd7f | 660 | struct device_node *dn = |
0d416f2a | 661 | xlate_iomm_address(addr, &dsa, &bar_offset, "read_long"); |
1da177e4 | 662 | |
0d416f2a | 663 | if (dn == NULL) |
1da177e4 | 664 | return 0xffffffff; |
1da177e4 | 665 | do { |
1da177e4 | 666 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, |
7a73bd7f SR |
667 | bar_offset, 0); |
668 | } while (check_return_code("RDL", dn, &retry, ret.rc) != 0); | |
1da177e4 | 669 | |
4cb3cee0 | 670 | return ret.value; |
1da177e4 | 671 | } |
1da177e4 LT |
672 | |
673 | /* | |
674 | * Write MM I/O Instructions for the iSeries | |
675 | * | |
1da177e4 | 676 | */ |
34489388 | 677 | static void iseries_writeb(u8 data, volatile void __iomem *addr) |
1da177e4 | 678 | { |
7a73bd7f | 679 | u64 bar_offset; |
1da177e4 | 680 | u64 dsa; |
a2ebaf25 | 681 | int retry = 0; |
1da177e4 | 682 | u64 rc; |
7a73bd7f | 683 | struct device_node *dn = |
0d416f2a | 684 | xlate_iomm_address(addr, &dsa, &bar_offset, "write_byte"); |
1da177e4 | 685 | |
0d416f2a | 686 | if (dn == NULL) |
1da177e4 | 687 | return; |
1da177e4 | 688 | do { |
7a73bd7f SR |
689 | rc = HvCall4(HvCallPciBarStore8, dsa, bar_offset, data, 0); |
690 | } while (check_return_code("WWB", dn, &retry, rc) != 0); | |
1da177e4 | 691 | } |
1da177e4 | 692 | |
34489388 | 693 | static void iseries_writew_be(u16 data, volatile void __iomem *addr) |
1da177e4 | 694 | { |
7a73bd7f | 695 | u64 bar_offset; |
1da177e4 | 696 | u64 dsa; |
a2ebaf25 | 697 | int retry = 0; |
1da177e4 | 698 | u64 rc; |
7a73bd7f | 699 | struct device_node *dn = |
0d416f2a | 700 | xlate_iomm_address(addr, &dsa, &bar_offset, "write_word"); |
1da177e4 | 701 | |
0d416f2a | 702 | if (dn == NULL) |
1da177e4 | 703 | return; |
1da177e4 | 704 | do { |
7a73bd7f SR |
705 | rc = HvCall4(HvCallPciBarStore16, dsa, bar_offset, data, 0); |
706 | } while (check_return_code("WWW", dn, &retry, rc) != 0); | |
1da177e4 | 707 | } |
1da177e4 | 708 | |
34489388 | 709 | static void iseries_writel_be(u32 data, volatile void __iomem *addr) |
1da177e4 | 710 | { |
7a73bd7f | 711 | u64 bar_offset; |
1da177e4 | 712 | u64 dsa; |
a2ebaf25 | 713 | int retry = 0; |
1da177e4 | 714 | u64 rc; |
7a73bd7f | 715 | struct device_node *dn = |
0d416f2a | 716 | xlate_iomm_address(addr, &dsa, &bar_offset, "write_long"); |
1da177e4 | 717 | |
0d416f2a | 718 | if (dn == NULL) |
1da177e4 | 719 | return; |
1da177e4 | 720 | do { |
7a73bd7f SR |
721 | rc = HvCall4(HvCallPciBarStore32, dsa, bar_offset, data, 0); |
722 | } while (check_return_code("WWL", dn, &retry, rc) != 0); | |
1da177e4 | 723 | } |
caf81329 | 724 | |
4cb3cee0 | 725 | static u16 iseries_readw(const volatile void __iomem *addr) |
caf81329 | 726 | { |
34489388 | 727 | return le16_to_cpu(iseries_readw_be(addr)); |
caf81329 | 728 | } |
caf81329 | 729 | |
4cb3cee0 | 730 | static u32 iseries_readl(const volatile void __iomem *addr) |
caf81329 | 731 | { |
34489388 | 732 | return le32_to_cpu(iseries_readl_be(addr)); |
caf81329 | 733 | } |
caf81329 | 734 | |
4cb3cee0 | 735 | static void iseries_writew(u16 data, volatile void __iomem *addr) |
caf81329 | 736 | { |
34489388 | 737 | iseries_writew_be(cpu_to_le16(data), addr); |
caf81329 | 738 | } |
caf81329 | 739 | |
4cb3cee0 | 740 | static void iseries_writel(u32 data, volatile void __iomem *addr) |
caf81329 | 741 | { |
34489388 | 742 | iseries_writel(cpu_to_le32(data), addr); |
caf81329 | 743 | } |
caf81329 | 744 | |
4cb3cee0 BH |
745 | static void iseries_readsb(const volatile void __iomem *addr, void *buf, |
746 | unsigned long count) | |
caf81329 | 747 | { |
4cb3cee0 BH |
748 | u8 *dst = buf; |
749 | while(count-- > 0) | |
34489388 | 750 | *(dst++) = iseries_readb(addr); |
caf81329 | 751 | } |
caf81329 | 752 | |
4cb3cee0 BH |
753 | static void iseries_readsw(const volatile void __iomem *addr, void *buf, |
754 | unsigned long count) | |
caf81329 | 755 | { |
4cb3cee0 BH |
756 | u16 *dst = buf; |
757 | while(count-- > 0) | |
34489388 | 758 | *(dst++) = iseries_readw_be(addr); |
caf81329 | 759 | } |
caf81329 | 760 | |
4cb3cee0 BH |
761 | static void iseries_readsl(const volatile void __iomem *addr, void *buf, |
762 | unsigned long count) | |
caf81329 | 763 | { |
4cb3cee0 BH |
764 | u32 *dst = buf; |
765 | while(count-- > 0) | |
34489388 | 766 | *(dst++) = iseries_readl_be(addr); |
caf81329 | 767 | } |
caf81329 | 768 | |
4cb3cee0 BH |
769 | static void iseries_writesb(volatile void __iomem *addr, const void *buf, |
770 | unsigned long count) | |
caf81329 | 771 | { |
4cb3cee0 BH |
772 | const u8 *src = buf; |
773 | while(count-- > 0) | |
34489388 | 774 | iseries_writeb(*(src++), addr); |
caf81329 | 775 | } |
caf81329 | 776 | |
4cb3cee0 BH |
777 | static void iseries_writesw(volatile void __iomem *addr, const void *buf, |
778 | unsigned long count) | |
caf81329 | 779 | { |
4cb3cee0 BH |
780 | const u16 *src = buf; |
781 | while(count-- > 0) | |
34489388 | 782 | iseries_writew_be(*(src++), addr); |
caf81329 | 783 | } |
caf81329 | 784 | |
4cb3cee0 BH |
785 | static void iseries_writesl(volatile void __iomem *addr, const void *buf, |
786 | unsigned long count) | |
caf81329 | 787 | { |
4cb3cee0 BH |
788 | const u32 *src = buf; |
789 | while(count-- > 0) | |
34489388 | 790 | iseries_writel_be(*(src++), addr); |
caf81329 | 791 | } |
caf81329 | 792 | |
4cb3cee0 BH |
793 | static void iseries_memset_io(volatile void __iomem *addr, int c, |
794 | unsigned long n) | |
caf81329 | 795 | { |
4cb3cee0 | 796 | volatile char __iomem *d = addr; |
caf81329 | 797 | |
4cb3cee0 | 798 | while (n-- > 0) |
34489388 | 799 | iseries_writeb(c, d++); |
caf81329 | 800 | } |
caf81329 | 801 | |
4cb3cee0 BH |
802 | static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src, |
803 | unsigned long n) | |
caf81329 | 804 | { |
4cb3cee0 BH |
805 | char *d = dest; |
806 | const volatile char __iomem *s = src; | |
caf81329 | 807 | |
4cb3cee0 | 808 | while (n-- > 0) |
34489388 | 809 | *d++ = iseries_readb(s++); |
caf81329 | 810 | } |
caf81329 | 811 | |
4cb3cee0 BH |
812 | static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src, |
813 | unsigned long n) | |
caf81329 | 814 | { |
4cb3cee0 BH |
815 | const char *s = src; |
816 | volatile char __iomem *d = dest; | |
caf81329 | 817 | |
4cb3cee0 | 818 | while (n-- > 0) |
34489388 | 819 | iseries_writeb(*s++, d++); |
caf81329 | 820 | } |
caf81329 | 821 | |
4cb3cee0 BH |
822 | /* We only set MMIO ops. The default PIO ops will be default |
823 | * to the MMIO ops + pci_io_base which is 0 on iSeries as | |
824 | * expected so both should work. | |
825 | * | |
826 | * Note that we don't implement the readq/writeq versions as | |
827 | * I don't know of an HV call for doing so. Thus, the default | |
828 | * operation will be used instead, which will fault a the value | |
829 | * return by iSeries for MMIO addresses always hits a non mapped | |
830 | * area. This is as good as the BUG() we used to have there. | |
831 | */ | |
832 | static struct ppc_pci_io __initdata iseries_pci_io = { | |
833 | .readb = iseries_readb, | |
834 | .readw = iseries_readw, | |
835 | .readl = iseries_readl, | |
836 | .readw_be = iseries_readw_be, | |
837 | .readl_be = iseries_readl_be, | |
838 | .writeb = iseries_writeb, | |
839 | .writew = iseries_writew, | |
840 | .writel = iseries_writel, | |
841 | .writew_be = iseries_writew_be, | |
842 | .writel_be = iseries_writel_be, | |
843 | .readsb = iseries_readsb, | |
844 | .readsw = iseries_readsw, | |
845 | .readsl = iseries_readsl, | |
846 | .writesb = iseries_writesb, | |
847 | .writesw = iseries_writesw, | |
848 | .writesl = iseries_writesl, | |
849 | .memset_io = iseries_memset_io, | |
850 | .memcpy_fromio = iseries_memcpy_fromio, | |
851 | .memcpy_toio = iseries_memcpy_toio, | |
852 | }; | |
caf81329 | 853 | |
4cb3cee0 BH |
854 | /* |
855 | * iSeries_pcibios_init | |
856 | * | |
857 | * Description: | |
858 | * This function checks for all possible system PCI host bridges that connect | |
859 | * PCI buses. The system hypervisor is queried as to the guest partition | |
860 | * ownership status. A pci_controller is built for any bus which is partially | |
861 | * owned or fully owned by this guest partition. | |
862 | */ | |
863 | void __init iSeries_pcibios_init(void) | |
caf81329 | 864 | { |
4cb3cee0 BH |
865 | struct pci_controller *phb; |
866 | struct device_node *root = of_find_node_by_path("/"); | |
867 | struct device_node *node = NULL; | |
caf81329 | 868 | |
4cb3cee0 BH |
869 | /* Install IO hooks */ |
870 | ppc_pci_io = iseries_pci_io; | |
caf81329 | 871 | |
9ccc4fd2 SR |
872 | pci_probe_only = 1; |
873 | ||
3d5134ee BH |
874 | /* iSeries has no IO space in the common sense, it needs to set |
875 | * the IO base to 0 | |
876 | */ | |
877 | pci_io_base = 0; | |
878 | ||
4cb3cee0 BH |
879 | if (root == NULL) { |
880 | printk(KERN_CRIT "iSeries_pcibios_init: can't find root " | |
881 | "of device tree\n"); | |
882 | return; | |
883 | } | |
884 | while ((node = of_get_next_child(root, node)) != NULL) { | |
885 | HvBusNumber bus; | |
886 | const u32 *busp; | |
caf81329 | 887 | |
4cb3cee0 BH |
888 | if ((node->type == NULL) || (strcmp(node->type, "pci") != 0)) |
889 | continue; | |
caf81329 | 890 | |
e2eb6392 | 891 | busp = of_get_property(node, "bus-range", NULL); |
4cb3cee0 BH |
892 | if (busp == NULL) |
893 | continue; | |
894 | bus = *busp; | |
895 | printk("bus %d appears to exist\n", bus); | |
896 | phb = pcibios_alloc_controller(node); | |
897 | if (phb == NULL) | |
898 | continue; | |
6207e816 SR |
899 | /* All legacy iSeries PHBs are in domain zero */ |
900 | phb->global_number = 0; | |
caf81329 | 901 | |
4cb3cee0 BH |
902 | phb->first_busno = bus; |
903 | phb->last_busno = bus; | |
904 | phb->ops = &iSeries_pci_ops; | |
50c9bc2f BH |
905 | phb->io_base_virt = (void __iomem *)_IO_BASE; |
906 | phb->io_resource.flags = IORESOURCE_IO; | |
907 | phb->io_resource.start = BASE_IO_MEMORY; | |
908 | phb->io_resource.end = END_IO_MEMORY; | |
909 | phb->io_resource.name = "iSeries PCI IO"; | |
910 | phb->mem_resources[0].flags = IORESOURCE_MEM; | |
911 | phb->mem_resources[0].start = BASE_IO_MEMORY; | |
912 | phb->mem_resources[0].end = END_IO_MEMORY; | |
913 | phb->mem_resources[0].name = "Series PCI MEM"; | |
4cb3cee0 | 914 | } |
caf81329 | 915 | |
4cb3cee0 | 916 | of_node_put(root); |
caf81329 | 917 | |
4cb3cee0 | 918 | pci_devs_phb_init(); |
caf81329 | 919 | } |
4cb3cee0 | 920 |